Efficient Checking of Power Delivery Integrity for Power Gating

Transcription

1 Efficient Checking of Power Delivery Integrity for Power Gating Zhiyu Zeng Texas A&M University Zhuo Feng Michig an Technological Un iversity Peng Li Texas A&M University Abstract Multi-core architecture has emerged as the primary architectural choice to achieve power-efficient computing in microprocessors and SoCs. Power gating is indispensable for system power and thermal management and well suited for multi-core architectures. However, checking the power integrity (such as electromigration and voltage drop) of large gated power delivery networks (PDNs) presents a significant challenge due to the sheer die-package network complexity and the existence of an extremely large number of possible gating and operation configurations. We propose a simulation-based checking methodology that encompasses a comprehensive set of essential checking tasks. We tackle the challenges brought by the large checking space by developing strategies that efficiently identify top-ranked worstcase operating conditions, which are sequentially analyzed through a well-controlled number of full simulations for fidelity. We demonstrate the superior performance of the proposed approach on large power gating checking problems that are completely intractable to brute-force methods. approach for the global grid is proposed which can efficiently compute exact DC currents for all possible power gating configurations. Whereas, in the more complicated transient checking of gated power grid networks, a number of complications arise, such as new transient noise behaviors, the handling of transient superposition under multiple sleep transistors per local grid, and the need to verify both the global and local grids. On the other hand, since there exists a very large checking space consisting of all possible power gating configurations and transitions, a brute-force exhaustive enumeration over all possible configurations is impractical. This work is motivated by the need to ensure power integrity in power-gated delivery networks and the challenges associated with checking such complex networks. The task is to check whether power integrity constraints (e.g. EM and voltage drop) are met under all possible power gating and transition modes. To carry out the checking tasks, we propose a practical simulation-based approach which achieves efficient checking by identifying one or several worst-case voltage drop and EM violations, the corresponding power gating configurations and power-on transitions. In recognizing the critical role circuit transients play in power integrity associated with aggressive power gating, we perform the transient checking on both global and local grids under a rather general hierarchical topology of gated power delivery. Our main contributions include: 1. Introduction In the last several years, multi-core architecture has emerged as the primary architectural-level choice to achieve powerefficient computing in microprocessors and SoCs. This trend has manifested in a number of multi-core or many-core processor offerings from major vendors [1, 2]. Power gating is 1. We develop a comprehensive strategy that checks the indispensable in controlling system power consumption and complete power delivery hierarchy (local and global grids), under all possible stable power gating configurations well suited for multi-core architectures [3, 4]. Gated PDN ch eck in g is a ver y im p o r tan t bu t ch allen and g - core power-on noise injection in terms of EM and ing task to chip designers. It can be defined as: for a given peak dynamic voltage drops. loading current distribution for each core, check/verify if the gated PDN can satisfy given electromigration (EM) and voltage drop specifications under all possible on/off configurations and on/off transitions. In [5], a useful DC EM analysis 2. We achieve the feasibility of checking by developing fast equivalent circuit modeling and superposition methods for approximate and conservative identification of worstcase violations in the large checking space, followed by selective full-simulation validation. 2. Background and Overview 2.1 Power-Gated PDN Circuit Models The modeling of a die-package PDN with power gating is shown in Fig. 1. Without loss of generality, it is assumed that only the header sleep transistors are used for power gating /11/$ IEEE th Int'l Symposium on Quality Electronic Design

2 gulator Voltage Reg + Package PDN sleep transistor l G Gated Local Grid Non Gated Local Grid On Die PDN Figure 1. Die-package power-gated PDN model (with only one pair of VDD/GND pins shown). The PDN model consists of two components: the package model and on-die model. The package model captures the parasitics of the package and on-board PDN that connect the on-die PDN with onboard voltage regulator through multiple VDD/GND pins. A variety of distributed, lumped or macromodels can be used to model the package. A simple lumped package model for a pair of VDD/GND pins is shown in Fig. 1. The on-die PDN has the following major components: a global VDD grid, ungated local grids, gated local grids, a global GND grid, decoupling capacitors and switching transistors, as well as sleep transistors for power gating. The global VDD grid distributes the power to ungated local grids through vias and to gated local grids through multiple sleep transistors. The dynamic current sources are generally approximated with triangular waveforms. When a sleep transistor is completely turned on, it is modeled as a resistor with small resistance, otherwise, it is treated as an open circuit. During the power-on process, due to the charging effect of the decoupling capacitors, sleep transistors are working in saturation and linear regions in different phases. Hence, sleep transistors can be modeled as time-varying resistors during the power-on process. 2.2 Checking Metrics We define important electromigration (EM) and dynamic voltage drops (DVD) metrics for interconnects and switching transistors, respectively, in our transient checking task. We use average currents to define the EM metric [6] and peak DVD for dynamic voltage drop metric [7]. For a wire w m with transient current I m (t), the EM metric is given as t2 t EM m = 1 I m (t)dt t 2 t 1. (1) For a transistor T n connected between V DDn (t) and V SSn (t), the peak DVD is defined as DV D Pn = max {V DD V DDn (t)+v SSn (t)}. (2) t 1 t t Checking Tasks In a gated multi-core power delivery network, each local grid has four possible states: sleep, active, transition, and idle. In the sleep state, the sleep transistors are completely turned off. In the active state, the sleep transistors are completely turned on and the switching transistors are working steadily. In the transition state, the sleep transistors are gradually turned on while the decoupling capacitors are being charged, but the switching transistors are in idle. Finally, in the idle state, the sleep transistors are completely turned on while the switching transistors are still in idle. In this work, the idle state is not explicitly considered, since it can be considered active by modeling leakage currents. For local grid G k, its state is represented by b k (0 for sleep state; 1 for active state 2 for transition state; 3 for idle state). active sleep transition Stable Configuration Transition Configuration Figure 2. Stable and transition configurations. A power gating configuration is a combination of the above possible states of gated local grids. Two kinds of power gating configurations are examined in this work: 1. Stable configuration: as shown in Fig. 2, each gated local grid is either in the active state or sleep state. Assume there are N independent gated local grids G 1,...,G N. A stable configuration C i can be represented as C i = {b 1i,b 2i,...,b Ni}, b ki =0, 1; k =1,...,N, (3) where b ki is the state of grid G k. 2. Transition configuration: some gated local grids are in the transition state while others are either in the active or sleep state. Similarly, a transition configuration D j can be represented by D j = {b 1j,b 2j,...,b Nj}, b kj =0, 1, 2; k =1,...,N, (4) As summarized in Fig. 3, the proposed checking tasks are categorized into stable mode checking and power-on checking. 1. In the stable mode checking, the mission is to find the worst or near-worst case dynamic performance (the largest EM and peak DVD values) of the PDN under all possible stable configurations. We capture both the time averaging and temporal effects by checking EM effects and peak DVD constraints. Moreover, interconnect EM metrics in both the global and local grids are checked. However, it is only necessary to perform peak DVD checks for local grids, where switching transistors reside and fluctuations of the supply level influence the timing performance of the circuit.

3 Global Grids Stable Mode Checking Power Gating Checking Power on Checking EM DVD P DVD P Local Grids Figure 3. Proposed checking tasks. 2. In the power-on checking, the worst or near-worst case dynamic performance under all possible transition configurations is identified. The goal is to determine when coupled with stable workloads from other cores, whether or not the power-on current transients will jeopardize power delivery integrity (the peak DVD value). 2.4 Overview of the Proposed Checking Methodology With current loadings (the starting times of all current loadings are fixed) given for each local grid, according to (3) and (4), a PDN with N gated local grids, or cores, has 2 N stable configurations and 3 N 2 N transition configurations. A brute-force exhaustive checking would require at least 2 N lengthy die-package PDN transient simulations, each covering at least hundreds of clock cycles to capture the dynamics of the network. Hence, the brute-force approach is simply infeasible. To achieve the feasibility and efficiency, in this work, we propose novel techniques to drastically reduce the number of full simulations from 2 N or even more to O(N). Ourmethods develop an equivalent circuit modeling scheme, which makes superposition being able to be used for efficient approximations for all power gating configurations. These approximations are obtained by fully simulating O(N) number of configurations, whose contributions are superimposed to find out several configurations (also in the order of O(N)) that can potentially cause the worst-case circuit performance. Those configurations are called worst case candidates in the paper. Then, this set of worst-case configuration candidates are fully simulated, and their dynamic metrics are obtained. The worst or near-worst case performances for the PDN under the stable and transition configurations therefore can be found. As can be seen, the proposed process can significantly reduce the computation complexity from O(2 N ) to O(N). 3. Stable-Mode EM Checking The stable-mode EM checking is to find the largest average current, for a wire in the on-die PDN, under all possible stable configurations. 3.1 Stable-Mode EM Checking for Global Grids Challenges for Transient EM Checking Superposition method is employed in the DC EM analysis for a simple gated power grid in [5]. In this work, a more general and complex PDN model is used. Meanwhile, we consider the more meaningful transient dynamics for gated PDNs. However, the above leads to three key difficulties for employing superposition theory. The existence of decoupling capacitances as well as the package makes the entire PDN a strongly coupled system. Therefore, finding a clear cut for the inputs to the system is difficult. Since multiple sleep transistors are used for each local grid, the change of gating configuration would cause redistribution of the currents through sleep transistors. For the transient analysis, there are currents flowing through the decoupling capacitances. Due to the resonance caused by the on-die capacitance and the package parasitics, those current values are subject to change when the power gating configuration changes (the total on-die capacitance may change). Although the transient EM analysis for PDNs is challenged by the above difficulties, we develop the following concepts of equivalent circuit modeling and superposition to speedup the checking in the large space of possible gating configurations Superposition Approximations Identifying the circuit to which supposition is applied and the correspondinginputs is crucial in applying superposition technique. If we treat the current loads in each local grid as the inputs and the remaining PDN as the circuit, then, turning on or off the local grids not only changes the inputs, but also changes the circuit. Therefore, in order to maintain the circuit while turning on/off gated local grids, the local grids should be treated as the inputs, and the global grids, c4 bumps and the package are included in the circuit. Since when a local grid is active, it draws currents from or provides currents (through decaps) to the global grids, each local grid can be modeled as a set of switchable time-varying current sources attached to the global grids. As a simple example, in Fig. 4 local grid 1 and 2 are modeled as switchable current sources I 1 (t) and I 2 (t) respectively. Before determining the value for each switchable current source, we define a global basic stable configuration C g i as below (assume there are N independent gated local grids), C g i = {b 1i,b 2i,...,b Ni }, b ii =1, others =0, (5) where only grid G i is active, and others are in sleep. Although the value of each switchable current source I i (t) changes with the configuration alternation, it can be approximated as the time-varying current flowing in or out of the global grids under its corresponding basic configuration C g i.

4 Current Source Modeling Local Grid 1 Local Grid 2 Local Grid 3 I 1 (t) I 2 (t) Figure 4. Switchable current source model for local grids. For simplicity, the package is not shown and there are only three local grids. Superposition Local Grid 1 Local Grid 2 I 3 1(t) I 3 2(t) + = + I m (t) I m1 I m2 Figure 5. Superposition for global grids checking. The immediate benefit of this approximation is that with each local grid modeled as a set of switchable currents with fixed values, the circuit responses on the global grids in any stable configuration C i can be efficiently estimated using the principle of superposition [8]. As shown in Fig. 5, for a wire w m on the global grids under the stable configuration {1, 1}, its current I m (t) can be approximated as I m (t) I m1 (t)+i m2 (t) (6) where I m1 (t) and I m2 (t) are the contributions from two current sources I 1 (t) and I 2 (t). I m1 (t) and I m2 (t) are obtained by simulations of the basic configurations C g 1 = {1, 0} and C g 2 = {0, 1} respectively. In a more general PDN, assume there are N gated local grids (with indices from 1 to N, ungated local grids are counted the same as gated local grids). For wire w m in the global grid, the current contribution from local grid G i can be represented as a time varying variable I mi (t). Applying superposition, the average current (from time t 1 to t 2 )flowing through the wire w m under an arbitrary configuration C k = {b 1k,...,b Nk } can be approximated as N t2 t EM mk EM mk,apx = b 1 I mi (t)dt ik t 2 t 1, (7) where I mi (t) is obtained by fully simulating basic configuration C g i Worst Case Validation As stated above, errors are introduced by approximating the local grids using independent current sources. The configuration that has the EM m,apx max may not be the worstcase configuration. Therefore, a validation scheme is needed. Instead of only selecting the approximate worst-case configuration, a set of configurations, C t1,...,c tp,that correspond to the largest P approximate average currents, EM mt1,apx,..., EM mtp,apx, are selected as the top-p I 3 (t) worst-case EM configuration candidates. The top-p cases can be found by going through all 2 N possible configurations (rank them according to their approximated average currents) and picking up the P configurations that have the largest P approximate average currents. According to the experimental results, the runtime for identifying top-p worst cases is insignificant compared to lengthy die-package transient simulations, thus does not affect the overall complexity of our approach. Next, full simulations are applied to all these P candidate configurations. Finally, the real EM m max is obtained by choosing the largest validated EM mti (i =1...P), and its corresponding stable configuration can also be found. The number P can be increased to cover more possible configurations to assure that the actual EM m max can be identified in the final validation simulations. Usually P is in the order of O(N) andmuchsmaller than 2 N. In contrast to exhaustive enumeration, the presented approach reduces the complexity from O(2 N ) to O(N), leading to significant efficiency improvement. The entire algorithm for stable-mode EM checking is summarized in Algorithm 1. Algorithm 1 Stable-mode EM checking for wire w m in global grids Input: Global basic stable configuration C g 1 Cg N,andthe number of worst-case candidates P. Output: EM m max and its corresponding stable configuration C max. 1: for i 1 to N do 2: Full simulation for the global basic stable configuration C g i. t2 t I 3: I Ai 1 mi (t)dt t 2 t 1 4: end for 5: Obtain P worst-case candidates C t1,...,c tp. 6: for i 1 to P do 7: Full simulation for worst-case candidate C ti. t2 8: EM mti t I ti 1 m (t)dt t 2 t 1. 9: end for 10: EM m max max P EM mti. 11: return EM m max and its configuration as C max. We have discussed how to identify the worst-case EM condition for a single wire. It is important to note that the same principle can be straightforwardly extended to find, say, the worst-case EM condition among all wires on the global grids. The extra handling required is the ranking of the EM metrics among all wires, which doesn t require any additional full circuit simulations. This applies to other types of checking presented in the following subsections. 3.2 Stable-Mode EM Checking for Local Grids A modified approach is taken to perform the EM checking of a wire on a local grid. Under the context of power gating, this also implies that this local grid is always powered on. Similar to the stable-mode EM checking for global grids,

5 Superposition Local Grid 1 I 2 (t) Local Grid 1 I 2 (t) Local Grid 1 = + I m (t) I m2 2(t) I m1 1(t) + I s1 (t) Figure 6. Superposition for local grids checking. in order to apply superposition approach, the circuit and the inputs should be identified. Different from the setup in Fig. 5, since the target of checking is a particular local grid, this local grid is always included in the global PDN circuit as shown in Fig. 6, where the wire of checking is assumed to be in local grid 1. Therefore, the circuit includes the global grids, package, the targeted local grid, and its decoupling capacitors and resistor models for turned-on sleep transistors. As stated in the previous checking, all other local grids are modeled as switchable current sources to circuit.thesecurrent source models as well as the intrinsic current loads at the targeted local grid are treated as inputs.infig.6,whenanalyzing the impact of I 2 (t) on local grid 1,gridG 1 should be considered as in the idle state; the contribution from its own current loads I s1 (t) is computed separately by only having grid G 1 active. Similar to the global basic stable configuration, for a PDN with N independent gated local grids, assume the targeted wire is in local grid G j, a local basic stable configuration Cji l can be defined as, C l ji = {b 1i,b 2i,...,b Ni}, b ji =3,b ii =1, others =0 (8) where grid G j is idle, grid G i is active, and others are in sleep. Generally, assuming the targeted wire w n is on local grid G j, the average current (from t 1 to t 2 ) under the configuration C k = {b 1k,...,b Nk ; b jk =1} is approximated as N;i j t2 b ik t EM nk,apx = 1 I ni(t)dt + t 2 t 1 I nj(t)dt (9) t 2 t 1 where I nj (t) is obtained by simulating global basic configuration C g j,andwheni j, I ni(t) is obtained by simulating local basic configuration C l ji. The procedures of identifying top-p worst-case candidates and the following full simulation validation illustrated in Algorithm 1 can be applied here to find the maximum average current EM n max for wire w n in a local grid. 4. Peak Dynamic Voltage Drop Checking 4.1 Stable-Mode Peak Dynamic Voltage Drop Checking Here, the task is to find the largest peak dynamic voltage drop (DVD) for a transistor in the on-die PDN under all possible stable power gating configurations. It should be noted that the current loadings are assumed to be given. node a Tn node b Local Grid 1 Local Grid 2 Figure 7. Dynamic voltage drop for circuit block T n.for simplicity, the package is not shown. For a simple PDN circuit shown in Fig. 7, a circuit block T n is connected to local grid 1 at node a and to the global GND at node b. Assume the voltages at a and b are V a (t) and V b (t) respectively. The dynamic voltage drops of node a and b can be expressed as, DV D a (t) =V DD V a (t), for VDD grid nodes, (10) DV D b (t) = V b (t), for GND grid nodes. (11) Therefore, the dynamic voltage drop for circuit T n is, DV D n(t) =V DD [V a(t) V b (t)] = DV D a(t) DV D b (t), (12) According to the PDN model in Fig. 1, all the circuit blocks exist between local grids and the global GND grid. Therefore, the voltages of nodes in local grids must be considered in DVD checking, which implies that the targeted local grids should always be on. Since in this case the circuit and inputs categorization is the same as in stable-mode EM checking for local grids, the current source modeling, approximation method, worst-case identification scheme and validation procedure presented in Section 3.2 can be applied here. It should be noted that in order to use the superposition theorem, voltage drop (defined in (10) and (11)) is used here instead of the actual node voltage. In a general PDN with N independent gated local grids, assuming the peak DVD (from t 1 to t 2 )ofacircuitblockt n, which is connected to the node a on local grid G j and and the node b in the global GND grid, is examined. Under the configuration C k = {b 1k,...,b Nk ; b jk =1}, the dynamic voltage drop at node a and b can be approximated by, DV D a,apx (t) = DV D b,apx (t) = N;i j N;i j b ik DV D ai (t)+dv D aj (t) (13) b ik DV D bi (t)+dv D bj (t) (14) where DV D aj (t) and DV D bj (t) are defined in (10) and (11), and are obtained by simulating global basic configuration C g j,andwheni j, DV D ai(t) and DV D bi (t) are obtained by simulating local basic configuration C l ji. Therefore, the peak dynamic voltage drop for T n under configuration C k is approximated as DV D Pn,apx = max {DV D a,apx(t) DV D b,apx (t)} (15) t 1 t t 2

6 Similar to finding the top-p worst-case configuration candidates for stable-mode EM checking, the top-p worstcase configuration candidates for peak DVD checking can also be found. The full simulation validation will be carried out for those candidates to find out the maximum DV D Pn. 4.2 Power-on Peak Dynamic Voltage Drop Checking When a local grid is in transition, although no switching activity has been experienced from the devices powered by the grid yet, large rush currents may be drawn from the global grids to charge the local grid s decoupling capacitors, which are discharged in the sleep state due to leakage. Such current disturbances may propagate through the global grids and cause droops on the power and ground lines of other local grids. For a given turn-on time, the task of power-on peak dynamic voltage drop (DVD) checking is to identify the worst-case peak voltage drop caused by the turn-on noise in conjunction with the noise contributions from all possible stable workloads. For the purpose of illustration, the case in which only one local grid is powered on at a time is examined, as shown in Fig. 8. The cases with multiple power-on local grids can be handled in a similar way. The grid in transition can be modeled as rush current sources which are a part of the inputs to the circuit, thus the superposition technique can be applied for peak DVD approximation. l G rush current l G Approximation Local Grid 1 Local Grid 2 Local Grid 1 I 2 (t) charging Figure 8. Checking of power-on peak dynamic voltage drop. For a general PDN with N independent gated local grids, assume the targeted grid is G j and G s is in transition, we introduce basic transition configuration Cjs t defined as, C t js = {b 1s,b 2s,...,b Ns}, b js =3,b ss =2, others =0 (16) where grid G s is in transition, G j is in idle, and others are in sleep. Assuming the peak DVD (from t 1 to t 2 )ofacircuit block T n, which is connected to the node a on local grid G j and and the node b in the global GND grid, is examined. Local grid G s is in transition. Under the configuration C k = {b 1k,...,b Nk ; b jk =1,b sk =3}, the dynamic voltage drop at node a and b can be approximated by, N ;i j,s DV D a,apx(t) = b ik DV D ai(t)+dv D aj (t)+dv D as(t) (17) N ;i j,s DV D b,apx (t) = b ik DV D bi (t)+dv D bj (t)+dv D as(t) (18) where DV D as (t) and DV D bs (t) are obtained by simulating basic transition configuration C t js, DV D aj(t) and VD bj (t) are obtained by simulating global basic configuration C g j,andwheni j, s, DV D ai(t) and DV D bi (t) are obtained by simulating local basic configuration C l ji. Therefore, the peak dynamic voltage drop for T n under transition configuration C k is approximated as DV D Pn,apx = max {DV D a,apx(t) DV D b,apx (t)} (19) t 1 t t 2 Following Algorithm 1, the DV D Pn,max can be found. Turning off a local grid is equivalent to removing the decoupling capacitance under that local grid from the power delivery network. Using the same current modeling technique, the checking for powering off process can be performed. 5. Experimental Results The transient power gating checking employs a die-package PDN simulator [9] implemented in CUDA [10] and C++. The GPU program is executed on a single GPU of the NIVIDIA Geforce 9800 GX2 card (including two GPUs), with a total on board memory of 512Mb. All the C++ programs are executed on a workstation with Intel Xeon CPU@2.33GHz and 4G RAM running 64-bit Linux OS. The on-chip power grids of PDNs are generated according to the typical current loadings and wire conductance of the IBM power grid benchmarks [11], while the package level model parameters, such as inductance and capacitance values, as well as total on-die capacitance are adopted from [12]. Three power gated million-node PDNs with N gated local grids, N =4, 8, 16 are employed for the transient checking presented in the paper. Each PDN has millions of onchip nodes and a few hundred chip-to-package pins. Each local grid has several blocks with different current loadings to represent different function modules. 200 clock cycles (2000 time steps) are simulated to capture the time averaging and temporal effects (waveforms are stabilized). 5.1 Stable Mode Checking The approximate average currents for nodes in the global grids using the proposed superposition approach, as well as the exact values obtained by full simulation validation (for a PDN with 4 local grids) are presented in Table 1. For this time averaging effect, the approximate values are very close to the exact values. For the node at the corner of the global grid, it is mostly influenced by the local grid under that node, and the impacts from other local grids are much smaller. Thus, the approximate values for the top 8 configurations are close to each other, which makes the determination of their precise ranking difficult. For practical purposes, however, this does not present a real issue because of the closeness of values for these configurations. On the other hand, for the node in the center, the impacts from all 4 grids are similar, therefore, the ranking for the approximate values and the validated values matches well with each other. Moreover, for both nodes, the actual largest average currents are captured

7 by the top-ranked configuration candidates identified via the proposed superposition approach. In addition, the comparison for the approximate peak D- VD and the validated peak DVD (for a PDN with 8 local grids) is shown in Table 2. A node at the grid in the corner, and a node at the center grid are both examined. Similar to the average current case, the grid close to the checking node has the most impact to its DVD. Therefore, the configuration ranking obtained from the superposition approximation does not precisely match the true ranking while the overall trend is preserved. Unlike the previous case, the approximate and the validated peak DVD values have a greater difference. However, since the trend is well preserved in the approximation, the largest peak DVD can still be captured by top-ranked configurations through the approximation method. The stable-mode EM checking have been carried out for three million-node PDNs. The run time and the largest EM obtained by choosing P as 4, 8, 12 are shown in Table 3. Although in some cases when using a small P value, the largest value is missed (i.e. node Ncor in the 8.25M-node grid, when P =4, 8, the largest average current is 1.01mA. When P =12, the largest value is 1.02mA), the final results do not differ much (less than 1%). This means that our proposed checking methodology can capture the worst (or near worst) cases very effectively. Moreover, in terms of runtime, for the PDNs with a large number of gated grids, the number of possible stable configurations is very large, which leads to excessive runtime for brute-force enumeration (107,000 hours for the largest case!). However, by using the proposed checking scheme, only a small number of full simulations need to be carried out, therefore, the runtime has been greatly reduced (only a couple of hours for the largest grid). The stable-mode peak DVD checking results shown in Table 4 demonstrate a similar behavior to the EM checking. Still, the largest peak DVD can be well captured by the proposed approach. The runtime saving over brute-force enumeration for PDNs with a large number of gated grids is huge, estimated as over 2,740X for the largest case when P = Power-on Checking In terms of power-on checking, without loss of generality, a gated grid at the center is chosen to be in transition state. A transistor at a grid near the transition and a transistor at a grid far away from the transition are chosen to be examined. As can be seen from the results shown in Table 5, similar to the stable mode checking, the proposed method can effectively capture the largest or near largest peak DVD by simulating only a small number of configurations. 6. Conclusion In this work, we propose a simulation-based transient power gating checking approach. Specific circuit modeling techniques have been developed to individually verify each of the on-chip global and local power grids against given electromigration and voltage drop constraints. The proposed approach allows the use of fast superposition approximation methods to identify the top worst-case conditions validated by a small number of full simulations to achieve feasibility. Experimental results shows that our approach can accomplish the EM and DVD checking of an eight-million-node PDN in less than 11 hours. Although, the checking for a single wire or node is considered in this work, our methodology can be easily extended to verify all the wires or nodes in a PDN. 7. Acknowledgement This material is based upon work supported by the National Science Foundation under Grant No and SRC under Contract 2009-TJ References [1] J. Dorsey S. Searles and etc. An integrated quad-core opterontm processor. In Proc. ISSCC, pages , [2] S. Borkar. Thousand core chips - a technology perspective. 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8 Table 1. Top 8 approximate EM apx as well as their validated values EM val and rankings. The PDN has 4 gated grids. Two nodes in the global VDD grid are examined. Ncor: node at the corner; Ncen: node at the center; Con.: configuration index; AR.: rank for approximate values; VR.: rank for validated values. EM is in ma. The transient checking is run for 200 clock cycles (2000 time steps). Node Con. EM apx AR. EM val VR. Node Con. EM apx AR. EM val VR. Ncor Ncen Table 2. Top 12 approximate DV D p,apx as well as their validated values DV D p,val and rankings (with shiftable timing). The PDN has 8 gated grids. Two nodes in two different local grids are examined. NGcor: node at the corner grid; NGcen: node at the center grid; Con.: configuration index; AR.: rank for approximate values; VR.: rank for validated values. DV D p is in mv. The transient checking is run for at least 200 clock cycles (2000 time steps). Node Con. DV D p,apx AR. DV D p,val VR. Node Con. DV D p,apx AR. DV D p,val VR. NGcor NGcen Table 3. EM stable mode checking for gated PDN. Two nodes in the global VDD grid are examined. Ncor: node at the corner; Ncen: node at the center; # Con.: number of configurations; T: total runtime; EM max : maximum absolute average current; P: number of worst case candidates. Runtime is in hrs. EM is in ma. Runtime of the enumeration methods for larger circuits are the estimated time ( time value). The transient checking is run for 200 clock cycles (2000 time steps). Gated Grids # Con. # Nodes Node Enumeration P=4 P=8 P=12 T EM max T EM max T EM max T EM max M Ncor Ncen M Ncor NA Ncen NA M Ncor 1.07e5 NA Ncen 1.07e5 NA Table 4. Peak DVD stable mode checking for gated PDN with shiftable timing. For grids with 8 and 16 grids, two nodes in two different local grids are examined. NGcor: node at the corner grid; NGcen: node at the center grid; # Con.: number of configurations; T: total runtime; DV D p,max : maximum peak DVD; P: number of worst case candidates. Runtime is in hrs. DVD is in mv. Runtime of the enumeration methods for larger circuits are the estimated time ( time value). The transient checking is run for at least 200 clock cycles (2000 time steps). Gated Grids # Con. # Nodes Node Enumeration P=4 P=8 P=12 T DV D p,max T DV D p,max T DV D p,max T DV D p,max M NA NA M NGcor NA NGcen NA M NGcor 7.06e4 NA NGcen 7.06e4 NA Table 5. Peak DVD transition checking for gated PDN. The transition grid is at the center. For grids with 8 and 16 grids, two nodes in two different grids are examined. NGclo: node in the grid close to the transition grid; NGfar: node in the grid far away from the transition grid; # Con.: number of configurations; T: total runtime; DV D p,max : maximum peak DVD; P: number of worst case candidates. Runtime is in hrs. DVD is in mv. Runtime of the enumeration methods for larger circuits are the estimated time ( time value). The transient checking is run for at least 200 clock cycles (2000 time steps). Gated Grids # Con. # Nodes Node Enumeration P=4 P=8 P=12 T DV D p,max T DV D p,max T DV D p,max T DV D p,max M NA NA NA NA M NGclo NA NGfar NA M NGclo 3.94e4 NA NGfar 3.94e4 NA