12. Finite State Machine Design

Transcription

1 EECS 7 Winter 3. Finite State Machine esign Profs. Kang Shin & Valeria Bertacco EECS epartment University of Michigan, nn rbor Copyright Frank Vahid Instructors of courses requiring Vahid's igital esign textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. ny other use requires explicit permission. Instructors may obtain PowerPoint source or obtain special use permissions from Wiley see for information.

2 FSM esign Goal: esign a FSM that satisfies the requirements of the given problem description (spec.) Follow FSM analysis steps in reverse! (more or less) ) (optional) Construct state diagram ) Construct state/output table 3) Create state assignments rt of design 4) Create transition/output table 5) Choose FF type 6) Construct excitation/output table - Similar to transition/output table Turn the crank 7) Find excitation and output logic equations EECS7 - Copyright 3

3 FSM esign Example Problem description: design a Moore FSM with one input IN and one output OUT, such that OUT is one iff IN is for three consecutive clock cycles State table: EECS7 - Copyright 3 3

4 State ssignments How many state variables are needed to encode four states? In general, if we have n states, how many state variables are needed to encode those states? log n These state assignments may seem rather arbitrary that s because they are! We will soon see the impact that state assignments have on our final circuit EECS7 - Copyright 3 4

5 Transition/output table State/Output Table: Transition/Output Table: IN Q Q OUT + + Q Q Choose FF type: Using flip-flops will simplify things (as we ll see below ) Excitation table Shows FF input values required to create next state values for every current state/input combination If we re designing with FFs, entries in excitation/output table are the same as those in transition/output table! Because of FF characteristic equation: Q + = EECS7 - Copyright 3 5

6 Excitation Logic Excitation/Output Table: Q Q IN Q IN IN Q Q Q IN Q Q IN Output Logic Q IN Q IN Q Q IN EECS7 - Copyright 3 OUT 6

7 Circuit: Excitation Equations: IN Q Q IN Q Q Output Equation: OUT EECS7 - Copyright 3 7

8 In Class Exercise esign a state/output table for the following problem specification: Combination lock: Two inputs, X and Y, encode a binary number between and 3 (X is MSB, i.e., XY = ). single output signal UNLOCK should be set to iff the sequence,, occurs on the inputs in three consecutive clock cycles EECS7 - Copyright 3 8

9 FSM Transition List esign: 5s Vending Machine Inputs d: asserted when user inserts dime n: asserted when user inserts nickel c: asserted when user presses candy button s: asserted when user presses soda button Outputs dc: dispenses candy when asserted ds: dispenses soda when asserted cr: 4-bit unsigned number, represents the user s credit Specifications ll inputs are one-hot Candy costs cents, soda costs 5 cents Money need only be counted up to 5 cents EECS7 - Copyright 3 9

10 Vending Machine State iagram and Transition List dsc d d n n d+n cr = dc = ds = B cr = 5 dc = ds = C cr = dc = ds = E cr = 5 dc = ds = c c s EECS7 - Copyright 3 dndcn cr = dc = ds = nf cr = 5 dc = ds = G cr = dc = ds = Transition List Transition S Q Q Q Expression S + Q Q Q n B d C n d B n C B d E B n d B C n+d E C c C n d c C E c F E s G E s c E F B G

11 Transition List Transition S Q Q Q Expression S + Q Q Q n d B C n d B B n d C E B n d B C C n+d c E C n d c C E E c s F G E s c E F G B Q Q Q B C E F G Output Table EECS7 - Copyright 3 cr dc ds Q dc Q Q Q Q Q Q Q ds Q ndc Q c Q d Q n Q n Q QQ QQQ Q QQ d Q ( Q Q n d) QQQ c QQQ s QQQ sc s nd Q c c

12 5s Vending Machine: Mealy Implementation dcs EECS7 - Copyright 3 c, dc = E cr = 5 s, ds = Outputs are assumed to be unless stated otherwisend n cr = dnd n B cr = 5 C cr = dcnc, dc = The Mealy implementation uses fewer states, and therefore fewer FFs! d+n

13 State ssignments Back to our combinational lock example S B C UNLOCK X Y B B C B C S + EECS7 - Copyright 3 Minimal SOP: 6 literals Minimal POS: literals Perhaps we can do better using smarter state assignments 3

14 nother state assignment approach S B C Maximize the number of s UNLOCK X Y B B C B C S + Q + XY QQ Q Q UNLOCK Q + XY QQ X Y + + Q Q EECS7 - Copyright 3 Minimal SOP: literals Minimal POS: 9 literals Using smarter state assignments improved the next-state circuit cost from literals to 9 literals! 4

15 nother approach: use more flip-flops one-hot encodings (with the addition of ) S B C UNLOCK X Y B B C B C S + Read minterms directly off of transition table: Q Q XY XY Q Q XYQ EECS7 - Copyright 3 Q Q Q XY Q XYQQQ X YQQQ Q XYQQ Q 3 literals How many states are really in our new state machine? What happened to the other 4 states??? 5

16 Unused States Previous design: all unused states were implicitly assigned a next state of (state ) This is known as a safe design If noise causes the machine to enter an unused state, it will return to a used state under any input conditions u u u3 u4 X Y Q Q Q UNLOCK Q Q Q EECS7 - Copyright 3 6

17 Efficient esign: Treat the next-states and outputs of unused states as don t cares Minimizes circuit cost! If an unused state is ever entered, state machine may never return to normal operation u u u3 u4 X Y Q Q Q UNLOCK Q Q Q Finding transition equations now requires 5-variable K-maps! d d d d EECS7 - Copyright 3 7

18 State clustering assigns unused states to behave like used states If noise causes an unused state to be entered, the machine will return to a used state in a single clock cycle X Y Q Q Q x x x Q Q Q UNLOCK Represents (C) and (u) Represents (), (u), (u3), and (u4) EECS7 - Copyright 3 8