Module 10: Sequential Circuit Design

Size: px

Start display at page:

Download "Module 10: Sequential Circuit Design"

Clement Morrison
5 years ago
Views:

1 Module : Sequential Circuit esign Wakerly: Chapter 7 (Part 3) : ECE 3233 r. Keith A. eague Spring 23 REA Chapter 7 (skipping references to HL) 23 -Machine esign and Synthesis he creative part, like writing a program or figuring out HOW to solve the problem urning the crank, like a compiler does the implementation part Example: esign a combination lock with two inputs, and 2. Open for the sequence, 2, 2 (one input per clock). 23 2

2 Example: esign a combination lock with two inputs, and 2. Open for the sequence, 2, 2 (one input per clock) Meaning ame ULOCK Start A A A B A(B) Got B A C A A (C) Got,2 C A A A () Got,2,2 A A() B A Specification ambiguities are resolved in the state table Assignment Can minimize number of states (see text), but hardly anyone bothers anymore. We ll look at this a little later and learn about one sub-optimal technique called row matching eed to assign state-variable combinations to states. Minimum number of variables for n states is log 2 n Using more than minimum number may be advantageous in some situations, e.g., one variable per state ( one-hot ) (see text). Example -- 4 states, 2 state variables (Q,Q2): A ==> B ==> C ==> ==> Up to this point is art, the rest is just turning the crank. 23 4

3 ransition able Substitute state-variable combinations for states in the state table Meaning Q Q2 ULOCK Start Got Got,2 Got,2, Q Q2 5 ransition Equations; Circuit transition table specifies each state variable (Q, Q2 ) as a combinational logic function of Q, Q2,, 2. ind a realization of each function by your favorite means -- ad hoc, minimal sum-of-products, etc. Build the circuit. Q Q2 Q Q Q ULOCK 2 CLK Q2 Q Q2 23 6

4 Another esign Example (from text) esign a machine with inputs A and B and output Z that is if: A had the same value at the two previous ticks, or B has been since the last time the above was true 23 7 Assignment here are 6,72 different state assignments of 5 states to 3 variables. And there are even more using 4 or more variables Here are a few obvious or interesting ones: 23 8

5 ransition/output able (decomposed assignment) With flip-flops, excitation table is identical to transition table evelop Excitation Equations 5-variable K-Maps! Assume unused states have next-state = 23

6 Alternative Machine Representations Why iagrams Are Sometimes ot Enough ot flexible enough for describing very complex finite state machines ot suitable for gradual refinement of finite state machine o not obviously describe an algorithm: that is, well specified sequence of actions based on input data algorithm = sequencing + data manipulation separation of control and data Gradual shift towards program-like representations: Algorithmic Machine (ASM) otation Hardware escription Languages (e.g., VHL) You can take a class at OSU on VHL. 23 Alternative Machine Representations Algorithmic Machine (ASM) otation hree Primitive Elements: Box ecision Box Output Box Machine in one state block per state time Single Entry Point Unambiguous Exit Path for each combination of inputs Outputs asserted high (.H) or low (.L); Immediate (I) or delayed til next clock Entry Path * ame Output List Condition Condition Box Conditional Output List *** Code Box ASM Block Output Box Exits to other ASM Blocks 23 2

7 Alternative Machine Representations ASM otation Condition Boxes: Ordering has no effect on final outcome Equivalent ASM charts: A exits to B on (I I) else exit to C A A I I I I B C B C 23 3 Alternative Machine Representations Example: Parity Checker Even Input, Output Z othing in output list implies Z not asserted Odd H. Z race race paths to derive state state transition tables tables Z asserted in Odd Symbolic able: Input Input Present Even Even Odd Odd Encoded able: Present ext Even Odd Odd Even ext Output A A Output 23 4

8 Basic esign Approach Six Step Process. Understand the statement of the Specification 2. Obtain an abstract specification of the SM 3. Perform a state minimization 4. Perform state assignment 5. Choose types to implement SM state register 6. Implement the SM, 2 covered now; 3, 4, 5 covered later; 4, 5 generalized from the counter design procedure 23 5 inite Machine Word Problem Mapping English Language escription to ormal Specifications Case Study: igital Combination Lock We will use state diagrams and ASM Charts 23 6

9 inite Machine Word Problems igital Combination Lock "3 bit serial lock controls entry to locked room. Inputs are RESE, EER, 2 position switch for bit of key data. Lock generates an ULOCK signal when key matches internal combination. ERROR light illuminated if key does not match combination. Sequence is: () Press RESE, (2) enter key bit, (3) Press EER, (4) repeat (2) & (3) two more times." Problem specification is incomplete: how do you set the internal combination? exactly when is the ERROR light asserted? Make reasonable assumptions: hardwired into next state logic vs. stored in internal register assert as soon as error is detected vs. wait until full combination has been entered Our design: registered combination plus error after full combination 23 7 inite Machine Word Problems igital Combination Lock ull ext or he Word Problem A 3-bit serial lock is used to allow entry to a locked room. he lock has a RESE button, an EER button, and a twoposition switch to represent the key value being entered ( or ). When the ULOCK signal is asserted, a relay is released, allowing the door to open. he unlock process begins when the operator presses RESE. He or she then sets the input switch, followed by pressing the EER button. his is repeated for the second and third key digits (bits). An ERROR light should be illuminated if, after entering the three binary digits, the operator has not matched the key. he process can be repeated by asserting RESE again. 23 8

10 inite Machine Word Problems igital Combination Lock Understanding the problem: draw a block diagram RESE Operator ata Internal Combination EER KEY -I L L L 2 Combination Lock SM ULOCK ERROR Inputs: Key-In L, L, L2 Outputs: Unlock Error 23 9 inite Machine Word Problems igital Combination Lock Enumeration of states: what sequences lead to opening the door? error conditions on a second pass SAR state plus three key COMParison states S AR COMP SAR entered on RESE Exit SAR when EER is pressed KI = L Y Continue on if Key-In matches L 23 2

11 inite Machine Word Problems igital Combination Lock Path to unlock: COMP ILE KI = L Wait for Key press Y ILE COMP2 COMP KI = L 2 Y OE H.Unlock Compare Key-I KI = L Y S AR 23 2 inite Machine Word Problems igital Combination Lock ow consider error paths Should follow a similar sequence as ULOCK path, except asserting ERROR at the end: ILE' ILE' ERROR3 H.Error ERROR ERROR2 S AR COMP error exits to ILE' COMP error exits to ILE' COMP2 error exits to ERROR

12 inite Machine Word Problems igital Combination Lock + Start KI = L Comp KI L Idle Idle' Equivalent iagram Comp KI = L Idle KI L Error Idle' Comp2 Error2 KI = L2 KI L2 one [Unlock] Error3 [Error] Start Start Another Example Example: Vending Machine SM General Machine Concept: deliver package of gum after 5 cents deposited single coin slot for dimes, nickels no change Step. Understand the problem: raw a picture! Block iagram Coin Sensor Vending Machine SM Open Gum Release Mechanism Clk 23 24

13 Vending Machine Example Step 2. Map into more suitable abstract representation abulate typical input sequences: three nickels nickel, dime dime, nickel two dimes two nickels, dime S raw state diagram: Inputs:,, reset S S2 Output: open S3 S4 S5 S6 [open] [open] [open] S7 [open] S8 [open] Vending Machine Example Step 3: Minimization, 5 5 [open] reuse states whenever possible Present 5 5 Inputs ext Symbolic able Output Open 23 26

14 Vending Machine Example Step 4: Encoding Present Q Q Inputs ext Output Open Alternative Machine Representations ASM Chart for Vending Machine 5 5 H.Open 23 28

15 Vending Machine Example Step 5. Choose s for implementation easiest to use Q Q Q Q Q Q Q Q Q Q K-map for Q K-map for Q K-map for Open Q \Q Q Q CLK Q R \reset Q \Q OPE = Q + + Q = Q + Q + Q + Q Q \ Q Q Q CLK Q R \reset Q \Q 8 Gates OPE = Q Q Vending Machine Example Step 5. Choosing for Implementation J-K Present Q Q Inputs ext J K J K Remapped encoded state transition table 23 3

16 Q Q Vending Machine Example Implementation: Q Q Q Q J = + Q Q K-map for J Q Q Q Q K-map for K Q Q Q K = J = Q + Q K = Q Q \ Q CLK J Q K R Q Q \ Q Q K-map for J Q K-map for K Q OPE \ Q CLK J Q K Q R Q \ Q \reset 7 Gates 23 3

Synchronous Sequential Circuit Design. Dr. Ehab A. H. AL-Hialy Page 1

Synchronous Sequential Circuit Design Dr. Ehab A. H. AL-Hialy Page Motivation Analysis of a few simple circuits Generalizes to Synchronous Sequential Circuits (SSC) Outputs are Function of State (and Inputs)