Designing an LLC Resonant Half-Bridge Power Converter

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1 Topic 3 Designing an LLC Resonant Half-Bridge Power Converter Hong Huang

2 Agenda. Introduction Brief review Advantages 2. Design Prerequisites Configuration Operation Modeling Voltage gain function 3. Design Considerations Voltage gain and switching frequency Line and load regulation Zero voltage switching (ZVS) Steps for designing and a design example 4. Conclusions Texas Instruments 200 Power Supply Design Seminar 3-2

3 Introduction Brief review of resonant converters Series resonant converter (SRC) Parallel resonant converter (PRC) L r C r L r R L C r R L SRC Single resonant frequency Circuit frequency increases with lighter load PRC Resonant point changes with load Large amount of circulating current Texas Instruments 200 Power Supply Design Seminar 3-3

4 Introduction Brief review of resonant converters Combination of SRC and PRC LCC Two resonant frequencies Requires three elements LLC: alternative LCC L r and L m integrated in a transformer Advantages of LLC High efficiency (ZVS) Less frequency variation and lower circulating current ZVS over operating range L r C r L r C r C r2 R L L m R L LCC LLC Texas Instruments 200 Power Supply Design Seminar 3-4

5 Design Prerequisites Configuration Square-Wave Generator Resonant Network Rectifiers for DC Output Variable-frequency square-wave generator Divider formed by resonant network and R L V in = V DC Q + Q2 V sq I r C r L r + V so L m n:: D C o V o I o R L Rectifier to get DC output D2 Changing frequency varies voltage across R L C r L r Frequency-modulated converter instead of PWM I r + + V sq V so I m L m I os R Ĺ V sq V so Texas Instruments 200 Power Supply Design Seminar 3-5

6 Design Prerequisites Operation f sw switching frequency f 0 series resonant frequency (C r and L r ) f co circuit resonant frequency (C r L r, and L m, together R L ) V g_q V g_q V g_q V g_q2 V g_q2 V g_q2 V sq V sq V sq I r I m I r I m I r I m I s I s I s D D2 D D2 D D t0 t t2 t3 t4 t0 t t2 t3 t4 t0 t t2 time, t time, t time, t t3 t4 f sw = f 0 f sw < f 0 f sw > f 0 Texas Instruments 200 Power Supply Design Seminar 3-6

7 Modeling Design Prerequisites First harmonic approximation (FHA) C r L r C r L r I r I m I os I r V sq V so L m R Ĺ V ge L m I m R e I oe V oe V sq V so (a) Input and output: Square wave voltages Sinusoidal current in resonant circuit (b) Input and output: Fundamental components to approximate FHA Rectifier and R L equivalent to R e AC circuit method can be used Texas Instruments 200 Power Supply Design Seminar 3-7

8 Design Prerequisites Voltage gain function Expression from impedance divider n V V V M M M o so oe g_dc= g_sw = g_ac = V in/2 Vsq Vge C r L r M g_dc n Vo V = V /2 V in oe ge + V ge I r L m I m R e I oe + V oe = (jωl ) R m ω m e + ω r + ω (j L ) R j L e j C r where ω= 2π f = 2πf and j = sw Texas Instruments 200 Power Supply Design Seminar 3-8

9 Design Prerequisites Voltage gain function Expression (Normalization) n V V V M M M o so oe g_dc= g_sw = g_ac = V in/2 Vsq Vge 2 Ln fn g = 2 2 n + n + n n e n M [(L ) f ] j[(f ) f Q L ] Normalized Gain Resonant Frequency Quality Factor Normalized Frequency Inductor Ratio V M V /2 o g = f0 in = L/C r r 2 π LrC Qe = r R e f n = f f sw 0 L n = L L m r Eq. Load R. R e 2 8 n = R 2 π L Texas Instruments 200 Power Supply Design Seminar 3-9

10 Design Prerequisites Voltage gain function Plots of gain magnitude, fixed L n = 5 Q e (load current) increases peak gain decreases curves shrink Q e =0.5 Q e M g_pk Gain 0.8 Q e =0. Q e = Normalized Frequency Texas Instruments 200 Power Supply Design Seminar 3-0

11 Design Prerequisites Voltage gain function Plots of gain magnitude, fixed Q e = 0.5 Gain L n decreases peak gain increases ZVS obtained but conduction losses increase L n =0 L n =5 L n = Normalized Frequency L n M g_pk Texas Instruments 200 Power Supply Design Seminar 3-

12 Where to base a design? Design Considerations In the vicinity of series resonance, f n = narrowest frequency variation M g able to =, >, and < Right side of the resonant peak ZVS requirement Frequency in operation.6 Qe = 0.4 a3 a2 Gain, Mg.2 Q e = max a0 Qe = a 0.6 a Normalized Frequency, f n Texas Instruments 200 Power Supply Design Seminar 3-2

13 Line and load regulation Design Considerations Properly set up M g_max and M g_min Frequency limit set up.6.4 a3 a2 Qe = 0 Q e = max at full load M = g_max n x V V /2 in_min o_max Gain, Mg Qe= max a0 Qe = 0 a M = g_min n x V o_min V /2 in_max 0.6 a4 Qe = 0 at no load fn_min Qe= max fn_max Normalized Frequency, f n Texas Instruments 200 Power Supply Design Seminar 3-3

14 Design Considerations Overload current operation Q e = max to include and meet the required M g_max Operation still on the right side of resonant peak Frequency in operation.6.4 a3 a2 Qe = 0 M = g_max n x V V /2 in_min o_max Gain, Mg Qe= max a0 Qe = 0 a M = g_min n x V o_min V /2 in_max 0.6 a4 Qe = 0 fn_min Qe= max fn_max Normalized Frequency, f n Texas Instruments 200 Power Supply Design Seminar 3-4

15 2 Design Considerations Load short circuit Protection options Increase f sw rapidly to reduce Mg to zero Operation with f n >, i.e., f sw > f 0 at all times Independent protection function a3 Q = 0 e a2 M = g_max n x V V /2 in_min o_max Gain, Mg a0 a4 a Curve 2 Curve (Q = 0) e M = g_min n x V V /2 o_min in_max f n_min Curve 4 Curve 3 (Q = max) f n_max Normalized Frequency, f n Texas Instruments 200 Power Supply Design Seminar 3-5 e

16 Design Considerations Zero voltage switching (ZVS) How ZVS is achieved? V g_q V g_q2 Q Turns Off V in + V g V g Q Q2 V sq C DS L r I r C DS2 L m I m C r n:: V sq 0 0 I r I m Q2 Turns On V = 0 ds_q2 Q2: C ds Discharge, Body Diode Turns On t dead t0 t t2 time, t t3 t4 Texas Instruments 200 Power Supply Design Seminar 3-6

17 Design Considerations Zero voltage switching (ZVS) Necessary condition Input impendence of the resonant network inductive Operation on the right side of the resonant peak Sufficient condition Enough energy stored in the magnetic field, mainly L m Enough time to discharge the capacitors, mainly C DS Texas Instruments 200 Power Supply Design Seminar 3-7

18 Design Considerations Why not design on the left side of the resonant peak? Capacitive current results ZVS lost Hard switching Switching losses increase Body diode reverse recovery losses Primary MOSFET failure Higher EMI noise Reversed frequency relationship to feedback loop Texas Instruments 200 Power Supply Design Seminar 3-8

19 Design Considerations Design Steps How to initially select? f sw, switching frequency n, transformer turns ratio L n, inductance ratio Q e, series resonant quality factor Texas Instruments 200 Power Supply Design Seminar 3-9

20 Design Considerations Design Steps Switching frequency Usually selected for particular applications Example in off-line applications: Typical below 50 khz Selecting the switching frequency f decrease Bulkier converter f decrease Switching losses decrease ZVS benefit decrease f increase ZVS benefits increase vs. hard switching converters Very High f : Component availability Additional switching losses Additional concerns due to parasitic effects Texas Instruments 200 Power Supply Design Seminar 3-20

21 Design Considerations Design Steps Transformer turns ratio, n Voltage gain can be larger and smaller than unity Flexibility in selecting the turns ratio, n Turns ratio design with M g =, initially, and nominal V in and V o n V in/2 = Mg = V V /2 in _ nom V o o_nom M = g Texas Instruments 200 Power Supply Design Seminar 3-2

22 Design Considerations Design Steps L n and Q e L n and Q e to achieve M g_pk > M g_max for maximum load Select L n and Q e from preplotted peak gain curves Initial selection L n = 5 Q e = 0.5 Example: Select L n and Q e for M g_max =.2 To achieve design margin Final selection L n -3.5, Q e = % margin over Attainable Peak Gain, Mg_pk L n = 3.5 by Interpolation M g_pk =.56 Q = 0.45 e L = 3.0 n L n = 5 M g_pk =.2 Q = 0.5 e L =.5 n L n =.5 L n = 2.0 L n = 3.0 L n = 4.0 L n = 5.0 L n = 6.0 L n = 8.0 L n = Quality Factor, Q e Texas Instruments 200 Power Supply Design Seminar 3-22

23 Design Considerations Design Steps Trade-offs to select L n and Q e Different requirements for different applications Fixed Q e, L n decrease peak gain increase good for ZVS and avoids capacitive current But, L n decrease L m decrease conduction losses increase Fixed L n, Q e decrease peak gain increase frequency variation increase Recommend starting with L n = 5, and Q e = 0.5 (from design practice) Texas Instruments 200 Power Supply Design Seminar 3-23

24 Design Considerations Resonant circuit design flow Attainable Peak Gain, Mg_ap Gain, Mg L n =.5 L n = L n = 3.0 L = 3.0 L n n = L n = 5.0 L n = 6.0 L 2.2 L n = 3.5 by n = 8.0 L Interpolation n = M g_ap =.56 Q e = L n =.5.6 L n = 5.4 M g_ap =.2 Q e = Quality Factor, Q e Q = 0.47 e Q = 0 e f = 0.65 n_min L = 3.5 n M g_max =.3 M g_min = 0.99 Q e = f n_max = Converter Specifications M M g_min g_max n = V 2V in Choose Ln and Qe o n Vo_min = V /2 in_max n Vo_max = V /2 in_min Check M g and fn Against Graph Are Values Within Limits? M g_max Mg_min fn_max f n_min Change L nand Qe No Yes Magnetizing Inductance Resonant Inductor L Resonant Capacitor Calculate R e Lm= Ln Lr = r 2 ( sw) C = r 2π f C V 2 R 8 n 2 8 n 2 o e = 2 R L = π π2 P out π r Texas Instruments 200 Power Supply Design Seminar 3-24

25 Design example Design Considerations Specifications Rated output power: 300 W Input voltage: 375 to 405 VDC Output voltage: 2 VDC Rated output current: 25 A Efficiency (V in = 390 VDC and I o = 25 A): >90% Switching frequency: 70 khz to 50 khz Topology: LLC resonant half-bridge converter Texas Instruments 200 Power Supply Design Seminar 3-25

26 Design example Design Considerations Proposed converter circuit block diagram DT Q C in L r T n:: V o I r I o Q2 L m C o + C r R L I D I D2 U D D2 C B GD OC UCC25600 GD RT 2 VCC DT GND SS R DT RT RT2 U2 V s C f R f R o R o2 C SS U3 Texas Instruments 200 Power Supply Design Seminar 3-26

27 Design Considerations Design example UCC25600 Features 8-pin SOIC package Programmable: dead time f min and f max 8-pin SOIC (D), Top View DT RT GD VCC Drive soft start time Protection OCP: hiccup and latch-off OC SS GND GD2 Drive 2 VCC UVLO and OVP OTP Burst operation Texas Instruments 200 Power Supply Design Seminar 3-27

28 Design Considerations Resonant circuit design flow Attainable Peak Gain, Mg_ap Gain, Mg Quality Factor, Q e Q = 0.47 e L n = 3.5 by Interpolation M g_ap =.56 Q = 0.45 e L = 3.0 n L n = 5 M g_ap =.2 Q = 0.5 Q = 0 e f = 0.65 n_min L = 3.5 n M g_max =.3 M g_min = 0.99 Q e = f n_max = e L =.5 n L n =.5 L n = 2.0 L n = 3.0 L n = 4.0 L n = 5.0 L n = 6.0 L n = 8.0 L = 9.0 n Converter Specifications M M g_min g_max n = V 2V in Choose Ln and Qe o n Vo_min = V /2 in_max n Vo_max = V /2 in_min Check M g and f n Against Graph Are Values Within Limits? M g_max Mg_min fn_max f n_min Change L n and Qe No Yes n = 6 L n = 3.5 Q = 0.45 e Magnetizing Inductance Resonant Inductor L Resonant Capacitor Calculate R e Lm = Ln Lr = r 2 ( sw) C = r 2π f C V 2 R 8 n 2 8 n 2 o e = 2 R L = π π2 P out π L m = 20 µh L r = 60 µh C r = 27.3 nf r Texas Instruments 200 Power Supply Design Seminar 3-28

29 Design check Design Considerations.9.7 Q = 0 e L = 3.5 n.5 Q = 0.47 e Gain, Mg.3. Q = 0.52 e 0.9 f n_min = 0.65 (80.9 khz) f n_max = (26.9 khz) 70 khz 24.4 khz M g_max =.3 M g_min = khz Normalized Frequency, f n Texas Instruments 200 Power Supply Design Seminar 3-29

30 Design Considerations Design check Verification with computer-based circuit simulation Design reiteration, if needed Size/select components Build the board Verification with bench tests Re-spin the board/design, if needed Texas Instruments 200 Power Supply Design Seminar 3-30

31 Design Considerations Experiment results (L m = 280 µh, L r = 60 µh, C r = 24 nf) 95 Efficiency Efficiency (%) Input Voltage, V in 405 V 390 V 375 V Output Ripple Voltage (50 mv/div) 90 mv Output Ripple Voltage (full load) Load Current (A) Time (5 µs/div) Resonant Network Voltages (full load) (200 V/div) V Lr V Lm (200 V/div) V ds_q2 (500 V/div) V Cr (200 V/div) Time (5 µs/div) V C r (00 V/div) V gs_q2 I r (.2 A/div) Time ( µs/div) V ds_q2 (20 V/div) (500 V/div) Resonant Network Current and Voltage (full load) Texas Instruments 200 Power Supply Design Seminar 3-3

32 Test Result versus FHA from the Design In the vicinity of f 0, FHAbased result very accurate to the final test result (L r = 60 µh and C r = 24 nf) (65,.90) (60,.57) (55,.27) (80,.58) (00,.2) Bench Test Measurements Plot Based on Equation 8 Away from f 0, less accuracy from FHAbased result Equation (8) Gain, M g 0.6 (40, 0.70) (30, 0.5) (35, 0.99) (200, 0.78) (240, 0.72) (70, 0.87) (400, 0.56) Voe = = m Mg V ge (jx Lm R e ) + j(x L r X Cr ) = m jx ω m e + ω r + ω L (jωl ) R (j L ) R j L e R e j C r 0.0 f = 35 khz Frequency, f sw (khz) Texas Instruments 200 Power Supply Design Seminar 3-32

33 Conclusions FHA-based method approximately, while effectively, converted complicated LLC resonant-converter circuit to standard AC circuit greatly simplified its analysis and design Method results effective for LLC converter design, especially for initial parameters determination Design example with comprehensive design considerations in procedural design steps demonstrating method effectiveness Possibility of FHA-based approach for other resonant converters Texas Instruments 200 Power Supply Design Seminar 3-33

ET4119 Electronic Power Conversion 2011/2012 Solutions 27 January 2012

ET4119 Electronic Power Conversion 2011/2012 Solutions 27 January 2012 1. In the single-phase rectifier shown below in Fig 1a., s = 1mH and I d = 10A. The input voltage v s has the pulse waveform shown