ECEN720: High-Speed Links Circuits and Systems Spring 2017

Transcription

1 ECEN70: High-Speed Links Circuits and Systems Spring 07 Lecture : Channel Components, Wires, & Transmission Lines Sam Palermo Analog & Mixed-Signal Center Texas A&M University

2 Announcements Lab Lab begins on Jan 30 and is in CVLB 3 Prelab due at beginning of lab on Jan 30 TA Ashkan Roshan amir ashkanroshan@tamu.edu Office Hours M 3PM-5PM, WEB 35A Reference Material Posted on Website TDR theory application note S-parameter notes

3 Agenda Channel Components IC Packages, PCBs, connectors, vias, PCB Traces Wire Models Resistance, capacitance, inductance Transmission Lines Propagation constant Characteristic impedance Loss Reflections Termination examples Differential transmission lines 3

4 Channel Components Backplane trace Line card trace Packaged SerDes Edge connector Via stub [Meghelli (IBM) ISSCC 006] Pkg Line card trace Line card via Edge connector Backplane via Tx IC The Channel Backplane 6 trace Pkg Line card trace Line card via Edge connector Backplane via Rx IC 4

5 IC Packages Package style depends on application and pin count Packaging technology hasn t been able to increase pin count at same rate as on-chip aggregate bandwidth Leads to I/O constrained designs and higher data rate per pin Package Type Pin Count Small Outline Package (SOP) 8 56 Quad Flat Package (QFP) Plastic Ball Grid Array (PBGA) Enhanced Ball Grid Array (EBGA) Flip Chip Ball Grid Array (FC-BGA) SOP QFP PBGA FC-BGA [Package Images - Fujitsu] 5

6 IC Package Examples Wirebonding is most common die attach method Flip-chip packaging allows for more efficient heat removal D solder ball array on chip allows for more signals and lower signal and supply impedance Standard Wirebond Package Flip-Chip/Wirebond Package Flip-Chip/Solder Ball Package [Package Images - Fujitsu] 6

7 IC Package Model Bondwires L ~ nh/mm Mutual L K C couple ~ 0fF/mm Package Trace L ~ 0.7-nH/mm Mutual L K C layer ~ 80-90fF/mm C couple ~ 40fF/mm [Dally] 7

8 Printed Circuit Boards Components soldered on top (and bottom) Typical boards have 4-8 signal layers and an equal number of power and ground planes Backplanes can have over 30 layers 8

9 PCB Stackup Signals typically on top and bottom layers GND/Power plane pairs and signal layer pairs alternate in board interior Typical copper trace thickness 0.5oz (7.5um) for signal layers oz (35um) for power planes [Dally] 9

10 Connectors Connectors are used to transfer signals from board-to-board Typical differential pair density between 6-3 pairs/0mm [Tyco] 0

11 Connectors Important to maintain proper differential impedance through connector Crosstalk can be an issue in the connectors [Tyco]

12 Vias Used to connect PCB layers Made by drilling a hole through the board which is plated with copper Pads connect to signal layers/traces Clearance holes avoid power planes Expensive in terms of signal density and integrity Consume multiple trace tracks Typically lower impedance and create stubs [Dally]

13 Impact of Via Stubs at Connectors Packaged SerDes Backplane trace Line card trace Edge connector Via stub Legacy BP has default straight vias Creates severe nulls which kills signal integrity Refined BP has expensive backdrilled vias 3

14 PCB Trace Configurations Microstrips are signal traces on PCB outer surfaces Trace is not enclosed and susceptible to cross-talk Striplines are sandwiched between two parallel ground planes Has increased isolation [Johnson] 4

15 Wire Models Resistance Capacitance Inductance Transmission line theory 5

16 Wire Resistance Wire resistance is determined by material resistivity, ρ, and geometry Causes signal loss and propagation delay R l A l wh l A l r R [Dally] 6

17 Wire Capacitance Wire capacitance is determined by dielectric permittivity, ε, and geometry Best to use lowest ε r Lower capacitance Higher propagation velocity [Dally] C w s C log r r C log s r C w s log4s h 7

18 Wire Inductance Wire inductance is determined by material permeability, µ, and closed-loop geometry For wire in homogeneous medium CL Generally H/m 8

19 Wire Models Model Types Ideal Lumped C, R, L RC transmission line LC transmission line RLGC transmission line Condition for LC or RLGC model (vs RC) f 0 R L Wire R L C >f (LC wire) AWG4 Twisted Pair 0.08Ω/m 400nH/m 40pF/m 3kHz PCB Trace 5Ω/m 300nH/m 00pF/m.7MHz On-Chip Min. Width M6 (0.8µm CMOS node) 40kΩ/m 4µH/m 300pF/m.6GHz 9

20 RLGC Transmission Line Model As dx 0 V x, t I x t RIx, t L, x t I x, t V x t GV x, t C, x t () () General Transmission Line Equations 0

21 Time-Harmonic Transmission Line Eqs. Assuming a traveling sinusoidal wave with angular frequency, ω dv dx x x di dx G R jl jc V I x x Differentiating (3) and plugging in (4) (and vice versa) V dx I dx x d x V d I where is the propagation constant j x x (5) (6) (3) (4) - R jl G jc m Time-Harmonic Transmission Line Equations

22 Transmission Line Propagation Constant Solutions to the Time-Harmonic Line Equations: x r x f r f e V e V x V x V x V 0 0 What does the propagation constant tell us? Real part () determines attenuation/distance (Np/m) Imaginary part () determines phase shift/distance (rad/m) Signal phase velocity x r x f r f e I e I x I x I x I 0 0 where - m C j G L j R j (m/s)

23 Transmission Line Impedance, 0 For an infinitely long line, the voltage/current ratio is 0 From time-harmonic transmission line eqs. (3) and (4) 0 V I x x R G jl jc Driving a line terminated by 0 is the same as driving an infinitely long line [Dally] 3

24 Lossless LC Transmission Lines If Rdx=Gdx=0 j j 0 LC No Loss! LC Waves propagate w/o distortion Velocity and impedance independent of frequency Impedance is purely real 0 L C LC [Johnson] 4

25 Low-Loss LRC Transmission Lines If R/L and G/C << Behave similar to ideal LC transmission line, but Experience resistive and dielectric loss Frequency dependent propagation velocity results in dispersion Fast step, followed by slow DC tail 5 j C G L R LC j G R LC GL RC j LC j C j G L j R j D R G R D R 8 8 C G L R LC 8 8 C G L R LC Resistive Loss Dielectric Loss

26 Skin Effect (Resistive Loss) High-frequency current density falls off exponentially from conductor surface Skin depth,, is where current falls by e - relative to full conductor Decreases proportional to sqrt(frequency) Relevant at critical frequency f s where skin depth equals half conductor height (or radius) Above f s resistance/loss increases proportional to sqrt(frequency) d J e f f s R f R h R DC R f f f f s DC 0 s [Dally] For rectangular conductor: 6

27 Skin Effect (Resistive Loss) 5-mil Stripguide RDC 7 m, fs 43MHz 30 AWG Pair RDC 0.08 m, fs 67kHz R R f f DC 0 s [Dally] 7

28 Dielectric Absorption (Loss) An alternating electric field causes dielectric atoms to rotate and absorb signal energy in the form of heat tan D G C Dielectric loss is expressed in terms of the loss tangent [Dally] Loss increases directly proportional to frequency D G 0 f fc tan D tan LC D L C 8

29 Total Wire Loss [Dally] 9

30 Reflections & Telegrapher s Eq. 30 T i T V I , V I V V I I I I V I T T i r T i i r T f r i f 0 0 V V I I k T T i r f r r Termination Current: With a Thevenin-equivalent model of the line: KCL at Termination: Telegrapher s Equation or Reflection Coefficient [Dally]

31 Termination Examples - Ideal R S = 50 0 = 50, t d = ns R T = 50 in (step begins at ns) V k k i rt rs 50 V V source termination 3

32 Termination Examples - Open R S = 50 0 = 50, t d = ns R T ~ (M) in (step begins at ns) termination V k k i rt rs 50 V V source 3

33 Termination Examples - Short R S = 50 0 = 50, t d = ns R T = 0 in (step begins at ns) V k k i rt rs 50 V V source termination 33

34 Arbitrary Termination Example R S = = 50, t d = ns R T = 600 in (step begins at ns) V k k i rt rs 50 V 0.V V termination source 0.78V 0.05V

35 Lattice Diagram R S = = 50, t d = ns R T = 600 in (step begins at ns) Rings up to 0.6V (DC voltage division) 35

36 Termination Reflection Patterns source R S = 5, RT = 5 kr S & kr T < 0 Voltages Converge termination source termination R S = 5, RT = 00 kr S < 0 & kr T > 0 Voltages Oscillate R S = 00, RT = 5 kr S > 0 & kr T < 0 Voltages Oscillate termination source termination R S = 00, RT = 00 kr S > 0 & kr T > 0 source Voltages Ring Up 36

37 Termination Schemes No Termination Little to absorb line energy Can generate oscillating waveform Line must be very short relative to signal transition time n = 4-6 Limited off-chip use Source Termination Source output takes steps up Used in moderate speed pointto-point connections tr ntround trip nl t porch l LC LC 37

38 Termination Schemes Receiver Termination No reflection from receiver Watch out for intermediate impedance discontinuities Little to absorb reflections at driver Double Termination Best configuration for min reflections Reflections absorbed at both driver and receiver Get half the swing relative to single termination Most common termination scheme for high performance serial links 38

39 Differential Signaling Differential signaling advantages Self-referenced Common-mode noise rejection Increased signal swing Reduced self-induced power-supply noise Requires x the number of signaling pins relative to single-ended signaling But, smaller ratio of supply/signal (return) pins Total pin overhead is typically.3-.8x (vs x) 39

40 Odd & Even Modes [Hall] Even mode When equal voltages drive both lines, only one mode propagates called even more Odd mode When equal in magnitude, but out of phase, voltages drive both lines, only one mode propagates called odd mode For a differential pair (odd mode), a virtual reference plane exists between the conductors that provides a continuous return current path Electric field is perpendicular to the virtual plane Magnetic field is tangent to the virtual plane 40

41 Balanced Transmission Lines Even (common) mode excitation [Dally] Effective C = C C Effective L = L + M Odd (differential) mode excitation Effective C = C C + C d Effective L = L M DIFF even odd, CM even odd L Cc L M C c M Cd 4

42 PI-Termination even R odd R R even R R odd even even odd 4

43 T-Termination even R R R odd even R odd 43

44 Next Time Channel modeling Time domain reflectometer (TDR) Network analysis 44