RECENT ADVANCES in NETWORKING, VLSI and SIGNAL PROCESSING

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Loreen Osborne
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1 Optimization of Reflection Issues in High Speed Printed Circuit Boards ROHITA JAGDALE, A.VENU GOPAL REDDY, K.SUNDEEP Department of Microelectronics and VLSI Design International Institute of Information Technology P-14, Rajiv Gandhi Infotech Park, Hinjewadi, Pune INDIA Abstract: The problems associated with design of printed circuit board are many folds. The signal integrity within the PCB needs to be analyzed before finalization of PCB routing and needless to say that simulation is must. The major sources of signal integrity problems are the reflections along the PCB tracks. This paper proposes different techniques to minimize the reflections in a PCB using Allegro SPB A novel technique of using terminations for minimizing reflections is presented. Keywords: Signal Integrity, Reflections, Ringing, Terminations, Allegro SPB Introduction The rapid development of super large scale IC and computer technologies leverage the system design trend towards high-speed devices and miniaturization, as well as emphasize the problems of signal integrity and EMI/EMC issues in the PCB design. The cause of these problems is the development of IC port signal becoming faster. In digital systems design the signal transmission on the PCB is affected by parasitic parameters such as capacitance, inductance, and resistance of the printed circuit line. Receiving a severely distorted digital signal causes instability or system abnormality. Signal integrity should be considered in high PCB design. After considering and analyzing signal integrity in the design, simulation results may vary a lot from the actual, because analysis parameters in the tools do not match the actual PCB parameters. This paper focuses the reflection issues of signal integrity. Reflections are unwanted byproducts in digital logic design. Reflections are both a signal integrity and EMI issue. The paper is organized as follows: Next section, describes the reflection issues in high speed printed circuit boards. Third section presents different simulation results of reflection using Allegro SPB Concluding remarks are presented in the final section. 2 Reflections in High Speed Boards Reflections are unwanted byproducts in digital logic designs. Reflection can produce false clock triggering, increase in clock and signal jitter, and enhancing total emission from PCB. Ringing within transmission line contains both overshoot and ringing before stabilizing to a quiescent level, and is a manifestation of a same effect. Overshoot is the effect of an excessive voltage level above the power rail or below the ground reference. Undershoot is a condition that occurs when the voltage level does not reach the desired amplitude for both maximum and minimum transition levels. Overshoot can be controlled by terminations and proper PCB and IC package design. Overshoot, if severe enough, can overstress devices and cause damage or failure [7]. 2.1 Discontinuities in Signal Reflections are observed when impedance discontinuities exist in the transmission line. These discontinuities consists of [2] 1. Changes in trace width 2. Improperly matched terminations 3. Lack of termination 4. T-stubs/bifurcated traces 5. Vias between routing layers 6. Varying load and logic families ISSN: ISBN:

2 7. Large power plan discontinuities 8. Connector transitions 9. Changes in impedance of the trace 2.2 Trace Terminations Termination absorbs excess or unwanted energy. The need for termination is based on several design criteria, the most important of which is the existence of an electrically long trace. When the trace is electrically long, or when the length exceeds one-sixth of the electrical length of the edge transition time, the trace requires termination. Even if a trace is short, termination may still be required if the load is capacitive or highly inductive to prevent ringing. Termination not only matches trace impedance and removes ringing and reflections, but it may also slow down the edge rate transition clock signal if incorrect values are applied [1]. In high-speed PCB, traces act like transmission lines, and reflections occur at all points on the PCB trace where, impedance mismatches exist. The improper termination will also produce above problems. Signal reflections are caused by an impedance mismatch between the signal source and load. The impedance mismatch means that the transmitted signal is not fully absorbed by the load and is reflected back to the source, this process continues until all of the energy is absorbed. An impedance mismatch can be overcome by matching the source and load impedance using terminations. The easiest way to terminate is to use resistive element. Two basic configurations exist, source and load. Several methodologies available for these configurations are series termination resistor, parallel termination resistor, thevenin termination, AC termination and diode termination. Among the various techniques mentioned above, this paper focuses on shunt and thevenin termination techniques Shunt termination Widely known and simplest termination technique is shunt termination. In this technique a terminating resistor connects the receiver end to ground [4]. Choose the terminating resistor to match the characteristics impedance of the trace with load impedance as shown in Fig. 1. Fig.1 Shunt termination Advantages Simplicity of design Requires only one component Disadvantages More DC power is dissipated through the resistor. Termination to ground may change the duty cycle Thevenin termination Thevenin termination or dual termination uses two resistors whose parallel combination matches the characteristics impedance of the trace [4]. The combination of the resistors should equal the characteristic impedance of trace as in Fig.2 Advantages Fig.2 Thevenin termination This type of termination provides good overshoot suppression. Disadvantages Large current drive 2.3 Reflection Coefficient The magnitude of reflection is determined by a measure called as reflection coefficient. The trace is designed carefully with constant and controlled characteristic impedance. If it is terminated correctly, there will be no reflection from the far end. But if the terminating resistor is not selected properly, there will be reflection. Reflection coefficient is defined as follows [1], ISSN: ISBN:

3 Reflection = (R L Z o )/ (R L + Z o ) Where, R L is terminating or load resistor. Z o is the characteristic impedance of the trace. If R L = Z 0, then magnitude of the reflection coefficient goes to zero and there is no reflection. If the trace is left un-terminated, then the reflection coefficient becomes R L /R L = 1. This means the reflection is 100% and it is positive sign. If we short circuit the trace, so that terminating resistance is zero, then the reflection coefficient will become -Z 0 /Z 0 =-1. This means that reflection is 100% but with opposite sign. The value of the reflection coefficient can range between -1 and +1. It is +1 for an open trace and -1 for a shorted trace. A reflection coefficient value of zero means the trace is perfectly terminated. 2.4 Problem Statement for Reflection Fig.3 shows the basic reflection model simulation of clock signal in Allegro [5]. It consists of driver as clock source Y1 and two receivers as C8 and U1 connected through transmission line TL1 and TL2 of trace impedance 60Ω. Fig.3 Basic reflection model in Allegro The reflection simulation of basic reflection model for a frequency of 50MHz, without any termination is shown in Fig4. It is observed that as a result of ringing, the receivers U1 & C8 has the following values for overshoot high, overshoot low and noise margin. Receiver U1 has an overshoot high of mV, overshoot low = mV and noise margin = mV and at receiver C8 with values of overshoot high = mV, overshoot low = mv and noise margin= mv. In order to minimize ringing the basic reflection model is simulated for different trace widths adapting shunt and thevenin termination techniques. These termination techniques are studied for various frequencies of 50MHz, 100MHz and 150MHz. Fig.4 Driver and receiver signals without terminations 3 Reflection Simulations Reflections in the trace are eliminated by employing two widely used termination techniques shunt and thevenin termination techniques. Reflection simulation is done using the above mentioned shunt and thevenin terminations. 3.1 Reflection Simulation by shunt termination Table1 Shows the reflection simulation result for a frequency of 50MHz. For shunt termination, connect a termination resistor equal to characteristic impedance of trace impedance. According to the tabulations it is observed that terminating resistors of impedance 110 Ω, 100 Ω and 80 Ω, there is an impedance mismatch, resulting in overshoot high and overshoot low. Even it is observed that for a termination of 60Ω there is an overshoot for trace width of 10mils. Retaining the value of termination impedance the track width is changed to 8mills. From this result it is observed that trace width is also an important factor to minimize reflection [6]. Similarly the impact of shunt termination for frequencies of 100MHz and 150MHz are studied. It s been observed that to eliminate reflection for frequencies of 100MHz and 150MHz the trace width has to be 10mills for the same terminating impedance of 60 Ω at ISSN: ISBN:

at the receivers C8 and U1 From the above we conclude that to eliminate reflection along the trace it is necessary to maintain a good combination of frequency and track width.

TABLE II OBSERVATIONS FOR THEVENIN TERMINATION TECHNIQUE Fig.

4 at the receivers C8 and U1 From the above we conclude that to eliminate reflection along the trace it is necessary to maintain a good combination of frequency and track width. TABLE I OBSERVATIONS FOR SHUNT TERMINATION yields better result when compared to the former. The thevenin s termination is at its best for a track width of 8mils. TABLE II OBSERVATIONS FOR THEVENIN TERMINATION TECHNIQUE Fig. 5 shows the reflection simulation of trace XTAL2 for a trace width of 8mils, Shunt impedance of 60 Ω at both the receivers U1 and C8 at a frequency of 50MHz. Fig 6 shows the reflection simulation of trace XTAL2 for a trace width of 8mills and shunt termination at receiver U1 and Thevenin termination at C8 at a frequency of 50MHz. Fig.5 Reflection simulation with shunt terminations 3.2 Reflection Simulation by Thevenin termination Table.2 shows the reflection simulation results for a frequency of 50MHz. For a thevenin termination, connect two resistors whose parallel combination matches the characteristics impedance of the trace. In the following Table.2 termination type T and S denote thevenin and shunt termination respectively [6]. According to the tabulations it is observed that, use of thevenin termination at both U1 and C8 doesn t yield good result. The use of shunt at one of the receiver Fig.6 Reflection simulation with Thevenin termination at C8 and shunt termination at U1 4 Conclusion In High speed printed circuit board, consideration of signal integrity issues such as reflection, crosstalk and EMI are very important. This paper focuses on reflection minimization methods such as track width variation and termination techniques. Shunt termination and thevenin termination techniques are studied and results are tabulated using cadence Allegro SPB 16.0 simulation tool. From the above results we conclude that not only ISSN: ISBN:

5 termination techniques play a major role in minimizing the reflection but the track width and length also have a considerable role in minimizing reflection along the track. References [1] Douglas Brooks Integrity Issues and Printed circuit Board Design, Prentice Hall [2] Jon Varteresian Fabricating printed circuit boards, Newnes Publications [3]Knack, Kella. Debunking High-Speed PCB Design Myths. ASIC & EDA, [4] Mohamad Tisani Solutions to Current High-Speed Board Design, Pericom, Note22 [5] Allegro SI, Simulation and Analysis Reference, Product Version 16.01, June 2008 Cadence Design Systems Inc [6] Allegro Constraint Manager Reference, Series 200 and 600, Product Version 16.01, June 2008 Cadence Design Systems, Inc. [7] Hall, Stephen, et.al. High-Speed Digital System Design, Wiley Inter science, New York, NY, ISBN: , 2000 [8] [9] 1/reflection-and-ringing.html [10] 19 November 2009 [11] 25 November 2009 ISSN: ISBN:

AN B. Basic PCB traces transmission line effects causing signal integrity degradation simulation using Altium DXP version 6.

AN B. Basic PCB traces transmission line effects causing signal integrity degradation simulation using Altium DXP version 6. AN200805-01B Basic PCB traces transmission line effects causing signal integrity degradation simulation using Altium DXP version 6.9 By Denis Lachapelle eng. and Anne Marie Coutu. May 2008 The objective