64K x V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect IDT71V632. Features. Description. Pin Description Summary

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1 64K x V SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect IDT71V632 Features 64K x 32 memory configuration Supports high system speed: Commercial: A4 4.5 clock access time (117 MHz) Commercial and Industrial: 5 5 clock access time (100 MHz) 6 6 clock access time (83 MHz) 7 7 clock access time (66 MHz) Single-cycle deselect functionality (Compatible with Micron Part # MT58LC64K32D7LG-XX) LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (), byte write enable (BWE), and byte writes (BWx) Power down controlled by ZZ input Operates with a single 3.3V power supply (+10/-5%) Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP) Green parts available, see ordering information Pin Description Summary A0 A 5 1 s Description The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32 with full support of the Pentium and PowerPC processor interfaces. The pipelined burst architecture provides cost-effective secondary cache performance for processors up to 117MHz. The IDT71V632 SRAM contai write, data, address, and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the extreme end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V632 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses will be defined by the internal burst counter and the LBO input pin. The IDT71V632 SRAM utilizes IDT's high-performance, high-volume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board deity in both desktop and notebook applicatio. Chip Enable CS0, CS1 Chips Selects Output Enable Asynchronous Global Enable BWE Byte Enable B W, 1 B W2, B W3, W B 4 Individual Byte Selects Clock N/ A Burst Advance A DSC Status (Cache Controller) A DSP Status (Processor) LBO Linear / Interleaved Burst Order DC ZZ Sleep Mode Asynchronous I/O0 I/ O 31 Data /Outpu t I/ O, Q 3.3V Power N/ A VSS, VSSQ Array Ground, I/O Ground Power N/ A Pentium processor is a trademark of Intel Corp. PowerPC is a trademark of International Business Machines, Inc Integrated Device Technology, Inc tbl 01 FEBRUARY 2017 DSC-3619/09

2 IDT71V632, 64K x 32, 3.3V SRAM Pin Definitio (1) Symbol Pin Function I/ O Active Description A0 A 5 1 ddress s A I N/ A inputs. The address register is triggered by a combination of the rising edge of and Low or Low and C E Low. Status (Cache Controller) I L OW Status from Cache Controller. is an active LOW input that is used to load the address registers with new addresses. is NOT GATED by C E. Status (Processor) I LOW Status from Processor. is an active LOW input that is used to load the address registers with new addresses. is gated by C E. Burst Advance I L OW Advance. is an active LOW input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. When this input is HIGH the burst counter is not incremented; that is, there is no address advance. BWE Byte Enable I LOW byte write enable gates the byte write inputs BW1 BW4. If BWE is LOW at the rising edge of then BWX inputs are passed to the next stage in the circuit. A byte write can still be blocked if is LOW at the rising edge of. If is HIGH and BWX is LOW at the rising edge of then data will be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked and only G W can initiate a write cycle. BW1 BW4 Individual Byte Enables I L OW byte write enables. BW1 controls I/O(7:0), BW2 controls I/O(15:8), etc. Any active byte write causes all outputs to be disabled. LOW disables all byte writes. BW1 BW4 must meet specified setup and hold times with respect to. Chip Enable I L OW chip enable. is used with CS0 and IDT71V632. also gates A DSP. CS1 to enable the Clock I N/ A This is the clock to this input. input. All timing references for the device are made with respect CS0 Chip Select 0 I HIGH active HIGH chip select. CS0 is used with and the chip. CS1 to enable CS1 Chip Select 1 I L OW active LOW chip select. the chip. CS1 i s used with and CS0 to enable Global Enable I LOW global write enable. This input will write all four 8-bit data bytes when LOW on the rising edge of. supercedes individual byte write enables. 31 Data /Outpu t I/O0 I/ O I/ O N/ A data input/output (I/O) pi. Both the data input path path are registered and triggered by the rising edge of. and data output LBO Linear Burst Order I LOW Output Enable I LOW Asynchronous burst order selection DC input. When LBO is HIGH the Interleave d ( Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst sequence is selected. LBO is a static DC input and must not change state while the device is operating. Asynchronous output enable. When is LOW the data output drivers are enabled on the I/O pi if the chip is also selected. When is HIGH the I/ O pi are in a high-impedence state. Power Supply N/ A N / A 3.3V core power supply inputs. V DDQ Power Supply N/ A N / A 3.3V I/O power supply inputs. VSS Ground N/ A N / A Core ground pi. V SSQ Ground N/ A N / A I/O ground pi. No Connect N/ A N / A pi are not electrically connected to the chip. ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the internally and power down the IDT71V632 to its lowest power coumption level. Data retention is guaranteed in Sleep Mode. NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to tbl

3 IDT71V632, 64K x 32, 3.3V SRAM Functional Block Diagram LBO Binary Counter CLR Burst Sequence 2 Burst Logic Q0 Q1 A0* A1* INTERNAL ADDRESS 16 64K x 32 BIT MEMORY ARRAY. A0 A15 BWE BW1 BW2 BW3 BW4 EN ADDRESS REGISTER Byte 1 Register Byte 2 Register Byte 3 Register Byte 4 Register 16 2 A0, A1 A2 A Byte 1 Driver Byte 2 Driver Byte 3 Driver Byte 4 Driver OUTPUT REGISTER CS0 CS1 D Q Enable Register EN DATA INPUT REGISTER ZZ Powerdown D Q Enable Delay Register OUTPUT BUFFER I/O0 I/O drw

4 IDT71V632, 64K x 32, 3.3V SRAM Absolute Maximum Ratings (1) Symbol V V Rating 2) TERM ( Terminal Voltage wit h Respect to GND 3) TERM ( Terminal Voltage wit h TA Respect to GND Value Unit 0.5 to +4.6 V 0.5 to V Operating Temperatur e 0 to +70 o C Recommended Operating Temperature and Supply Voltage Grade Commercial Industrial Temperature VSS Q 0 C to +70 C 0 V 3.3V+10/-5% 3.3V+10/-5% 40 C to +85 C 0 V 3.3V+10/-5% 3.3V+10/-5% 3619 tbl 03 T BIAS Temperature Under Bias 55 to +125 o C TSTG PT I OUT 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2., Q and terminals only. 3. I/O terminals. Capacitance (TA = +25 C, f = 1.0MHz, TQFP package) Symbol CIN CI/ O Storage Temperatur e 55 to +125 o C Power Dissipatio n 1. 0 W DC Output 50 ma 1) P arameter Capacitanc e ( onditio C Max. VN I I/O Capacitanc e VOUT 3619 tbl 05 Unit = 3dV 6 pf = 3dV 7 pf Recommended DC Operating Conditio Symbol V DDQ V SS, VSSQ VIH VIH VIL P arameter M in. Max. Unit Core Supply Voltag e V I/O Supply Voltag e V Ground 0 0 V High Voltage s High Voltage I/ O 2. 0 V DQ 0. Low Voltag e 0. 3 ( 3). 8 ( 1) 5 V ( 2) D + 3 V 0 V 3619 tbl VIH (max) = 6.0V for pulse width less than tcyc/2, once per cycle. 2. VIH (max) = Q + 1.0V for pulse width less than tcyc/2, once per cycle. 3. VIL (min) = 1.0V for pulse width less than tcyc/2, once per cycle tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested

VSSQ I/O18 I/O19 I/O20 I/O21 VSSQ Q I/O22 I/O23 1 2 3 4 5 6 7 8 9 10 11 12 13 80 79 78 77 76 75 74 73 72 71 70 69 68 / (1) 14 67 15 PKG100 66 VSS

52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O15 I/O14 Q VSSQ I/O13 I/O12 I/O11 I/O10 VSSQ Q I/O9 I/O8 VSS ZZ (2) I/O7 I/O6

5 IDT71V632, 64K x 32, 3.3V SRAM Pin Configuration A6 A7 CS0 BW4 BW3 BW2 BW1 CS1 VSS BWE A8 A I/O16 I/O17 Q VSSQ I/O18 I/O19 I/O20 I/O21 VSSQ Q I/O22 I/O / (1) PKG VSS I/O24 I/O25 Q VSSQ I/O26 I/O27 I/O28 I/O29 VSSQ Q I/O30 I/O I/O15 I/O14 Q VSSQ I/O13 I/O12 I/O11 I/O10 VSSQ Q I/O9 I/O8 VSS ZZ (2) I/O7 I/O6 Q VSSQ I/O5 I/O4 I/O3 I/O2 VSSQ Q I/O1 I/O0 LBO A5 A4 A3 A2 A1 A0 VSS A10 A11 A12 A13 A14 A drw 02 Top View TQFP 1. Pin 14 can either be directly connected to or not connected. 2. Pin 64 can be left unconnected and the device will always remain in active mode

6 IDT71V632, 64K x 32, 3.3V SRAM Truth Table (1,2) Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Cycle, Begin Burst Cycle, Begin Burst Cycle, Begin Burst Cycle, Begin Burst Cycle, Begin Burst Cycle, Begin Burst Cycle, Begin Burst 1. L = VIL, H = VIH, X = Don t Care. 2. ZZ = LOW for this table. 3. is an asynchronous input. Used CS0 CS BWE BWX E O ( 3) CL K None H X X X L X X X X X Hi-Z None L X H L X X X X X X Hi-Z None L L X L X X X X X X Hi-Z None L X H X L X X X X X Hi-Z None L L X X L X X X X X Hi-Z External L H L L X X X X X L DOUT External L H L L X X X X X H Hi-Z External L H L H L X H H X L DOUT External L H L H L X H L H L DOUT External L H L H L X H L H H Hi-Z External L H L H L X H L L X DIN External L H L H L X L X X X DIN X X X H H L H H X L DOUT X X X H H L H H X H Hi-Z X X X H H L H X H L DOUT X X X H H L H X H H Hi-Z H X X X H L H H X L DOUT H X X X H L H H X H Hi-Z H X X X H L H X H L DOUT H X X X H L H X H H Hi-Z X X X H H L H L L X DIN X X X H H L L X X X DIN H X X X H L H L L X DIN H X X X H L L X X X DIN X X X H H H H H X L DOUT X X X H H H H H X H Hi-Z X X X H H H H X H L DOUT X X X H H H H X H H Hi-Z H X X X H H H H X L DOUT H X X X H H H H X H Hi-Z H X X X H H H X H L DOUT H X X X H H H X H H Hi-Z X X X H H H H L L X DIN X X X H H H L X X X DIN H X X X H H H L L X DIN H X X X H H L X X X DIN I/ O 3619 tbl 07

7 IDT71V632, 64K x 32, 3.3V SRAM Function Truth Table (1) Operation BWE BW1 BW2 BW3 BW4 H H X X X X H L H H H H all Bytes L X X X X X all Bytes H L L L L L ( 2) W rite Byte 1 H L L H H H ( 2) W rite Byte 2 H L H L H H ( 2) W rite Byte 3 H L H H L H ( 2) W rite Byte 4 H L H H H L 1. L = VIL, H = VIH, X = Don t Care. 2. Multiple bytes may be selected during the same cycle tbl 08 Asynchronous Truth Table (1) 2) O peration ( ZZ I/O Status L L Data Out (I/ O0 - I/ O3 1) Active X L High-Z Data In (I/ O0 - I/ O3 1) Active H L High-Z Deselected X L High-Z Sleep X H High-Z 1. L = VIL, H = VIH, X = Don t Care. 2. function pi must be biased appropriately to satisfy operation requirements. Power Active Standby Sleep 3619 tbl 09 Interleaved Burst Sequence Table (LBO=) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Second Third ( 1) F ourth NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. Linear Burst Sequence Table (LBO=VSS) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Second Third ( 1) F ourth tbl 10 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state tbl

8 IDT71V632, 64K x 32, 3.3V SRAM 3,4) S A4 ( 5 DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ( = 3.3V +10/-5%) Symbol Parameter ILI Leakage IL ZZ ZZ and IL O VO L 3.3V) LBO Output Leakage ( Output Low Voltag e VO H 3.3V) ( Output High Voltag e 1) I nput Leakage = Max., V N I = 0V to V D ( = Max., VI N = 0V to V D C E IOL IOH > VIH or O E > VIH V T est Conditio M in. Max. NOTE: 1. The LBO pin will be internally pulled to if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1) (VHD = Q 0.2V, VLD = 0.2V) S S6 S7 Unit D 5 µ A D 30 µ A, OUT = 0V to, VD D Max. = 5 µ A = 5mA, VD D = Min V = 5mA, VD D = Min V 3619 tbl 12 Symbol Parameter T est Conditio C om'l. I nd. C om'l. I nd. C om'l. I nd. C om'l. Ind. Unit IDD Operating Power Supply Device Selected, Outputs Open, = Max., VI N > VIH o r < VI L, (2) f = fmax ma ISB Standby Power Supply Device Deselected, Outputs Open, = Max., VI N > VIH o r < VI L, (2) f = fmax ma ISB1 Full Standby Power Supply Device Deselected, Outputs Open, = Max., VI N > VHD o r < VL D, (2) f = ma IZZ I/O Full Sleep Mode Power Supply AC Test Loads Z0 = 50Ω Z Z > VHD V, D D Max. 50Ω = ma 1. All values are maximum guaranteed values. 2. At f = fmax, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while = LOW; f=0 mea no input lines are changing. 3. SA4 speed grade corresponds to a tcd of C to +70 C temperature range only. +3.3V Q/2 I/O 351Ω 317Ω 5pF* 3619 tbl 13 tcd (Typical, ) Figure 1. AC Test Load Capacitance (pf) 3619 drw drw 05 Figure 3. Lumped Capacitive Load, Typical Derating * Including scope and jig capacitance. Figure 2. High-Impedence Test Load (for tohz, tchz, tolz, and tdc1) AC Test Conditio Pulse Rise/Fall Timing Output Timing AC Test Load Levels Times Reference Levels Reference Levels 3619 drw 04 0 to 2 3.0V 1.5V 1.5V See Figures 1 and tbl 14

9 IDT71V632, 64K x 32, 3.3V SRAM Symbol CLOCK PARAMETERS t CYC Parameter Clock Cycle Time. 5 tc H ( 1) lock High Pulse Widt h C. 5 tc L ( 1) lock Low Pulse Widt h OUTPUT PARAMETERS tcd t CDC C. 5 C lock High to Valid Data Clock High to Data Change. 5 2) tclz ( lock High to Output Activ e 5,6) 71V632SA4 C 0 t t ( 1V632S5 AC Electrical Characteristics (, Q = 3.3V +10/-5%, ) 7 71V632S6 71V632S7 M in. M ax. M in. M ax. M in. M ax. M in. Max Unit _ _ C O utput Enable Access Time 2) OLZ ( utput Enable Low to Data Activ e O 0 2) tchz ( lock High to Data High- Z 2) tohz ( O utput Enable High to Data High- Z SETUP TIMES tsa tss tsd tsw t SAV tsc HOLD TIMES tha ths thd thw t HAV thc Setup Time. 2 Status Setup Time. 2 Data in Setup Time. 2 Setup Time. 2 Advance Setup Time. 2 Chip Enable/Select Setup Time. 2 Hold Time. 5 Status Hold Time. 5 Data In Hold Time. 5 Hold Time. 5 Advance Hold Time. 5 Chip Enable/Select Hold Time. 5 SLEEP MODE AND CONFIGURATION PARAMETERS t ZZP W ZZ Pulse Width 00 3) tzzr ( Z Recovery Tim e Z 00 4) tcfg ( onfiguration Set-up Tim e C _ 6 _ _ tbl Measured as HIGH above 2.0V and LOW below 0.8V. 2. Traition is measured ±200mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tcfg is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation. 5. The 71V632SA4 speed grade corresponds to a tcd of C to +70 C temperature range only

10 IDT71V632, 64K x 32, 3.3V SRAM Timing Waveform of Pipelined Cycle (1,2) tcyc tss tch tcl ths (1) tsa tha ADDRESS Ax Ay tsw thw, BWE, BWx tsc thc, CS1 (Note 3) tsav thav t ierts a wait-state tcd DATAOUT tolz O1(Ax) tohz tclz tcdc (Burst wraps around to its initial state) tchz O1(Ay) O2(Ay) O3(Ay) O4(Ay) O1(Ay) O2(Ay) Output Disabled Pipelined Burst Pipelined 3619 drw O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. ZZ input is LOW and LBO is Don t Care for this cycle. 3. CS0 timing traitio are identical but inverted to the and CS1 signals. For example, when and CS1 are LOW on this waveform, CS0 is HIGH

11 IDT71V632, 64K x 32, 3.3V SRAM Timing Waveform of Combined Pipelined and Cycles (1,2,3) tcyc tss ths tch tcl (2) tsa tha ADDRESS Ax Ay Az tsw thw tsd thd t DATAIN tcd tohz tclz I1(Ay) tolz tcdc DATAOUT O1(Ax) O1(Az) O2(Az) O3(Az) Single Pipelined Pipelined Burst 3619 drw Device is selected through entire cycle; and CS1 are LOW, CS0 is HIGH. 2. ZZ input is LOW and LBO is Don t Care for this cycle. 3. O1(Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay. O1(Az) represents the first output from the external addresss Az; O2(Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input

12 IDT71V632, 64K x 32, 3.3V SRAM Timing Waveform of Cycle No. 1 Controlled (1,2,3) tcyc tss tch tcl ths tha tsa Ax Ay Az ADDRESS thw BWE is ignored when initiates burst tsw tsc thc tsav thav, CS1 (Note 3) ( suspends burst) thd tsd I1(Ax) I1(Ay) I2(Ay) I2(Ay) I3(Ay) I4(Ay) I1(Az) I2(Az) I3(Az) DATAIN tohz O3(Aw) O4(Aw) DATAOUT Burst Burst Burst 3104 drw 08 Single. 1. ZZ input is LOW, BWE is HIGH, and LBO is Don t Care for this cycle. 2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2(Ay) this data is valid for two cycles because is high and has suspended the burst. 3. CS0 timing traitio are identical but inverted to the and CS1 signals. For example, when and CS1 are LOW on this waveform, CS0 is HIGH

13 IDT71V632, 64K x 32, 3.3V SRAM Timing Waveform of Cycle No. 2 Byte Controlled (1,2,3) tcyc tss tch tcl ths ADDRESS tha tsa Ax Ay Az BWE thw BWE is ignored when initiates burst tsw BWx thw BWx is ignored when initiates burst tsw, CS1 (Note 3) tsc thc tsav ( suspends burst) tsd thd DATAIN I1(Ax) I1(Ay) I2(Ay) I2(Ay) I3(Ay) I4(Ay) I1(Az) I2(Az) I3(Az) tohz DATAOUT O3(Aw) O4(Aw) Burst Single Burst Extended Burst 3104 drw ZZ input is LOW, is HIGH, and LBO is Don t Care for this cycle. 2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2(Ay) this data is valid for two cycles because is high and has suspended the burst. 3. CS0 timing traitio are identical but inverted to the and CS1 signals. For example, when and CS1 are LOW on this waveform, CS0 is HIGH

14 IDT71V632, 64K x 32, 3.3V SRAM Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3) tcyc tss tch tcl ths ADS C ADDRESS tsa Ax tha tsc thc, CS1 (Note 4) t tolz DATAOUT O1(Ax) tzzr ZZ tzzpw Single Snooze Mode 1. Device must power up in deselected Mode. 2. LBO input is Don t Care for this cycle. 3. It is not necessary to retain the state of the input registers throughout the Power-down cycle. 4. CS0 timing traitio are identical but inverted to the and CS1 signals. For example, when and CS1 are LOW on this waveform, CS0 is HIGH. Az 3104 drw

15 IDT71V632, 64K x 32, 3.3V SRAM Non-Burst Cycle Timing Waveform ADDRESS Av Aw Ax Ay Az, BWE, BWx, CS1 CS0 DATAOUT (Av) (Aw) (Ax) (Ay) 3619 drw 11, 1. ZZ input is LOW, is HIGH and LBO is Don t Care for this cycle. 2. (AX) represents the data for address AX, etc. 3. For read cycles, and function identically and are therefore interchangeable

16 IDT71V632, 64K x 32, 3.3V SRAM Non-Burst Cycle Timing Waveform ADDRESS Av Aw Ax Ay Az, CS1 CS0 DATAIN (Av) (Aw) (Ax) (Ay) (Az) 3619 drw 12, 1. ZZ input is LOW, and are HIGH, and LBO is Don t Care for this cycle. 2. (AX) represents the data for address AX, etc. 3. Although only writes are shown, the functionality of BWE and BWx together is the same as. 4. For write cycles, and have different limitatio

17 IDT71V632, 64K x 32, 3.3V SRAM Ordering Information XXXX Device Type S Power X Speed XX Package X X Process/ Temperature Range X Blank 8 Blank I(1) Tray Tape and Reel Commercial (0 C to +70 C) Industrial (-40 C to +85 C) G (2) Green PF 100-Pin TQFP (PKG100) A (3) Access Time of Nanoseconds 71V632 64K x 32 Pipelined Burst SRAM, 3619 drw Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. 3. Commercial only. Part Number Speed in Megahertz tcd Parameter Clock Cycle Time 71V632SA4PF 117 MHz V632S5PF 100 MHz V632S6PF 83 MHz V632S7PF 66 MHz tbl

18 IDT71V632, 64K x 32, 3.3V SRAM Datasheet Document History 9/9/99 Updated to new format Pg. 1, 8, 9, 17 Revised speed offerings to MHz Pg. 15, 16 Added non-burst read and write cycle timing diagrams Pg. 18 Added Datasheet Document History 09/30/99 Pg. 1, 4, 8, 9, 17 Added industrial temperature range offerings 04/04/00 Pg. 17 Added 100pinTQFP package Diagram Outline 08/09/00 Not recommended for new desig 08/17/01 Removed Not recommended for new desig from the background on the datasheet 02/28/07 Pg. 18 Added Z generation die step to data sheet ordering information. 10/16/08 Pg. 18 Removed IDT from orderable part number. 05/27/10 Pg. 17 Added "Restricted hazardous substance device" to the ordering information 02/24/17 Pg. 1 Removed Z from device part number Added green availability to features Pg. 5 Update PK100-1 to package code PKG100 and restore overbars Pg. 14 Restored Sleep (ZZ) Timing Waveform Pg. 16 Restored Non-Burst Cycle Timing Waveform Removed PSC Package Diagram Pg. 17 Restored Ordering Information: Added Green,Tape & Reel, Tray and footnote indicators Removed Z Die Stepping indicator in Ordering Information CORPORATE HEADQUARTERS for SALES: 6024 Silver Creek Valley Road or San Jose, CA fax: The IDT logo is a registered trademark of Integrated Device Technology, Inc. for Tech Support: sramhelp@idt.com

SRAM with ZBT Feature, Burst Counter and Pipelined Outputs

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