Degradation Mechanisms of Amorphous InGaZnO Thin-Film Transistors Used in Foldable Displays by Dynamic Mechanical Stress

Transcription

1 170 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 1, JANUARY 2017 Degradation Mechanisms of Amorphous InGaZnO Thin-Film Transistors Used in Foldable Displays by Dynamic Mechanical Stress Sang Myung Lee, Student Member, IEEE, Dongseok Shin, Student Member, IEEE, and Ilgu Yun, Senior Member, IEEE Abstract Foldable displays represent one of the most attractive next-generation display applications. Therefore, it is critical to analyze the effects of mechanical stress on amorphous InGaZnO (a-igzo) thin-film-transistors (TFTs) in order to apply them to foldable displays. In foldable display applications, the dynamic mechanical stress tests are designed to be carried out using a bending radius of less than 3 mm. In this paper, dynamic mechanical bending stress tests are performed on a-igzo TFTs using various bending radii and directions in order to examine the instability characteristics of the TFTs. In addition, the degradation mechanisms are investigated using a technology computeraided design simulation. As a result, we have demonstrated that it is now possible to establish reliable circuit guidelines for using a-igzo TFTs in foldable display applications. Index Terms Amorphous InGaZnO (a-igzo), bending direction, degradation mechanism, foldable display, mechanical stress, modeling and simulation. I. INTRODUCTION AMORPHOUS InGaZnO (a-igzo) is an attractive active material that is suitable for use in foldable thin-filmtransistor (TFT) displays, because it exhibits high mobility and has a low fabrication temperature [1]. However, in order to use this foldable TFT in industrial applications, the mechanical stress effects must be first characterized. This is critical because mechanical stress generates defects or cracks in the TFTs, which degrade the operational characteristics and reliability of the devices. Previous research has focused on the influence of compressive [2] or tensile [3] bending stress on TFTs in only a single bending direction; however, to the best of our knowledge, the influence and geometry of cracks on the active layer have not yet been reported. The reason may be due to the fact that it is difficult to directly observe the generated cracks because of the etch stopper layer and the fact that the cracks are randomly generated. Regardless, the degradation Manuscript received November 17, 2016; accepted November 18, Date of publication December 5, 2016; date of current version December 24, This work was supported in part by LG Display and in part by the Institute of BioMed-IT, Energy-IT, and Smart-IT Technology, a Brain Korea 21 Plus Program, Yonsei University. The review of this paper was arranged by Editor M. M. Hussain. The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea ( iyun@yonsei.ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED Fig. 1. Schematic structure of the tested a-igzo TFTs. mechanisms caused by dynamic mechanical stress have not been previously investigated. In this paper, the effects of mechanical stress on the electrical characteristics of a-igzo TFTs are investigated. A series of dynamic mechanical stress tests are performed, and the electrical variations are characterized as a function of the bending radius and direction. Next, we modify the active layer structure to produce different types of cracks, and then analyzed the corresponding electrical effects and degradation mechanisms using a technology computer-aided design (TCAD) simulation. Finally, we propose guidelines for the reliable circuit design using a-igzo TFTs based on the test results. II. DEVICE STRUCTURE AND EXPERIMENT A. Dynamic Mechanical Stress Test The a-igzo TFTs in this paper are fabricated on a polyimide substrate with Cu/MoTi is used as the gate. A SiO 2 layer is then added to act as a gate insulator, and the a-igzo active layer is formed on top of the SiO 2 layer. The etch stopper layer is deposited next, followed by the deposition of the Cu/MoTi source and drain electrodes. By varying the channel width (W) and length (L), six distinct devices with different geometries are fabricated for the analysis (W/L [μm/μm] = 12/8, 12/16, 16/8, 16/16, 24/8, 24/16). Fig. 1 shows a schematic diagram of the tested TFTs, which have a bottom-gate, top-contact structure. The current voltage (I V ) characteristics are measured using a Keithley 236 source measure unit, and the dynamic mechanical stress IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 LEE et al.: DEGRADATION MECHANISMS OF a-igzo TFTs 171 Fig. 2. Dynamic mechanical bending stress tester. is applied using the flexible materials tester from Hansung Systems Inc., as shown in Fig. 2. Three different bending radii, namely, 1 (1R), 2 (2R), and 3 mm (3R), and two bending directions with respect to the source-to-drain current path, namely, perpendicular and parallel, are used when performing the dynamic mechanical stress tests. Fig. 3. Schematic of the simulated device structure with (a) vertical and (b) horizontal cracks. TABLE I Descriptions for Simulated Structures B. TCAD Modeling Scheme and Experiment For the TCAD simulation, the Silvaco TCAD simulation tool is used. In this paper, we assume that the total density of states (DOS) was composed of four bands consisting of two tail bands and two deep level bands, and these bands are modeled using a Gaussian distribution. In an exponential tail distribution, the DOS can be described using the conduction and valence band edge intercept densities (N TA and N TD ), and by the characteristic decay energy (W TA and W TD ). The values are used for the defect parameters in the TCAD simulation were N TA = cm 3 /ev, W TA = 0.02 ev, N GA = cm 3 /ev, and W GA = ev [4], and these values are consistent with those for tested oxide TFTs. The active layer material is a-igzo with a thickness of 50 nm. The channel is designed to be 16 μm wideand 16 μm long in order to avoid channel size effects. We then design crack structures on the simulated device in order to observe the effects of the cracks. At first, a single trench is built on the active layer in order to analyze the effects of trench-type cracks, such as the crack position, trench depth (TD), and trench width (TW). The bridge-type cracks are then created in the TCAD simulation to analyze the effects of this structure. After the dynamic mechanical stress tests are completed, the device laid in a reflat condition in order to measure the transfer curve. In this procedure, a small contact is made on the channel layer, referred to as the bridge in this paper, before implementing the same structure in the TCAD simulation where the crack is formed as a vacuum. The schematics of trench-type and bridge-type cracks are shown in Fig. 3(a). We then analyze the effects of the bridge depth, bridge thickness (BT), and crack width (CW). We also create a horizontal crack effect between the gate and gate insulator layer to analyze the effects of shearing mechanical stress, as shown in Fig. 3(b). The descriptions for simulated structures are shown in Table I. In this paper, all structural modification simulated results are used the Monte Carlo technique for statistical analysis. All of the sample sizes of the simulated results with Monte Carlo technique are over The uniform distribution is used for the Monte Carlo technique. III. RESULTS AND DISCUSSION A. Degradation via Bending Radius and Bending Direction In previous research, mechanical stress has been shown to generate cracks that disturb the movement of the carriers, especially in the channel of the TFT [5]. In this section, we examine the degradation caused by applying 5000 cycles of bending tests. The dynamic mechanical stress tests are performed on devices of various sizes using several bending radii that were perpendicular to the source drain current path. The measurement conditions are V DS = 2.1 V and V GS was swept from 10 to 15 V. For the normalized data, the ON-current is defined as the drain current at V DS = 2.1 V and V GS = 15 V. The normalized ON-current is calculated as I ON,Norm = I ON,5000 (1) I ON,Init where I ON,Norm is the normalized ON-current, I ON,Init is the initial ON-current before the mechanical stress is applied, and I ON,5000 is the ON-current after 5000 bending cycles are applied.

3 172 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 1, JANUARY 2017 Fig. 4. Normalized ON-current after application of 5000 cycles of parallel mechanical stress and various bending radii. As shown in Fig. 4, it can be seen that the TFTs that underwent 3R or 2R bending curvatures during testing exhibited almost no degradation, while the TFTs that underwent 1R bending curvature during testing exhibited severe degradation under parallel strain. To calculate the strain on the foldable TFTs, we assume that the strain (ε) is applied to the tested TFT where a neutral plane was formed in the middle of the total thickness. Using this approximation, the strain on the TFT device can be calculated as [6] substrate thickness + TFT stack thickness strain =. (2) 2 bending radius The calculated strains for the 3R, 2R, and 1R curvatures are 0.28%, 0.56%, and 0.84%, respectively. It is found that bending curvatures over 2R did not generate enough strain to degrade the TFT being tested. For this reason, the following experiments only analyzed the results of the TFTs tested with a bending curvature of 1R. In order to analyze the degradation effects under different bending directions, experiments are performed that varied the channel size. The measurements assumed V DS = 2.1 V, and V GS is swept from 10 to 15 V. In terms of the normalized data, we select the I DS result when V GS = 15 V. In the dynamic mechanical stress tests, the strain is applied by subjecting the TFTs to outward bending in both the parallel and perpendicular directions with respect to the source drain current path. The degradation caused by the effects of the parallel strain, as shown in Fig. 5, is more severe than the degradations caused by the effects of the perpendicular strain. Since the generated cracks can disturb the movement of the carriers, and the direction of the cracks depends on the bending direction, the cracks caused by the perpendicular strain have negligible influence on the movement of the carriers, because the direction of the cracks is almost the same as the direction of the carrier movement [5]. However, parallel strain causes cracks that are perpendicular to the source drain current path, and these can physically block carrier movement, resulting in the electrical characteristic degradation of the TFTs. Fig. 5. Normalized I ON with various bending directions and the application of 5000 bending cycles on devices of various sizes. Therefore, the carrier mobility is more significantly affected by parallel strain than it is by perpendicular strain. If the number of bending cycles is increased, the bridge depth and length will also increase causing device performance to degrade [7], [8]. B. Degradation Analysis Using a TCAD Simulation During the mechanical stress tests, vertical-type cracks are generated in the channel. To simulate the effects of these cracks, a single trench-type crack structure is designed on the active layer in the TCAD simulation, and the TD and width are varied. The tests caused a crack seed to form in the channel. The stress intensity factor at any point along the crack front in a finite thickness plate can be expressed according to [7], [8] K = (S t + H j S b ) π a Q F j (3) where K is the stress intensity factor, S t is the remote uniform tension stress, H j is the bending multiplier representing the stress intensity for remote bending, S b is the remote bending stress on the outer fibers, a is the depth of the crack, Q is the shape factor for an elliptical crack, and F j is the boundarycorrection factor for the stress intensity of the remote tension. Each crack seed generated in the channel causes a single crack to form. In addition, the crack growth rate can be calculated by assuming the Paris relationship between crack growth rate and stress intensity factor range [9]. To obtain more accurate simulation results, we measure the crack sizes on the tested device using a focused-ion-beam measurement system. The results are shown in Fig. 6, indicating that the bridge that is formed varied from 5 to 40 nm in width. Consequently, the CWs in this simulation are designed to be less than 40 nm. The simulated results of the single trench-type structure are shown in Fig. 7. In this simulation, we assumed that the channel is connected with a 5-nm-thickness trench, and the generated crack depth was 45 nm.

4 LEE et al.: DEGRADATION MECHANISMS OF a-igzo TFTs 173 Fig. 6. Measurement results showing the CW in the channel using a focused-ion-beam measurement. Fig. 8. Transfer curves resulting from different measurement conditions. Fig. 7. Simulated result of the 45-nm TD structure with different TWs. In the simulation results, the ON-current slightly decreased due to the trench. However, TW variation showed no difference performance. The reason is that the TW is nanoscale and it is not enough to make significant differences on the potential energy concentration into the channel. In addition, trench-type cracks alone are not sufficient to explain the device degradation results. In the bottom-gate TFT structure, carriers accumulate on the bottom of the channel and trenchtype cracks do not disturb the accumulation process in the channel until they are fully disconnected from the current path. Therefore, in order to explain the degradation results, other types of crack structures are needed, such as bridge-type cracks. In the dynamic mechanical stress experiment after the strain and bending cycles are applied, the transfer curve that is measured under the flat and bending conditions exhibited different tendencies. The results of the bending conditions fully show the failure characteristics. However, after the strain is released and the transfer curve is measured in flat conditions on the same device, the ON-current is found to have increased. The experimental results are shown in Fig. 8. Fig. 9. Normalized ON-current resulting from different crack positions and bridge depths. Fig. 8 shows the results for a device with a 16-μm-channel width and 8-μm-channel length device under parallel strain, 1R bend radius, and 5000 cycles of mechanical stress test under different measurement conditions. The strain is 0.84%, and the calculated CW is nm for the 1R bending condition. However, the reflat condition acted to shrink the length of the crack, and the active layer around the crack is reorganized, causing some parts to create bridges. This reduces the resistance of the crack and causes a current path to reform on the channel. In this paper, the connections at the surface of the active layer and at the bottom of the active layer are defined as the top and the bottom bridge, respectively. Fig. 9 shows the results of the normalized ON-currents for different crack positions and bridge depths. In Fig. 9, the crack position means the generated crack position between source and drain. Therefore, the 4-μm crack position means that the crack generated closer to source side. In addition, the BT is assumed with 5 nm, and the variations of the bridge depth are 0 45 nm. In this case, the 0-nm bridge depth means that

5 174 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 1, JANUARY 2017 Fig. 11. Simulated transfer curves with top position bridge type and horizontal cracks. Fig.10. Normalized ON-current resulting from (a) different bridge depths with BT variations and (b) different CWs with BTs variations. the bridge generated at the top of the channel. In addition, 45-nm bridge depth generates a bridge at the bottom of the channel, which is the same with the trench. As shown in Fig. 9, the crack position does not affect significantly on device operations. However, a bridge in the top position caused more degradation to the TFT characteristics due to the potential energy. The reason is a top positioned bridge that has a relatively weak potential energy, which disturbs the generation of the channel. According to Fig. 9, the bridge, which generated on the top of the channel, is the most degrade the device operation. However, to specify the effects of the BT variation, the Monte Carlo technique is also used. Fig. 10(a) also shows that the top positioned with thin BTs bridge shape cracks more degrades the device operations. In addition, to more specific analysis of the top positioned bridge structures, CW and BT are changed. Fig. 10(b) shows a CW and BT relationship. As a result, the ON-current changes as CW variations. However, in this case, the BT is more crucial, because increased BT is also the bottom of the bridge that is closer to the gate and it has higher potential energy. In addition to the crack types already described, dynamic mechanical stress can also generate horizontal cracks in the interlayer due to the shearing stress. In the TCAD simulation, horizontal cracks that formed as a vacuum are designed between the gate insulator and the gate. A schematic diagram of the generated vertical and horizontal cracks is shown in Fig. 3(b). Our results show that the cracks that are generate increased the total insulating factor on the device and causes the device characteristics to be degraded. The simulated results are shown in Fig. 11. The results of the simulation are based on several vertical and horizontal cracks. A 40-nm-wide vertical crack structure is designed with a 5-nm-thick top bridge in the middle of the device. In addition, a horizontal crack is designed to be 20 nm thick and 6 μm wide between the gate and gate insulator layer. The experimental results are based on the application of only 5000 cycles of dynamic mechanical stress, which are not enough to cause the device to fail completely. The simulation results show that the horizontal crack type can slightly degrade the device characteristics; however, it is not enough to explain fully degraded device characteristics. Therefore, other mechanisms are needed. After a bridge is built on the channel, the carrier movement is disturbed by the bottleneck effect. Therefore, if the bridge connects the fractured channel, the interface of the crack is poor and increases the corresponding effect on the channel. This effect is simulated by increased the N TA parameter. The generated vertical crack space is modeled as a vacuum and it increases the N TA value in the bridge region that generates the bottleneck. In this simulation, the horizontal crack is removed to focus on the effect of defects. As a result, an increase in the value of N TA, which increases the defects in the channel, causes the device characteristics

6 LEE et al.: DEGRADATION MECHANISMS OF a-igzo TFTs 175 generated by the application of dynamic mechanical stress. Horizontal-type cracks served to increase the total insulating characteristics of the device, and vertical-type cracks disturbed the carrier movement and channel generation, especially during the accumulation process. After the dynamic mechanical stress test, a bridge was formed on the channel by the reflat procedure used for transfer curve measurement, which caused a bottleneck effect on the channel. The top contact, which was the top bridge, was the most degraded structure and increased the defect value of the bridge area, causing a fully degraded simulation result. Based on these results, the reliability of the TFT devices can be enhanced if the current path of the TFTs is parallel to the direction of folding. It was clear that understanding the effects of the cracks that were generated in the channel was crucial. Fig. 12. N TA value variation results with (a) normalized ON-current and (b) transfer curves with a top position bridge type structure. to increasingly degraded, as shown in Fig. 12(a). Usingthe simulated result of Fig. 12(b), we compare with cycles of mechanical stress tests, which made it is possible to fully simulate the degraded characteristics using this structure. IV. CONCLUSION In this paper, we analyzed the electrical effects of cracks under dynamic bending stress on flexible a-igzo TFTs using a TCAD simulation. To analyze the effects of cracks, we performed experiments with various bending radii and bending directions. Then, vertical and horizontal cracks types were simulated using the TCAD simulation tool. Parallel strain with respect to the source-to-drain current path resulted in greater degradation of the device characteristics than did perpendicular strain. Cracks parallel to the direction of the current path caused less disturbance to the movement of the carriers than perpendicular cracks did. Therefore, although the same bending cycles were applied to the device, perpendicular bending resulted in greater device degradation. In addition, vertical and horizontal type cracks were REFERENCES [1] M. Kim et al., High mobility bottom gate InGaZnO thin film transistors with SiO etch stopper, Appl. Phys. Lett., vol. 90, p , May [2] M. C. Wang, T. C. Chang, P.-T. Liu, S. Tsao, Y. Lin, and J. Chen, The instability of a-si:h TFT under mechanical strain with high frequency ac bias stress, Electrochem. Solid-State Lett., vol. 10, no. 10, pp. J113 J116, [3] M. Ito et al., Amorphous oxide TFT and their applications in electrophoretic displays, Phys. Status Solidi A, vol. 205, no. 8, pp , Aug [4] N. Münzenrieder, C. Zysset, L. Petti, T. Kinkeldei, G. A. Salvatore, and G. Tröster, Flexible double gate a-igzo TFT fabricated on free standing polyimide foil, Solid-State Electron., vol. 84, pp , Jun [5] ATLAS User s Manual. Santa Clara, CA, USA: Silvaco International, [6] J.-M. Kim et al., Atomic layer deposition ZnO:N flexible thin film transistors and the effects of bending on device properties, Appl. Phys. Lett., vol. 98, no. 14, p , [7] J. C. Newman, Jr., and I. Raju, An empirical stress-intensity factor equation for the surface crack, Eng. Fract. Mech., vol. 15, nos. 1 2, pp , [8] J. C. Newman, Jr., and I. S. Raju, Stress-intensity factor equations for cracks in three-dimensional finite bodies, in Fracture Mechanics: Fourteenth Symposium Theory and Analysis, vol.1.west Conshohocken, PA, USA: ASTM International, [9] P. C. Paris, The fracture mechanics approach to fatigue, in Proc. 10th Saga More Army Mater. Res. Conf., 1964, pp Sang Myung Lee (S 13) received the B.S. degree in electronic communication engineering from Hanyang University, Ansan, South Korea, in He is currently pursuing the joint M.S./Ph.D. degree in electrical and electronic engineering with Yonsei University, Seoul, South Korea. His current research interests include characterization, modeling, and simulation of semiconductor devices and statistical modeling of semiconductor devices using technology computer-aided design. Dongseok Shin (S 13) received the B.S. degree in electrical and electronic engineering from Yonsei University, Seoul, South Korea in 2013, where he is currently pursuing the joint M.S./Ph.D. degree in electrical and electronic engineering. His current research interests include characterization, modeling, and simulation of semiconductor devices and statistical modeling of semiconductor devices using technology computer-aided design. Ilgu Yun (SM 03) received the B.S. degree in electrical engineering from Yonsei University, Seoul, South Korea, in 1990, and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 1995 and 1997, respectively. He is currently a Professor of Electrical and Electronic Engineering with Yonsei University and the senior member of IEEE.