DSP Design Lecture 5. Dr. Fredrik Edman.

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1 SP esign SP esign Lecture 5 Retiming r. Fredrik Edman fredrik.edman@eit.lth.se Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

2 SP esign Repetition Critical path - the combinational path with maximum total execution time Loop (=cycle) - a path beginning and ending at same node Loop bound for loop T W j j loop computation time number of delays in loop Iteration Bound - maximum of all loop bounds = t T max l l L w l (3) (6) (1) B C It is the lower bound on execution time for FG (assuming only pipelining, retiming, unfolding) Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

3 SP esign Fine-Grain pielining x(n) Feedforward cutset h0 h1 (6) (4) h h3 (10) () () y(n) x(n) (6) (4) () y(n-1) (6) Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

4 SP esign a Parallel Processing b x(n) ax(n) abx(n) x(0), x(1), x()... k=0,1,,3... a b x(k) ax(k) abx(k) x(0), x(), x(4)... a b x(k+1) ax(k+1) abx(k+1) x(1), x(3), x(5)... Two samples are processed in parallel => double throughput or lower power consumption due to reduced V When block size is, 1 delay element = sampling delays x(k) x(k-) Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

5 SP esign Power Consumption The power consumption in original architecture P = seq f C L V The supply voltage can be reduced to β V, (0<β <1). Hence, the power consumption of the pipelined filter is: P pipe = f C L ( ) β V = β P seq f P LC V P L β ( ) para = L = β seq Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

6 SP esign The Effect of Pipelining and Parallelization We have seen that the power can be significantly reduced in a system using pipelining and parallelization. P = f C V Pipelining only Ppipe = f 1.1C (0.58V) = 0.37P f a Register b Register c Register Parallelization only Ppar = 0.5f.15C (0.58V) = 0.36P Pipe- and Parallelization Ppar, pipe = 0.5f.35C (0.4V) = 0.19P Compare Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

7 SP esign Pipelining Propagation delays of the sequential and the pipelined architecture: T seq = k C V, T ( C = M ) L L pip ( V VT ) k( βv VT ) β V The capacitance in each stage has been reduced. Since the same f is maintained T seq =T pipe M ( βv VT ) = β ( V VT Solve the equation to find valid β! Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden- )

8 SP esign Retiming Chapter 4. Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

9 SP esign What is retiming?? Retiming is a transformation technique used to change the location of delay elements in a circuit without affecting the characteristics of the circuit. Can be used for: - Reducing the clock period - Reducing the number of registers - Reducing the power consumption - Logic synthesis (not in this course) The lower bound on the clock period of the circuit can be achieved by retiming the circuit. Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

10 SP esign Retiming is about moving delays! elays can be moved from ALL inputs to ALL outputs Reduce Critical Path faster reduced power consumption Reduced number of Register Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

11 SP esign () (4) A Critical path = 6 Retiming Retiming does not change delay in loop T the iteration bound = B Loop bound = 6/ = 3 t max l l L w l Loop bound = () (4) A W B Critical path = 4 Loop bound = 6/ = 3...but it changes the critical path! T j j loop computation time number of delays in the loop Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

12 SP esign Retiming Techniques Cutset retiming and pipelining Systolic transformation Retiming Formulation Retiming for clock period minimization Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

13 SP esign x(n) Ex. Cutset Retiming T A = t.u. T M = 4 t.u. y(n) () 1 a b () (4) 3 (4) 4 Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

14 SP esign Ex. Cutset Retiming Cutset: A set of edges that if removed, or cut, results in two disjoint graphs. () () 1 (4) 3 Graph G Cutset Retiming Add k delays to edges going one way and remove k delays from ones going the other. Graph G 1 (4) 4 Cutset Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

15 SP esign Ex. Cutset Retiming Cutset Retiming: Add delays to edges going one way and remove from edges going the other. () 1 Graph G () 1 3 () T crit =4+=6 #=4 (4) (4) 3 4 Cutset () T crit =4++=8 #=5 Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden- (4) (4) 3 4

16 SP esign Ex. Node Cutset Retiming Node Retiming: Cutset around one node. () Cutset 1 () 1 () T crit =4+=6 #=4 (4) (4) 3 4 () (4) (4) 3 4 T crit =+=4 #=5 Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

17 SP esign Pipelining Pipelining is a special case of cutset retiming where there are no edges in the cutset from G to G 1, i.e., pipelining applies to graphs without loops. Retiming is a generalization of pipelining Pipelining is equivalent to introducing delays at the input followed by retiming Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

18 SP esign Pipelining Feedforward Cutset Pipelining is a special case of cutset retiming: Placing delays at feedforward cutsets. x(n) h0 h1 h h3 y(n) Feedforward cutset Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

19 SP esign Retiming Techniques Cutset retiming and pipelining Systolic transformation Retiming Formulation Retiming for clock period minimization Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

20 SP esign Systolic Transformation Eliminating global broadcasting Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

21 SP esign Retiming Techniques Cutset retiming and pipelining Systolic transformation Retiming Formulation Retiming for clock period minimization Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

22 SP esign Retiming Formulation ω(e) = weight of edge e = # of delays r(x) = retiming values r(u) U ω(e) V r(v) U ω r (e) V estination/receive Source/send ω r (e) = ω(e) + r(v) - r(u) Valid retiming if all ω r (e) >= 0 for all edges! Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

23 SP esign Retiming Formulation 1 Graph G Each node in G1 has retiming value j and each node in G has Graph G 1 3 retiming value j+k Any value j results in the 4 same retimed graph. Valid retiming only if all ω r (e) >= 0 Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

24 G 1 SP esign 1 Cutset Node Retiming with Formulation G 3 4 Original weights ( ω(e) ) 1 3 = = 1 = 1 3 = 0 4 = 0 Choose any retiming values G =0 r(1)=r(3)=r(4)=0 G 1 =1 r()=1 Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

25 SP esign Node Retiming with Formulation Original weights = 1 = 1 = = = 0 0 Retiming values r(1)=0, r()=1, r(3)=0 and r(4)=0 ω r (e) = ω(e) + r(v) - r(u) Receive Send 1 3= = 1 1 4= + 0 0= 1= = 0 3 = = 1 4 = = 1 Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

26 SP esign Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden Node Retiming with Formulation (3) Retimed weights = = = = = Algorithm for clock period minimization in 4.4. Retimed Graph

27 SP esign Node Retiming with Formulation (3) What happened is that delays have been moved around Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

28 SP esign Retiming Techniques Cutset retiming and pipelining Systolic transformation Retiming Formulation Retiming for clock period minimization Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

29 SP esign Retiming for Minimizing Clock Period Note that retiming will NOT alter the iteration bound T. Iteration bound is the theoretical minimum clock period to execute the algorithm. Let edge e connect node u to node v. If the node computing time t(u) + t(v) > T, then clock period T > T. For such an edge, we require that wr () e 1 In other words, for any possible critical path in the FG that is larger than T, we require w r (e) 1. Formula: Retiming for Minimizing Clock Period (1) Check that t(u) + t(v) T then w r (e) 0 if t(u)+t(v)=t w r (e) 1 if t(u)+t(v)>t () Solve w r (e uv ) = w(e) + r(v) r(u) (3) Check that the retime values are valid! Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

30 SP esign Ex. Retiming for Minimizing Clock Period Check that t(u) + t(v) T then w r (e) 0 if t(u)+t(v)=t w r (e) 1 if t(u)+t(v)>t w r (e 1 ) 0, since t()+t(1) = = T. w r (e 13 ) 1, since t(1)+t(3) = 3 > T. w r (e 14 ) 1, since t(1)+t(4) = 3 > T. w r (e 3 ) 1, since t(3)+t() = 3 > T. w r (e 4 ) 1, since t(4)+t() = 3 > T. Use eq. w r (e uv ) = w(e) + r(v) r(u) then T = w(e 1 ) + r(1) r() = 1 + r(1) r() 0 w(e 13 ) + r(3) r(1) = 1 + r(3) r(1) 1 w(e 14 ) + r(4) r(1) = + r(4) r(1) 1 w(e 3 ) + r() r(3) = 0 + r() r(3) 1 w(e 4 ) + r() r(4) = 0 + r() r(4) 1 Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

31 SP esign Ex. Retiming for Minimizing Clock Period Since the retimed graph G r remain the same if all node retiming values are added by the same constant. We thus can set r(1) = 0. The inequalities then become: 1 r() 0 or r() r(3) 1 or r(3) 0 + r(4) 1 or r(4) 1 r() r(3) 1 or r(3) r() 1 r() r(4) 1 or r() r(4) + 1 However for larger systems Since 1 r() r(3) =+ 1 one must have r() = +1. This implies r(3) 0. But we also have r(3) 0. Hence r(3)=0. These leave 1 r(4) 0. Hence the two sets of solutions are: r(0) = r(3) = 0, r() = +1, and r(4) = 0 or ( 1). Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

32 SP esign Solving a Systems of Inequalities Given a systems of inequalities: r(i) r(j) k; 1 i,j N Construct a constraint graph: 1. Map each r(i) to node i. Add a node N+1.. For each inequality r(i) r(j) k, draw an edge e ji such that w(e ji ) = k. 3. raw N edges e N+1,i = 0. The system of inequalities has a solution if and only if the constraint graph contains no negative cycles If a solution exists, one solution is where r i is the minimum length path from the node N+1 to the node i. Shortest path algorithms: (Applendix A) Bellman-Ford algorithm Floyd-Warshall algorithm See chapter 4.4. Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

33 SP esign Retiming Relationship Pipelining Cutset Retiming Systolic Transformation Retiming Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

34 SP esign rawbacks with Retiming The state encoding of the circuit may be destroyed, making testing and verification more difficult. Some retimed circuits may require complicated initialization logic to have the circuit start in a special initial state. Retiming changes the circuit's topology which have consequences in other logical and physical synthesis steps that make design closure more difficult. Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

35 SP esign Time Scaling using Slow own and Retiming A slow down process is often used in combination with the cutset retiming process - Replace each delay in a FG with N delays - N-slow FG N-1 - Null operations (or 0 samples) must be interleaved to preserve the functionality Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

36 SP esign Time Scaling (Slow own) Transform each delay element (register) to N Reduce the sample frequency by N-fold to slow down the computation N times. x(3) x() x(1) add mult y(3) y() y(1) -- x(3) -- x() -- x(1) In slow down the clock cycle time remains unchanged. Only the sampling time is increased. add mult y(3) -- y() -- y(1) This provides opportunity for retiming, and interleaving. Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

37 SP esign Replace each by k Slow own by k (1) (1) Clock 0 A0 B0 A B 1 A1 B1 A B After -slow transformation (1) A B (1) Clock 0 A0 B0 1 A1 B1 3 4 A B T clk = t.u. T iter = t.u. T clk = t.u. T iter = t.u. =4t.u. Input new samples every alternate cycles. null operations account for odd clock cycles. Hardware utilized only 50% time Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

38 SP esign Example: 3-stage Lattice Filter Loop Bounds L1 L L3 T T L1 L = = 3T 5T Add Add + T 1 + T Mult Mult T L3 = 5T Add + T 3 Mult Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

39 SP esign Example: 3-stage Lattice Filter Iteration Bound T = { T, T, T, K } max L1 L L3 = 3T Add + T 1 Mult Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

40 SP esign Example: 3-stage Lattice Filter Critical Path Critical Path Critical Path = (N+1) Adders + Mult N = Number of Stages Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

41 SP esign Example: 3-stage Lattice Filter Cutset Retiming Cutset Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

42 SP esign Example: 3-stage Lattice Filter Cutset Retiming Critical Path = 4 Adders + 4 Mult Independent of N = nr. of stages in filter compared to Original Critical Path = (N+1) Adders + Mult Worse for Low N. Trade-off depends on T M and T A Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

43 SP esign Compare: Cutset Retiming of a 4-stage Lattice Filter Move every second delay Critical Path = 4Adders + 4Mult Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

44 SP esign Compare: Cutset Retiming of a 5-stage Lattice Filter Critical Path = 4Adders +4Mult Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

45 SP esign Example: 3-stage Lattice Filter Cutset Retiming with Slowdown Critical Path Critical Path = (N+1) Adders + Mult N = Number of Stages Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

46 SP esign Example: 3-stage Lattice Filter Slowdown by factor Critical Path Critical Path has not changed. Same f clk. Insertion of 0 samples to preserve behavior! x 0 x 0 x 1 x 1 x x x 3 x 3... or x 0 0 x 1 0 x 0 x Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

47 SP esign Example: 3-stage Lattice Filter Slowdown by factor Cutsets Add delays on Edges in one direction and remove in the other Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

48 SP esign Example: 3-stage Lattice Filter Slowdown by factor Critical Path Critical Path = Adders + Mult But requires twice the number of clock cycles Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

49 SP esign Register Minimization y 1 y 1 3 y 4 y 3 7 y 3 y Register Sharing When a node has multiple fanout with different number of delays, the registers can be shared so that only the branch with max. # of delays will be needed. Register reduction through node delay transfer from multiple input edges to output edges (e.g. r(v) > 0) Should be done only when clock cycle constraint (if any) is not violated. Algorithm for register minimization in Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

50 SP esign End of Retiming Fredrik Edman, ept. of Electrical and Information Technology, Lund University, Sweden-

VLSI Signal Processing

VLSI Signal Processing Lecture 1 Pipelining & Retiming ADSP Lecture1 - Pipelining & Retiming (cwliu@twins.ee.nctu.edu.tw) 1-1 Introduction DSP System Real time requirement Data driven synchronized by data