Signal Flow Graphs. Roger Woods Programmable Systems Lab ECIT, Queen s University Belfast

Transcription

1 Signal Flow Graphs Roger Woods Programmable Systems Lab ECIT, Queen s University Belfast (Slides 2-13 taken from Signal Flow Graphs and Data Flow Graphs chapter by Keshab K. Parhi and Yanni Chen)

2 Contents Signal Flow Graphs (SFGs) DSP characteristcs Transfer FuncTon DerivaTon of SFG Mason s Gain Formula Data Flow Graphs (DFGs) DFG representatons Equivalent Single- rate from MulT- rate DFG SFG/DFG transformatons ReTming Pipelining 2

3 Signal Flow Graph RepresentaTon DSP characteristcs Data independence Input samples are processed periodically (typically a clock) Tasks are repeated infinite number of Tmes => non- terminatng programs High computatonal requirements Trend towards DSP micros and FPGAs Towards SFGs (and DFGs) powerful representatons of signal processing algorithms as they represent the operatons using a finite number of nodes 3

4 Key features of SFGs SFGs can be transformed using retming, pipelining, unfolding and folding resultng forms have same input- output characteristcs but different constraints Pipelining and retming can be used to reduce clock period Folding can be used to Tme- multplex i.e. reduce area Unfolding leads to: lower iteraton periods in so`ware implementatons (by highlightng concurrency) Faster hardware by exploitng parallel implementatons Key goal of transforming representaton to meet performance requirements by adaptng levels of pipelining and parallelism (or both) 4

5 Signal Flow Graph SFG is a collecton of nodes and directed edges A directed edge (j,k) denotes a linear transform from the signal at node j to the signal at node k Edges are usually restricted to multplier or delay elements 5

6 TransposiTon Flow graph reversal/transpositon can be applied to single- input single- output (SISO) systems by reversing directons of all edges, exchanging input/output nodes while keeping edge gain or edge delay unchanged 6

7 Mason's gain formula A few useful terminologies in Mason's gain formula have to be defined related to an SFG Forward path: a path that connects a source node to a sink node in which no node is traversed more than once. Loop: a closed path without crossing the same point more than once. Loop gain: the product of all the transfer functons in the loop. Non- touching or non- interactng loops: two loops are non- touching or non- interactng if they have no nodes in common. 7

8 Mason's gain formula M = transfer functon or gain of the system Y = output node X = input node N = total number of forward paths between X and Y Δ = determinant of the graph = 1- loop gains + non- touching loop gains taken two at a Tme - non- touching loop gains taken three at a Tme + M j = gain of the j th forward path between X and Y Δ j = 1- loops remaining a`er eliminatng the j th forward path i.e. eliminate the loops touching the j th forward path from the graph. If none of the loops remains, Δ j = 1. 8

9 SFG example 1) Find the forward paths and their corresponding gains Two forward paths exist in this SFG: M 1 = G 1 G 2 G 3 and M 2 = G 4 2) Find the loops and their corresponding gains There are four loops in this example: Loop 1 = - G 1 H 1 Loop 2 = - G 3 H 2 Loop 3 = - G 1 G 2 G 3 H 3 Loop 4 = - G 4 H 3 9

10 SFG example (Cont d) 3) Find the Δ j If we eliminate the path M 1 =G 1 G 2 G 3 from the SFG, no complete loops remain, so Δ 1 = 1. Similarly, if the path M 2 =G 4 is eliminated from the SFG, no complete loops remain neither, so Δ 2 = 1 as well. 4) Find the determinant Δ Only one pair of non- touching loops is in this SFG, i.e. Loop 1 and Loop 2, thus non- touching loop gains taken two at a Tme = (- G 1 H 1 )(- G 3 H 2 ). Therefore, 10

11 SFG example (Cont d) Δ = 1- loop gains + non- touching loop gains taken 2 at a Tme = 1 - (- G 1 H 1 - G 3 H 2 - G 1 G 2 G 3 H 3 - G 4 H 3 ) + (- G 1 H 1 )(- G 3 H 2 ) = 1 + G 1 H 1 + G 3 H 2 + G 1 G 2 G 3 H 3 + G 4 H 3 + G 1 G 3 H 1 H 2 5) The final step is to apply the Mason's gain formula 11

12 Data Flow Graph In DFGs, nodes represent computatons/functons and directed edges represent data paths with non- negatve numbers associated with them Captures data- driven property of DSP algorithms - node fires when all input data is available. y n = ay n- 1 + x n Block diagram ConvenTonal DFG Synchronous DFG 12

13 SDFGs and mult- rate Synchronous DFG is a DFG special case where the number of data samples produced or consumed by each node in each executon is specified a priori can be used for mult- rate A, B &C operate at frequencies f A, f B & f C A consumes f A samples & produces 3f A samples per Jme unit. B consumes 5f B samples, therefore using equality 3f A = 5f B, we have f B =3 f A /5. Equivalent SFG Similarly, f C = 2f B /3 = 2f A /5 which can be used to compute the frequencies for A, B and C for a specified required input sample rate. 13

14 SequenTal algorithms OperaTons are one a`er other. Throughput dictated by the Tme to perform P 1, P 2 and P 3. OperaTons can be carried out at the same Tme. 14

15 Some definitons - Latency Latency Tme needed to generate an output from when the corresponding input is entered. Throughput rate is defined as the rate at which the outputs (and/or inputs) are produced. 15

16 Why is latency important? Latency can dictate performance in applicatons with feedback loops 16

17 MulTplexing Technique to increase the throughput rate of sequental algorithms Processors (PEs) will operate in a Tme shared fashion. 17

18 MulTplexing SequenTal: TR = 1/(tP 1 + tp 2 + tp 3 ) and output every cycle. E.g. if tp 1 = tp 2 = tp 3 =10, TR=1/30 Interleaved: TR = 1/ (tp 1 or tp 2 or tp 3 ) E.g. if tp 1 = tp 2 = tp 3 =10, TR=1/10 tp n time taken for processor P n 18

19 Some definitons - pipelining Method to increase the throughput rate of a sequental (and parallel) algorithm TR = 1/ (tp 1 or tp 2 or tp 3 ) If tp 1 = tp 2 = tp 3 =10, TR=1/10 Problems in feedback loops allow interleaving only. clock rate = f output = 1 per cycle TR = f clock rate = 4Xf output = 1 per 4 cycles TR = f 19

20 ApplicaTon of pipelining # Clock Input Node 1 Node 2 Node 3 Output 0 x 0 a 0 x 0 1 x 1 a 0 x 1 a 0 x 0 a 0 x 0 y 0 2 x 2 a 0 x 2 a 0 x 1 + a 1 x 0 a 0 x 1 + a 1 x 0 y 1 3 x 3 a 0 x 3 a 0 x 2 + a 1 x 1 a 0 x 2 + a 1 x 1 + a 2 x 0 y 2 4 x 4 a 0 x 4 a 0 x 3 + a 1 x 2 a 0 x 3 + a 1 x 2 + a 2 x 1 y 3 20

21 ApplicaTon of pipelining #2 Why not apply pipelining to adder chain in FIR filter? Clock Input Node 1 Node 2 Node 3 Output 0 x 0 a 0 x 0 1 x 1 a 0 x 1 a 0 x 0 2 x 2 a 0 x 2 a 0 x 1 + a 1 x 0 a 0 x 0 y 0 3 x 3 a 0 x 3 a 0 x 2 + a 1 x 1 a 0 x 1 + a 1 x 0 + a 2 x 0 X 4 x 4 a 0 x 4 a 0 x 3 + a 1 x 2 a 0 x 2 + a 1 x 1 + a 2 x 1 X 21

22 Formal method to apply pipelining Problem was that pipelining was not applied in a systematc fashion providing a functonal change in the system specificaton i.e. changing the actual functon. A systematc approach is thus required to apply retming to the system in such a way that it does not corrupt the system specificaton. ReTming equates to moving around existng delays Does not alter the latency of the system Reduces (hopefully) the critcal path of the system Can be employed to retme the node 22

23 FormulaTon of retming ReTming FormulaTon w = w + r(v) - r(u) ProperTes of retming Weight of the retmed path p = V > V >..V k is given by w r (p)= w (p) + r(v k ) - r(v 0 ) ReTming does not change the number of delays in a cycle. ReTming does not alter the iteraton bound (see later) in a DFG as the number of delays in a cycle does not change Adding the constant value j to the retming value of each node does not alter number of delays in edges of the retmed graph. 23

24 ReTming of FIR Filter Express as DFG w r (1 2) = w(1 2) + r(2)- r(1) 2,3,4 are multpliers, w r (1 3) = w(1 3) + r(3)- r(1) 5, 6 are adders, 1 is x input w r (1 4) = w(1 4) + r(4)- r(1) Can express relatonships w r (2 5) = w(2 5) + r(5)- r(2) for all edges w r (3 5) = w(3 5) + r(5)- r(3) w r (4 6) = w(4 6) + r(6)- r(4) w r (5 6) = w(5 6) + r(6)- r(5) 24

25 ReTming of FIR Filter Using the following retming values, r(1)=- 1, r(2)=- 1, r(3)=- 1, r(4)=- 1, r(5)=0, r(6)=0 we get a pipeline a`er the multpliers w r (1 2) = w(1 2) + r(2)- r(1) w r (1 3) = w(1 3) + r(3)- r(1) w r (1 4) = w(1 4) + r(4)- r(1) w r (2 5) = w(2 5) + r(5)- r(2) w r (3 5) = w(3 5) + r(5)- r(3) w r (4 6) = w(4 6) + r(6)- r(4) w r (5 6) = w(5 6) + r(6)- r(5) = 0 + (- 1) (- 1) = 0 = 1 + (- 1) (- 1) = 1 = 2 + (- 1) (- 1) = 2 = 0 + (0) (- 1) = 1 = 0 + (0) (- 1) = 1 = 0 + (0) (- 1) = 1 = 0 + (0) (0) = 0 25

26 Conclusions RepresentaTons for DSP systems Signal Flow Graphs (SFGs) Transfer FuncTon DerivaTon using Mason s Gain Formula Data Flow Graphs (DFGs) Various form including synchronous DFG ConstrucTng an Equivalent Single- rate DFG from MulT- rate TransformaTons Pipelining allows speed of resultng implementatons to be increased. ReTming can be used to perform delay transfer but that is only part of the issue. Can increase(unfold)/decrease(fold) parallelism to match performance covered later 26