INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET F a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Infmation The IC06 74C/CT/CU/CMOS ogic Package Outlines 74C/CT4067 File under Integrated Circuits, IC06 September 1993

2 Philips Semiconducts 74C/CT4067 FEATURES ow ON resistance: 80 (typ.) at = V 70 (typ.) at = V 60 (typ.) at = V typical break befe make built-in Output capability: non-standard I CC categy: MSI GENERA DESCRIPTION The 74C/CT4067 are high-speed Si-gate CMOS devices and are pin compatible with the 4067 of the 4000B series. They are specified in compliance with JEDEC standard no. 7A. The 74C/CT4067 are multiplexers/demultiplexers with four address inputs (S 0 to S 3 ), an active OW enable input (E), sixteen independent inputs/outputs (Y 0 to Y 15 ) and a common input/output (Z). The 4067 contains sixteen bidirectional analog switches, each with one side connected to an independent input/output (Y 0 to Y 15 ) and the other side connected to a common input/output (Z). With E OW, one of the sixteen switches is selected (low impedance ON-state) by S 0 to S 3. All unselected switches are in the high impedance OFF-state. With E IG, all switches are in the high impedance OFF-state, independent of S 0 to S 3. The analog inputs/outputs (Y 0 to Y 15, and Z) can swing between as a positive limit and as a negative limit. to may not exceed 10 V. QUICK REFERENCE DATA = 0 V; T amb = 25 C; t r = t f = 6 ns SYMBO PARAMETER CONDITIONS t PZ / t PZ turn-on time C = 15 pf; R =1 k; = 5 V Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD V 2 CC f i + {(C + C S ) V 2 CC f o } where: f i = input frequency in Mz f o = output frequency in Mz {(C + C S ) V 2 CC f o } = sum of outputs C = output load capacitance in pf C S = max. switch capacitance in pf = supply voltage in V 2. F C the condition is V I = to F CT the condition is V I = to 1.5 V TYPICA E to V os ns S n to V os ns t PZ / t PZ turn-off time E to V os ns S n to V os ns C I input capacitance pf C PD power dissipation capacitance per switch notes 1 and pf C S max. switch capacitance independent (Y) 5 5 pf common (Z) pf C CT UNIT September

3 Philips Semiconducts 74C/CT4067 ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Infmation. PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1 Z common input/output 9, 8, 7, 6, 5, 4, 3, 2, 23, 22, 21, 20, 19, 18, 17, 16 Y 0 to Y 15 independent inputs/outputs 10, 11, 14, 13 S 0 to S 3 address inputs 12 ground (0 V) 15 E enable input (active OW) 24 positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. September

4 Philips Semiconducts 74C/CT4067 APPICATIONS Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating FUNCTION TABE Fig.4 Functional diagram. INPUTS E S 3 S 2 S 1 S 0 CANNE ON Y 0 Z Y 1 Z Y 2 Z Y 3 Z Y 4 Z Y 5 Z Y 6 Z Y 7 Z Y 8 Z Y 9 Z Y 10 Z Y 11 Z Y 12 Z Y 13 Z Y 14 Z Y 15 Z X X X X none Notes 1. = IG voltage level = OW voltage level X = don t care Fig.5 Schematic diagram (one switch). September

5 Philips Semiconducts 74C/CT4067 Fig.6 ogic diagram. September

6 Philips Semiconducts 74C/CT4067 RATINGS imiting values in accdance with the Absolute Maximum System (IEC 134) Voltages are referenced to (ground = 0 V) SYMBO PARAMETER MIN. MAX. UNIT CONDITIONS DC supply voltage V ±I IK DC digital input diode current 20 ma f V I < 0.5 V I > V ±I SK DC switch diode current 20 ma f V S < 0.5 V S > V ±I S DC switch current 25 ma f 0.5 V < V S < V ±I CC ; ±I DC current 50 ma T stg stage temperature range C P tot power dissipation per package f temperature range: 40 to +125 C 74C/CT plastic DI 750 mw above +70 C: derate linearly with 12 mw/k plastic mini-pack (SO) 500 mw above +70 C: derate linearly with 8 mw/k P S power dissipation per switch 100 mw Note 1. To avoid drawing current out of terminal Z, when switch current flows in terminals Y n, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no current will flow out of terminals Y n. In this case there is no limit f the voltage drop across the switch, but the voltages at Y n and Z may not exceed. RECOMMENDED OPERATING CONDITIONS SYMBO PARAMETER 74C 74CT min. typ. max. min. typ. max. UNIT CONDITIONS DC supply voltage V V I DC input voltage range V V S DC switch voltage range V T amb operating ambient temperature range C see DC and AC T amb operating ambient temperature range C CARACTER- ISTICS t r,t f input rise and fall times 1000 = 2.0 V ns = V = V = 10.0 V September

7 Philips Semiconducts 74C/CT4067 DC CARACTERISTICS FOR 74C/CT F 74C: = 2.0,, and V F 74CT: = V SYMBO R ON PARAMETER ON-resistance (peak) T amb ( C) 74C/CT to to +125 min. typ. max. min. max. min. max R ON ON-resistance (rail) R ON maximum variation of ON-resistance between any two channels UNIT (V) TEST CONDITIONS I S (µa) V is to to V I V I V I V I V I V I V I Notes 1. At supply voltages ( ) approaching 2 V, the analog switch ON-resistance becomes extremely non-linear. Therefe it is recommended that these devices be used to transmit digital signals only, when using these supply voltages. 2. F test circuit measuring R ON see Fig.7. Fig.7 Test circuit f measuring ON-resistance (R ON ). Fig.8 Test circuit f measuring OFF-state current. September

8 Philips Semiconducts 74C/CT4067 Fig.9 Test circuit f measuring ON-state current. Fig.10 Typical ON-resistance (R ON ) as a function of input voltage (V is ) f V is = 0 to. DC CARACTERISTICS FOR 74C Voltages are referenced to (ground = 0 V) T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74C to to +125 UNIT (V) V I OTER min. typ. max. min. max. min. max. V I IG level input voltage V 2.0 V I OW level input voltage V 2.0 ±I I input leakage current µa 10.0 ±I S analog switch OFF-state current per channel µa 10.0 V I V I V S = (see Fig.8) ±I S analog switch OFF-state current all channels µa 10.0 V I V I V S = (see Fig.9) ±I S analog switch ON-state current µa 10.0 V I V I V S = (see Fig.9) I CC quiescent supply current µa 10.0 V is = ; V os = September

9 Philips Semiconducts 74C/CT4067 AC CARACTERISTICS FOR 74C = 0 V; t r =t f = 6 ns; C = 50 pf SYMBO t P / t P t P / t P t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ PARAMETER propagation delay V is to V os ; Y n to Z propagation delay V is to V os ; Z to Y n T amb ( C) 74C to to +125 min. typ. max. min. max. min. max turn-off time 74 E to Y n turn-off time 83 S n to Y n turn-off time EtoZ turn-off time S n to Z turn-on time 80 E to Y n turn-on time 88 S n to Y n turn-on time E to Z turn-on time S n to Z UNIT TEST CONDITIONS (V) OTER R = ; C = 50 pf (see Fig.16) R =1k; C = 50 pf (see Fig.17) September

10 Philips Semiconducts 74C/CT4067 Note to AC CARACTERISTICS FOR 74C 1. Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal. DC CARACTERISTICS FOR 74CT Voltages are referenced to (ground = 0 V) T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74CY to to +125 min. typ. max. min. max. min. max. UNIT (V) V I OTER V I V I IG level input voltage OW level input voltage V to V to 5.5 ±I I input leakage current µa 5.5 ± I S analog switch OFF-state current per channel ±I S analog switch OFF-state current all channels ±I S analog switch ON-state current I CC I CC Note quiescent supply current additional quiescent supply current per input pin f unit load coefficient is 1 (note 1) µa 5.5 V I V I µa 5.5 V I V I µa 5.5 V I V I µa to µa to V V S = (see Fig.8) V S = (see Fig.9) V S = (see Fig.9) V is = ;V os = other inputs at 1. The value of additional quiescent supply current ( I CC ) f a unit load of 1 is given here. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT OAD COEFFICIENT E 0.6 S n 0.5 September

11 Philips Semiconducts 74C/CT4067 AC CARACTERISTICS FOR 74CT = 0 V; t r =t f = 6 ns T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74CT to to +125 min. typ. max. min. max. min. max. UNIT (V) OTER t P / t P t P / t P t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ Note propagation delay V is to V os ; Y n to Z ns propagation delay V is to V os ; Z to Y n ns turn-off time ns E to Y n turn-off time S n to Y n ns turn-off time ns E to Z turn-off time ns S n to Z turn-on time ns E to Y n turn-on time ns S n to Y n turn-on time ns E to Z turn-on time ns S n to Z R = ; C = 50 pf (see Fig.16) R = 1 k; C = 50 pf (see Fig.17) 1. Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal. September

12 Philips Semiconducts 74C/CT4067 ADDITIONA AC CARACTERISTICS FOR 74C/CT Recommended conditions and typical values = 0 V; t r =t f = 6 ns SYMBO PARAMETER TYP. UNIT (V) V is(p-p) (V) CONDITIONS f max C S sine-wave disttion f = 1 kz sine-wave disttion f = 10 kz switch OFF signal feed-through minimum frequency response ( 3 db) maximum switch capacitance independent (Y) common (Z) % % % % db db Mz Mz pf pf note 3 note 4 R = 10 k; C = 50 pf (see Fig.14) R = 10 k; C = 50 pf (see Fig.14) R = 600 ; C = 50 pf f = 1 Mz (see Figs 11 and 15) R =50;C = 10 pf (see Figs 12 and 13) Notes 1. V is is the input voltage at Y n Z terminal, whichever is assigned as an input. 2. V os is the output voltage at Y n Z terminal, whichever is assigned as an output. 3. Adjust input voltage V is is 0 dbm level (0 dbm = 1 mw into 600 ). 4. Adjust input voltage V is is 0 dbm level at V os f 1 Mz (0 dbm = 1 mw into 50 ). September

Test conditions: = V; = 0 V; R =50;R source =1 k. Fig.12 Typical frequency response.

13 Philips Semiconducts 74C/CT4067 Test conditions: = V; = 0 V; R =50;R source =1 k. Fig.11 Typical switch OFF signal feed-through as a function of frequency. Test conditions: = V; = 0 V; R =50;R source =1 k. Fig.12 Typical frequency response. Adjust input voltage to obtain 0 dbm at V os when f in = 1 Mz. After set-up frequency of f in is increased to obtain a reading of 3 db at V os. Fig.13 Test circuit f measuring minimum frequency response. September

14 Philips Semiconducts 74C/CT4067 Fig.14 Test circuit f measuring sine-wave disttion. Fig.15 Test circuit f measuring switch OFF signal feed-through. AC WAVEFORMS (1) C : V M = 50%; V I = to. CT : V M = 1.3 V; V I = to 3 V. Fig.16 Wavefms showing the input (V is ) to output (V os ) propagation delays. Fig.17 Wavefms showing the turn-on and turn-off times. September

15 Philips Semiconducts 74C/CT4067 TEST CIRCUIT AND WAVEFORMS Conditions TEST SWITC V is t PZ t PZ t PZ t PZ others open pulse C = load capacitance including jig and probe capacitance (see AC CARACTERISTICS f values). R T = termination resistance should be equal to the output impedance Z O of the pulse generat. t r = t f = 6 ns, when measuring f max, there is no constraint on t r,t f with 50% duty fact. Fig.18 Test circuit f measuring AC perfmance. FAMIY AMPI- TUDE V M t r,t f f max ; PUSE WIDT OTER 74C 50% < 2 ns 6 ns 74CT 3.0 V 1.3 V < 2 ns 6 ns Fig.19 Input pulse definitions. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. September

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET F a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Infmation The IC6 74C/CT/CU/CMOS ogic