INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete ata sheet, please also ownloa: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic Package Outlines 74C/CT59 8-bit aressable latch Prouct specification File uner Integrate Circuits, IC6 December 199

2 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 FEATURES Combines emultiplexer an 8-bit latch Serial-to-parallel capability Output from each storage bit available Ranom (aressable) ata entry Easily expanable Common reset input Useful as a 3-to-8 active IG ecoer Output capability: stanar I CC category: MSI GENERA DESCRIPTION The 74C/CT59 are high-spee Si-gate CMOS evices an are pin compatible with low power Schottky TT (STT). They are specifie in compliance with JEDEC stanar no. 7A. The 74C/CT59 are high-spee 8-bit aressable latches esigne for general purpose storage applications in igital systems. The 59 are multifunctional evices capable of storing single-line ata in eight aressable latches, an also 3-to-8 ecoer an emultiplexer, with active IG outputs (Q to Q 7 ), functions are available. The 59 also incorporates an active OW common reset (MR) for resetting all latches, as well as, an active OW enable input (E). The 59 has four moes of operation as shown in the moe select table. In the aressable latch moe, ata on the ata line (D) is written into the aresse latch. The aresse latch will follow the ata input with all non-aresse latches remaining in their previous states. In the memory moe, all latches remain in their previous states an are unaffecte by the ata or aress inputs. In the 3-to-8 ecoing or emultiplexing moe, the aresse output follows the state of the D input with all other outputs in the OW state. In the reset moe all outputs are OW an unaffecte by the aress (A to A ) an ata (D) input. When operating the 59 as an aressable latch, changing more than one bit of aress coul impose a transient-wrong aress. Therefore, this shoul only be one while in the memory moe. The moe select table summarizes the operations of the 59. QUICK REFERENCE DATA GND = V; T amb =5 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P/ t P propagation elay C = 15 pf; V CC =5 V D to Q n 18 ns A n, E to Q n 17 ns t P MR to Q n 15 ns C I input capacitance pf C PD power issipation capacitance per latch notes 1 an pf Notes 1. C PD is use to etermine the ynamic power issipation (P D in µw): P D =C PD V CC f i + (C V CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V CC f o ) = sum of outputs C = output loa capacitance in pf V CC = supply voltage in V. For C the conition is V I = GND to V CC For CT the conition is V I = GND to V CC 1.5 V December 199

3 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1,, 3 A to A aress inputs 4, 5, 6, 7, 9 1, 11, 1 Q to Q 7 latch outputs 8 GND groun ( V) 13 D ata input 14 E latch enable input (active OW) 15 MR conitional reset input (active OW) 16 V CC positive supply voltage Fig.1 Pin configuration. Fig. ogic symbol. Fig.3 IEC logic symbol. December 199 3

4 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 Fig.4 Functional iagram. MODE SEECT TABE E MR MODE aressable latch memory active IG 8-channel emultiplexer reset December 199 4

5 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 FUNCTION TABE OPERATING MODES INPUTS OUTPUTS MR E D A A 1 A Q Q 1 Q Q 3 Q 4 Q 5 Q 6 Q 7 master reset X X X X emultiplex (active IG) ecoer (when D = ) store (o nothing) X X X X q q aressable latch Notes 1. = IG voltage level = OW voltage level X = on t care = IG or OW ata one set-up time prior to the OW-to-IG E transition q = lower case letters inicate the state of the reference output establishe uring the last cycle in which it was aresse or cleare Q= Q= q q q q q q q Q= Q= Q= q q Q= q q q q q Q= Q= Q= Q= Q= Q= Q= Q= Q= Q= December 199 5

6 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 Fig.5 ogic iagram. December 199 6

7 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: stanar I CC category: MSI AC CARACTERISTICS FOR 74C GND = V; t r =t f = 6 ns; C = 5 pf SYMBO t P / t P t P / t P t P / t P t P PARAMETER propagation elay 58 D to Q n 1 17 propagation elay 58 A n to Q n 1 17 propagation elay 55 E to Q n 16 propagation elay 5 MR to Q n t T / t T output transition time t W t W t su t h t h E pulse with IG or OW MR pulse with OW set-up time D, A n to E hol time D to E hol time A n to E T amb ( C) 74C +5 4 to to +15 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) WAVEFORMS Fig.7 Fig.8 Fig.6 Fig.9 Figs 6 an 7 Fig.6 Fig.9 Figs 1 an 11 Fig.1 Fig.11 December 199 7

8 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: stanar I CC category: MSI Note to CT types The value of aitional quiescent supply current ( I CC ) for a unit loa of 1 is given in the family specifications. To etermine I CC per input, multiply this value by the unit loa coefficient shown in the table below. INPUT A n E D MR UNIT OAD COEFFICIENT December 199 8

9 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 AC CARACTERISTICS FOR 74CT GND = V; t r =t f = 6 ns; C = 5 pf T amb ( C) TEST CONDITIONS ns Fig ns Fig ns Fig ns Fig.9 74CT SYMBO PARAMETER UNIT V WAVEFORMS +5 4 TO TO +15 CC (V) min. typ. max. min. max. min. max. t P / t P propagation elay D to Q n t P / t P propagation elay A n to Q n t P / t P propagation elay E to Q n t P propagation elay MR to Q n t T / t T output transition time ns Figs 6 an 7 t W t W t su t su t h t h E pulse with OW MR pulse with OW set-up time D to E set-up time A n to E hol time D to E hol time A n to E ns Fig ns Fig ns Fig ns Fig.11 8 ns Fig.1 4 ns Fig.11 December 199 9

10 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 AC WAVEFORMS (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.6 Waveforms showing the enable input (E) to output (Q n ) propagation elays, the enable input pulse with an the output transition times. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the ata input (D) to output (Q n ) propagation elays an the output transition times. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.8 Waveforms showing the aress inputs (A n ) to outputs (Q n ) propagation elays an the output transition times. December 199 1

11 Philips Semiconuctors Prouct specification 8-bit aressable latch 74C/CT59 (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.9 Waveforms showing the conitional reset input (MR) to output (Q n ) propagation elays. The shae areas inicate when the input is permitte to change for preictable output performance. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.1 Waveforms showing the ata set-up an hol times for the D input to E input. The shae areas inicate when the input is permitte to change for preictable output performance. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.11 Waveforms showing the aress set-up an hol times for A n inputs to E input. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS