DATA SHEET. HEF4520B MSI Dual binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

Size: px

Start display at page:

Download "DATA SHEET. HEF4520B MSI Dual binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS"

Meryl Stokes
5 years ago
Views:

1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC File under Integrated Circuits, IC04 January 1995

2 DESCRIPTION The is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP 0 ) and an active LOW clock input (CP 1 ), buffered outputs from all four bit positions (O 0 to O 3 ) and an active HIGH overriding asynchronous master reset input (MR). The counter advances on either the LOW to HIGH transition of the CP 0 input if CP 1 is HIGH or the HIGH to LOW transition of the CP 1 input if CP 0 is low. Either CP 0 or CP 1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O 0 to O 3 = LOW) independent of CP 0, CP 1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.2 Pinning diagram. Fig.1 Functional diagram. P(N): 16-lead DIL; plastic (SOT38-1) D(F): 16-lead DIL; ceramic (cerdip) (SOT74) T(D): 16-lead SO; plastic (SOT109-1) (SOT109-1) ( ): Package Designator North America PINNING CP 0A,CP 0B CP 1A, CP 1B MR A,MR B O 0A to O 3A O 0B to O 3B clock inputs (L to H triggered) clock inputs (H to L triggered) master reset inputs outputs outputs FAMILY DATA, I DD LIMITS category See Family Specifications January

3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be... January FUNCTION TABLE CP 0 CP 1 MR MODE H L counter advances L L counter advances X L no change X L no change L L no change H L no change X X H O 0 to O 3 = LOW Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition Fig.3 Logic diagram (one counter). Philips Semiconductors

4 AC CHARACTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays CP 0, CP 1 O n ns 83 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 39 ns + (0,23 ns/pf) C L ns 32 ns + (0,16 ns/pf) C L ns 83 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 39 ns + (0,23 ns/pf) C L ns 32 ns + (0,16 ns/pf) C L MR O n ns 48 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 24 ns + (0,23 ns/pf) C L Output transition ns 17 ns + (0,16 ns/pf) C L times ns 10 ns + (1,0 ns/pf) C L HIGH to LOW 10 t THL ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L ns 10 ns + (1,0 ns/pf) C L LOW to HIGH 10 t TLH ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L Minimum CP ns pulse width; LOW 10 t WCPL ns Minimum CP ns pulse width; HIGH 10 t WCPH ns Minimum MR ns pulse width; HIGH 10 t WMRH ns ns Recovery time ns for MR 10 t RMR ns Set-up times ns CP 0 CP 1 10 t su ns ns CP 1 CP 0 10 t su ns Maximum clock MHz pulse frequency 10 f max MHz MHz see also waveforms Figs 4 and 5 January

5 AC CHARACTERISTICS V SS = 0 V; T amb =25 C; input transition times 20 ns V DD V TYPICAL FORMULA FOR P (µw) Dynamic power f i + (f o C L ) V 2 DD where dissipation per f i + (f o C L ) V 2 DD f i = input freq. (MHz) package (P) f i + (f o C L ) V 2 DD f o = output freq. (MHz) C L = load capacitance (pf) (f o C L ) = sum of outputs V DD = supply voltage (V) Fig.4 Waveforms showing recovery time for MR; minimum CP 0, CP 1 and MR pulse widths. January

6 Fig.5 Waveforms showing set-up times for CP 0 to CP 1 and CP 1 to CP 0, and propagation delays. January

7 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be... January Fig.6 Timing diagram. Philips Semiconductors

DATA SHEET. HEF4022B MSI 4-stage divide-by-8 Johnson counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4022B MSI 4-stage divide-by-8 Johnson counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,