DesignCon 2008 EDA365. Modeling a Phase Interpolator as a Delta-Sigma Converter. Andy Martwick

Transcription

1 DesignCon 28 Modeling a Phase Interpolator as a Delta-Sigma Converter Andy Martwick andy.martwick@intel.com

2 Abstract This paper provides a model and analysis of the frequency response and key characteristics of a phase interpolation type of a clock / data recovery circuit. By considering the circuit as a sigma delta conversion that with under sampling, linear system analysis is straightforward. The requirements of tracking the large low frequency phase jitter components of spread spectrum clocking (SSC) are detailed. The effects of delay in the loop are modeled, and the conditions for stable operation are given. A filter design is proposed that tracks SSC. Author Biography Andy Martwick is a jitter expert at Intel Corporation. He previously chaired the PCI express jitter work group during the early development of the specification. He is currently working on the USB 3 (5 Gb/s serial link), focusing is on reliability, errors, error correcting codes and equalization. Previous experience is in PCI express architecture, ESD, RFI and EMI. He has a B.S. in physics from Excelsior University and is a graduate student at Portland State University.

3 Introduction In today s high speed serial links the clock is extracted from the data by the Clock Recovery Circuit (CRC). This recovered clock is used to strobe the data and operates some of the logic in the receiver. The CRC is part of the larger Clock and Data Recovery circuit (CDR), also called the Data Recovery Circuit (DRC). Some functions of the CRC are to synthesize a clock in the absence of data transitions, multiply or divide the clock to different rates, generate multiple clock phases, and track the incoming jitter in a well controlled manner. The block diagram for the CDR is shown in figure. Figure : Clock and Data Recovery Circuit Traditionally I/O architectures used a Phase Locked Loop (PLL) to perform the clock recovery. The PLL has a proportional response to changes in the input phase of the data and tracks input data jitter in a well controlled manner. However, the PLL tends to be sensitive to noise, large in area and high in power requirements. With PCI Express it is not uncommon to see as many as 4 high speed serial links on a single device, prohibiting the practical use of the PLL for each link s CDR due to power and area constraints. The first instance of the modern Phase Interpolator (PI) based CDR was published by Lee, Donnelly, et al of Rambus in 994 [] with an application to memory interfaces. The reasons cited as motivation for the new circuit was the noise immunity, lower voltage operation and fast lock time of the Phase Interpolator vs. the PLL. Simplistically, the PLL was replaced with two Delay Locked Loops (DLL) and a digitally controlled MUX. This enabled the DLL to track the input phase over arbitrarily large phase changes as long as the frequency difference was bounded and did not exceed the circuit s maximum slew rate. In early 997 the first usage of the term Phase Interpolation (PI) applied to a CDR was published by Sidiropoulos and Horowitz [2], also of Rambus. In 998 Dally and Poulton included a description of the PLL and PI CDR in their textbook [3].

4 This paper covers the modeling of the bang-bang style phase detector in the phase interpolator. In particular, it sets out the challenges of tracking spread spectrum clocks (SSC) that have a.5% frequency difference that creates a relatively large low frequency phase jitter component. It covers the basic PI operation, the key performance requirements, and presents an implementation of the loop filter. The relevance to the serial specification is then discussed. Units of Phase Phase is expressed in units of radians. When dealing with clocks in high speed serial links the phase is measured relative to the bit time, also called a unit interval (UI). The sampling period of the system, T, is equivalent to a unit interval, UI. Phase is a variable that is at t= and increments at the rate n*t, where n is a transition. This is shown in figure 2, assuming a 4 ps UI. Absolute Phase, s, (radians) 9.6ns (48 π) 8.ns (4 π) 6.4ns (32 π) 4.8ns (24 π) 3.2ns (6 π).6ns (8 π) t n nt ideal t ns ns.6ns 3.2ns 4.8ns 6.4ns 8.ns Figure 2: Absolute Phase Jitter and the Ideal Clock The phase of two clocks can be subtracted to get the relative phase between them. Most often we are concerned with the difference between the phase of the data and the clock used to sample the data. This clock is recovered from the data stream and is called the recovered clock. The phase jitter between the phase of the recovered clock and the phase of the data is obtained by subtracting their phase. This is shown in figure ns

5 4 ps (2 π) F n Phase Jitter, s, (radians) 2 ps (π) ps ( π) -2 ps ( π) -4 ps ( 2 π) ns.6ns 3.2ns 4.8ns 6.4ns 8.ns nt Figure 3: Phase Jitter after Clock Recovery Throughout this paper phase is represented in units of time. To change from radians to time multiply the radians by the UI, and change from time to radians divide the time by the UI. The advantage of using time as the phase representation is any displacements in phase are independent of any particular clock period. This allows freedom to discuss and model amplitudes of phase that are independent of the bit rate of the system. Depending on the receiver architecture, there may be a static phase offset of π radians or equivalently of UI / 2 seconds between the clocks and the data that lines the sampling clock up with the center of the data bit. This offset has no effect on the models presented. This static offset is shown in figure 4. 2π 9.6ns π Figure 4: Static Phase Offset in Radians

6 Phase Interpolator Model Data Phase Detector Finite State Machine (FSM) Phase Adjust Recovered Clock Reference Clock Figure 5: Phase Interpolator Block Diagram A phase interpolator block diagram is shown in figure 5. The phase detector compares the phase of the recovered clock to the phase of the data. It generates early and late indicators to the Finite State Machine (FSM). The FSM is the digital logic that forms the control loop of the phase interpolator. The output of the FSM adjusts the phase of the reference clock to try to match the phase of the data. The frequency of the reference clock is bounded with respect to the data clock by the serial I/O specification, so the rate of the phase adjustment is designed to be sufficient to overcome frequency differences between the data and the reference clock. Since frequency is the first derivative of the phase, the maximum rate of change in phase of the phase interpolator sets the maximum frequency offset that can be tracked. The phase adjuster is accomplished by cascaded delay locked loops (DLL), the circuit details are described elsewhere [4]. What is important for modeling purposes is that there is a number provided to the phase adjuster that ranges between and N, where N is one UI divided by the step size. N is the amount of phase steps that can be taken by the phase interpolator. The maximum rate of change that can be generated by the FSM is a function of the step size and the rate of the indicators coming into the FSM, along with the gain of the FSM. The smallest possible step size is limited by the circuit tolerances of the particular process. Manufacturing tolerances in clock phase distribution, clock jitter due to noise and crosstalk, and other circuit errors typically are in the 5 ps range. This sets a lower bound on the minimum practical step size. Large step sizes will track greater frequency deltas, since the phase will move farther with each adjustment. Since the phase detector is of the bang-bang type, the FSM will dither around the phase location by at least one step. This dither is an error in the sampling location and is a consideration when choosing the maximum allowed step size. Smaller step sizes give smaller dither errors but cannot track larger frequency offsets. The loop delay is the amount of time it takes from when the input to the phase adjuster changes to when the recovered clock actually moves. Loop delay introduces a pole into

7 the phase interpolator loop. It will be shown that the loop delay is a key parameter that limits the tracking performance of the PI. The rate of the indicators coming into the FSM is limited by the number of transitions in the data. Since this is a random quantity the FSM is not a regularly sampled system if it operates on every possible transition and cannot be easily modeled. For 8bb encoding the worst case pattern has an edge at least once every 5 UI and worst case edge density of 3% [5]. By under-sampling the phase by at least 5 UI linear systems analysis can be applied. A summary of the critical PI modeling parameters in terms of the bit time (UI), is given in table. Table : Key PI parameters PARAMETER VALUE Description Step Size UI / N (sec) The step size is the size of the UI (ps) divided by the number of steps. It is limited at a minimum by the manufacturing tolerance and at a maximum by dither Loop Delay UI to k*ui (sec) The delay of k UIs is how long it takes the loop to update and move the reference clock Input Data Phase Xn The phase representation of the input data. Not every UI provides a phase indicator. Recovered Clock Yn The output phase of the recovered clock Finite State Machine (FSM) H(w) The FSM is the heart of the loop filter. It has a transfer function that can be approximated as a linear function of frequency Phase Adjustment P P is the phase offset between the data and the reference clock when the reference clock is taken to have the phase of. P ranges from to N, corresponding to a rotation in phase of to 2pi. Undersampling m The number of UI between samples. The sampling frequency is then f s = m* UI Early and Late Indicators The first step in recovering the clock is to extract the phase from the input data stream relative to the reference clock. This is done by sampling the data at the edge and in the middle with the current recovered clock. The current recovered clock is the reference clock plus the phase from the phase interpolator. The result of this comparison is the data phase is detected to be either early or late relative to the sampling clock. This is accomplished by sampling the data in the presumed middle of the bit and at the transition. This operation is shown in fig 6 and summarized in table 2.

8 D E D2 E2 D3 Figure 6: Sampling Edges and Data Table 2: Early and Late Indicators D E D2 Meaning No Transition, do nothing Sampling Early, move phase later Phase is off by ½ bit time Sampled Late, move the phase earlier Sampled Late, move the phase earlier Phase is off by ½ bit time Sampling Early, move phase later No Transition, do nothing Before discussing the finite state machine (FSM) we first establish the requirements for the FSM in terms of Spread Spectrum Clock (SSC) tracking. Besides the obvious centering of the bit, tracking spread spectrum clocks is a major challenge faced by the FSM tracking loop and is introduced next.

9 Spread Spectrum Clocks The slew rate requirement for spread spectrum clocks (SSC) can be found by approximating the phase of a SSC as a sinusoidal function. In actuality the phase of the SSC is parabolas alternating in sign, but the sinusoidal approximation is accurate enough for modeling purposes. SSC starts as a.5% downspread of the main system clock modulated at a constant rate of change of the UI. The average UI is f f f avg = 2 and is the frequency that will be measured by the clock recovery function as the average on an absolute scale. The peak phase over the average phase can be calculated by integrating the instantaneous frequency and subtracting out the average for all the times the UI is over (or under) the average UI [6]. This amounts to calculating the shaded area in figure 7. There are other spread spectrum profiles that are shaped differently, however the phase jitter is still approximated as a sinusoid. Figure 7: SSC Frequency Modulation The phase is the integral of the frequency. The phase difference is given by the shaded area shown in figure 6. This is t t φ = 2*.5 f dt t, where gives t is the time it takes for the phase to move from the average to the maximum. This 2 t f t 8us t φ =.5 =, φ max = 4 ns f,

10 in units of radians. To get to the time representation just multiply by the UI, or 4 ns. The maximum slew rate of SSC between two clock domains is approximately d dt 9 ( x (2* pi *33,* t) ) 4 max =.83 Practical limitations bound the maximum slew rate of the phase interpolator. Assuming that one step can be made every m UI, the maximum rate of change would be () d stepsize φ =. dt m* UI max With a 5 ps step size, an m value of 5 for the maximum 8bb data transition, a UI value of 2 ps then the maximum slew rate of the CDR is 5e 2 =.5 s / s 5* 2e 2 sec sec and is not sufficient to track SSC. This is shown in figure 8. Phase (s) x -8 PI Tracking of Phase Input Phase PI Tracking time (s) x -5 Figure 8: Tracking 8ns SSC with 5 ps step size, m=5

11 With a 2 ps UI, m=5 and solving equation () gives the minimum step size of 8.3 ps. This is shown figure 9. 5 x -8 PI Tracking of Phase 4 Input Phase PI Tracking Phase (s) time (s) x -5 Figure 9: Minimum step size tracking of SSC While at a step size of 8.2 ps the slew rate can no longer be completely tracked during the maximum. This small error cannot be seen on the tracking plot, but shows up in the error plot, shown in figure. Phase (s).5 x - Phase Error between input and PI output time (s) x -4 Figure : Error in steps between input SSC phase and output of PI

12 As will be shown later, under sampling of more than 5 may be required due to the loop delay of the circuit. The larger the under sampling, the larger the step size required to be able to track SSC unless some form of gain is introduced into the control loop. For a 2 ps UI, the graph in figure provides the minimum step size required to track SSC as a function of the undersampling integer, m. 2.2 x - min step size vs m 2 min step size required m Figure : Minimum step size required to track SSC vs undersampling integer m Although the larger step size does a better job of tracking SSC, it also causes a larger dither component that closes the eye. The amount of acceptable dithering at steady state sets the upper limit of the step size. Assuming m=, the minimum step size is approximately 7. The dither with a 5 ps step size closes the eye by 34 ps, as shown in figure 2a, compared to a step size of 5 ps and an eye closure of ps as shown in figure 2b. Phase (s) x - PI Tracking of Phase Input Phase PI Tracking time (s) x -5

13 Figure 2 a) Dither with a step of 7 ps x -2 PI Tracking of Phase 5 4 Input Phase PI Tracking Phase (s) time (s) x -5 Figure 3 a) Dither with a step of 5 ps The desire of good response at low frequencies and attenuation of dither at high frequencies can be managed with the proper filter design. Proper filter design can add gain to the low frequencies and attenuation at the higher frequencies, enabling small step sizes to track SSC. This is simpler than other mechanisms that achieve this by adding another control loop, adding variable gain or an integral filter [7]. Spread Spectrum Breakthrough Jitter The under-sampling integer, m in equation (), sets the Nyquist frequency of the tracking loop. Our model assumes that the output of the phase interpolator is updated every m th UI. During the time of maximum rate of change of the SSC input, the difference in UI accumulates for the m cycles while the PI is not updating the output. This accumulation is a source of tracking error during the maximum slew of the SSC phase. For example, at the maximum rate of change SSC can cause a phase difference of. * UI * m between updates. In the case of a 2 ps UI and an m value of, the phase will change by ps between updates. This will be positive for positive changes in slope, and negative for negative changes in slope giving an eye closure of 2 ps due simply to the lack of updates.

14 This jitter is called the breakthrough jitter. It may be compensated by various filter techniques that operate between updates; this is beyond the scope of this paper. An example of breakthrough jitter with is shown in figure 3. x -2 Phase Error between input and PI output Phase (s) time (s) x -5 Figure 4: Breakthrough jitter with m=, step = 5ps, 2 ps UI Averaging Random Jitter The bang-bang phase interpolator does not provide magnitude information making the response of the loop slow. However, in the presence of sufficient random jitter the average of many samples will give an indication of magnitude as proposed in [8]. This is seen in figure 5.

15 Figure 5: Sampling the tail of a random distribution If the sample location is far to the right of the distribution the value returned over m samples will be m. If the sample location was to the far left of the distribution the average returned over a large enough sample will be +m. If the sample location is at the center of the distribution the value returned would be. Sampling a Gaussian distribution at location sigma over m samples gives the result of m times the difference in the probability of left and right. The probability of left and right is given by the cumulative density function CDF(sigma), m * (CDF(-k) CDF(k)) where k is the location of the current sampling clock in terms of the sigma of the Rj distribution. This averaging operation is n m () + E = k n= m m I n m Where E m is the integer variable that represents the error between the clock and data, n is the bit rate, m is the decimation, k is the actual number of edges that occurred, and I n is the indicator of early,+, and late, -. As previously mentioned, E is only an integer variable in the region of sufficient random jitter. For 8bb an edge is guaranteed once every 5 UI, and as often as every UI. In order for the Rj to provide a magnitude indication the step size of the PI must be small relative to the sigma value of the Rj PDF. However, as the data rate for serial interfaces rises, the Rj component decreasing. For example, USB3. is considering a Rj component

16 of only 3 ps. The total useable distribution would then be approximately 4*3 = +- 2 ps. With a 5 ps step size, the useable magnitude would be 2 or 3 at the most. In addition, the Rj component is dominated by the ISI distribution of the media. This means the PI can be fooled by a particular data pattern. In the extreme case, a particular data pattern would always cause the PI to create a bit error. This type of averaging may be an optimization but is not necessarily required to properly track SSC. The models that follow do not require averaging. Finite State Machine: Transfer Functions Loop Delay The block diagram of the CDR is shown in figure 6. D S + S H + R - e sd Figure 6: Block Diagram of the Clock and Data Recovery C + - Ec The Nyquist frequency of the system is a function of the under sampling variable, m, (2) fn =. 2 mt Referring to figure 6, the data phase D is compared to a delayed version of the recovered clock phase, R. Advance increments the accumulator S and retard decrements the accumulator S as appropriate. Filtering and gain is provided by the transfer function H, as appropriate. This phase is then added to the reference clock C to generate the recovered clock, R. Since the phase jitter is always relative to the reference clock C, C can be chosen to be. The eye closure is shown as Ec and is the mismatch between the recovered clock and the data. Ideally Ec=, meaning that the clock is sampling the data in the center of the bit. This control loop operates at the Nyquist frequency given by equation (2), where m is the sub sampling integer. The loop delay in this circuit is d and is typically in the range of several UI. It is the amount of time it takes for the phase adjuster to change the setting of the current phase.

17 From the block diagram, the s domain response of D-C to R is: D C R = + H e s d When D = C the eye closure is. This means that the recovered clock phase exactly matches the data phase and the eye opening is at a maximum. As previously discussed, we are interested in the response to the phase error between C and D. If the loop filter, H, is then the total response is completely determined by the delay in the loop. This is where H Ec H Ec Y = = D C + e sd is the total transfer function. This can also be written H Ec =, sd sd sd e e + e and taking the frequency response, H Ec = 2cos( π f d) where f ranges from to Nyquist. With the Nyquist frequency normalized to.5, H is plotted as a function of f d in figure 7. Ec 8 Magnitude of H frequency * delay Figure 7: H vs Loop Delay * Nyquist In figure 7, f=.5 represents the delay equal to the Nyquist period. This is the case when d = 2 m T. At f*d =.25, the loop gain is less than one and the system is stable, this

18 corresponds to d = m T. As fd approaches the pole at.5, the system will be unstable regardless of the input. Once the minimum delay of the circuit is known, the maximum stable sampling rate is determined. The value of m required to meet the stability requirement is d m min = T For example, if the loop delay is UI, m should be set to or greater. The delay limits the maximum frequency at which phase interpolator can operate. This is generally not a problem since the phase interpolator is not expected to track very high frequency jitter. Figure 8 show the tracking error vs the loop delay for two different values. Phase (s) Phase (s) 5 Phase Error between input and PI output, m=, delay= time (s) x -5 Phase Error between input and PI output, m=, delay= time (s) x -5 Figure 8: Tracking error with different loop delay. The first plot shows stable operation, the second plot shows what happens when the pole from the delay is dominant. Errors are given in steps. As discussed previously, larger values of m lower the ability of the loop to track SSC and the stability requirement conflicts with the SSC tracking requirement. However, large values of m are required for stability. This requirement can be managed by adding loop gain to the tracking loop. Adding a proper loop filter to H can also manage and contain the loop delay, this is shown next. Filtering The PI block diagram is redrawn in figure 9 showing the Z domain model. The reference clock C is no longer shown since we are free to pick the phase of C as, transferring any jitter on C to D. Just like a sigma delta converter, the output R is adjusted until it matches the input signal D by summing a sign indicator and not using a magnitude indicator. In a delta sigma ADC converter this adjustment happens quickly relative to the sample rate of the ADC itself, and once a stable value is found (a dither of or less) then

19 the output value is made available at the lower rate. For the PI, the output directly controls the phase select, so the PI is always subject to dither. + Ec D + - S + H R - Z - Figure 9: Z domain PI model Some designs add an integral filter to compensate for the SSC phase jitter in an attempt to increase the low frequency tracking [7]. An alternative presented in figure 9 is to use a simple digital filter, H. Then gain can be added and the response can be shaped as desired by appropriate choice of filters coefficients. The total transfer function with the loop filter H in the z domain is R H D z + H z = d When H is implemented as a low pass IIR filter, the Z domain transfer function of H is k a H = + b z k selects the gain of the loop, while the corner frequency of H is set by the choice of the coefficients a and b as fc=5e6 x=exp(-2*pi*td*fc) a=-x b=x k=.8; With step=5ps, m =5, UI=2 ps, k =.8, fc=5e6, and the delay fd =.25, the transfer function of H is shown in figure 6. The nyquist frequency is given by equation 2 as 5 MHz.

20 6 Frequency Response 4 2 Magnitude 2 log(vo/vi) The eye closure, Ec, is given by Ec = D R Frequency Figure 2: Transfer function of D to R The transfer function of input jitter to eye closure with step=5ps, m = 5, fc = 5 Mhz, UI=2 ps, k =.8, and the delay fd =.25, is shown in figure 7. The Matlab equation implementing this transfer function is H=gain*a./(-b*z.^-); R=H./(-z.^-+H.*z.^.25); Ec=-R; It can be seen in these equations that having H as a low pass counteracts the effects of the delay. This allows the circuit delay can increase and the overall system will remain stable provided H is a low pass. Peaking occurs in the total transfer function as the corner frequency of H gets small. This is shown in figure 22 for H=5 MHz. This type of behavior is not necessarily obvious and highlights the importance of solving the total system transfer function to avoid cases of peaking.

21 2 Transfer function Ec to D, m=5, UI=2ps, fd=.25, fc=5 mhz Frequency Figure 2: Transfer function of D to Eye Closure, EC Transfer function Ec to D, m=5, UI=2ps, fd=.25, fc=5 mhz Frequency Figure 22: Peaking of H as corner frequency is lowered

22 Performance With m=5, step = 5ps, UI = 2ps, fc=5mhz, and k=.8, the tracking performance is +- ps as shown in figure 23. x - Phase Error between input and PI output Phase (s) time (s) x -5 Figure 23: Tracking error with 8 ns of SSC The entire tracking loop is implemented in just a few lines of Matlab. for n=start_n:n if mod(n,decimate) == % update every mth UI S=S+sign(d(n)-r(n-delay)); r(n)= (b*r(n-decimate) + k*a*s); % apply the IIR filter else r(n)=r(n-); % otherwise just hold the value end end Notes: decimate is the same as the m value. The sample UI is therefore m*ui. S is the running sum of the advance and retard indicators. R(n) is the recovered clock, D(n) is the input phase jitter record. Sign (D(n)-R(n)) generates an early or late indicator.

23 The lock time to an 8ns step is 8 us: x -8 PI Tracking of Phase Input Phase PI Tracking Phase (s) time (s) x -6 The tracking to random jitter, sigma = 5 ps, is Phase (s) 3 x - PI Tracking of Phase Input Phase PI Tracking time (s) x -4 An example of tracking performance: Phase (s) x -8 PI Tracking of Phase Input Phase PI Tracking time (s) x -5

24 Serial Specifications and the CDR High speed serial specifications, such as PCI Express, USB3. and SATA, indirectly specify the minimum performance required by the CDR. They do this by specifying the filter function that is used to measure the jitter from the transmitter and receiver. The filter function is a high pass filter, rejecting any low frequency components and passing high frequency jitter. This is shown in the figure 24. Tx + Channel Jitter Filter from Specification Figure 24: Measurement Schematic Jitter Measurement It is implied that the CDR must operate as well as the filter function at tracking jitter. In fact, the CDR total transfer function, figure 2, must be less than the jitter filter at all points in order for the performance of the phase interpolator to meet the specification requirement. In addition, we have seen the importance of the slew rate as a limiter to the PI tracking. It is now apparent that future serial specifications must include a maximum slew rate in order to bound the behavior of the phase interpolator type of CDR. Summary The details of the PI have been given, along with performance parameters that are critical to tracking SSC with a PI filter. Slew rate limitations have been given and the limits of step size relative to the sampling rate. The PI has been made linear by modeling it like a Sigma Delta ADC. Undersampling has been used to ensure a linear response, and transfer functions have been given for one instance of a first order filter. The importance of delay has been demonstrated and the delay transfer function has been given. The parameters for avoiding the pole caused by the delay have been given. One example of a filter has been given. Future work can look at optimizations in averaging, countering break through jitter, and filters of higher orders.

25 Acknowledgements: I would like to acknowledge Ron Swartz for providing his valuable feedback on this topic. References: [] Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark G. Johnson, and Tom Ishikawa, A 2.5 V CMOS Delay-Locked Loop for an 8 Mbit, 5 Megabytek DRAM, IEEE Journal of Solid State Circuits, VOL 29, No. 2, December 994, pp [2] S. Sidiropoulos and M. Horowitz, A semidigital dual delaylocked loop, IEEE J. Solid Sfate Circuits, vol. 32, pp , Nov [3] W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, 998. [4] Lee, M.-J.E.; Dally, W.J.; Greer, T.; Hiok-Tiaq Ng; Farjad-Rad, R.; Poulton, J.; Senthinathan, R.; Jitter transfer characteristics of delay-locked loops - theories and design techniques, Solid-State Circuits, IEEE Journal of Volume 38, Issue 4, April 23 Page(s):64-62 [5] A. X. Widmer, P. A. Franaszek, A DC-Balanced, Partitioned-Block, 8B/OB Transmission Code, IBM J. Res. Develop. Vol. 27, No. 5, September 983 [6] Li, M., Martwick, A., Talbot, G., Wilstrup, J., Transfer functions for the reference clock jitter in a serial link: theory and applications, Test Conference, 24. Proceedings. International, Oct , 24 Pages:58 67 [7] Ming-ta Hsieh; Sobelman, G.E.; Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications, Circuits and Systems, 25. ISCAS 25. IEEE International Symposium, May 25 Page(s): Vol. 5