Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out

Transcription

1 Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out Dimitris Bekiaris, Antonis Papanikolaou, Dimitrios Soudris, George Economakos and Kiamal Pekmestzi 1 1 Microprocessors and Digital Systems Lab, National Technical University of Athens , Zografou, Athens, Greece {mpekiaris, antonis, dsoudris, geconom, pekmes}@microlab.ntua.gr Abstract. The aggressive scaling of nanometer CMOS technology nodes and the integration of low-k dielectrics introduces novel reliability phenomena that progressively degrade the electrical characteristics of copper interconnects. These effects impact the performance of designs gradually rather than abruptly, leading to timing violations in several timing-critical paths and thus shortening the system s lifetime. Therefore, the need for design methodologies predicting the impact of such phenomena is emerging. This paper presents a case study for a dominating interconnect reliability effect, Electro-migration, based on an MP- SoC platform with two LEON3 SPARC processors as kernels. The proposed flow studies the impact of Electro-migration on the timing-critical paths of the design and estimates the system s lifetime due to this effect. The presented case study may be used as a guide to estimate the impact of Electro-migration in the performance of complex, MP-SOC designs, based on a proposed analysis framework, which can be extended to the study of relevant interconnect reliability phenomena. Keywords: Reliability, Electro-migration, Performance 1 Introduction As CMOS technology scales-down to the nanometer regime, the continuous shrinking of dimensions in both transistors and interconnects reveals novel emerging issues regarding the reliability of modern integrated circuits. Also, the new low-k dielectric materials, which are widely used to reduce the inter-metal capacitance, impose additional reliability wear-out mechanisms in adjacent wires of the same metal layer. However, technology scaling will not significantly reduce the operating voltage, even though the dimensions of devices and wires will keep on shrinking, according to the ITRS roadmap [1]. Hence, the total amount of current passing through the wires does not change significantly. Consequently, the current density of wires increases with scaling, as well as the electrical field between interconnects of the same layer. Hence, Back-End-of-Line (BEOL) reliability phenomena such as Electro-Migration (EM), Stress-Migration (SM) and Time-Dependent Dielectric Breakdown (TDDB) become important.

2 Regarding EM, scaling reduces both the width and the thickness of wires and therefore increases current density, leading to larger transport of Cu atoms and to formation of voids that increase the wire s resistance. The SM effect exists due to the abrupt changes of temperature that lead to tensile stress of interconnects, while TDDB rises with the shrinking of spacing between wires of the same metal layer, as electrical fields become more intense and form leakage conductive paths that gradually damage the inter-metal dielectric in nanoscale CMOS process technologies. The influence of the aforementioned interconnect reliability phenomena is much stronger than simply the decay of electrical and structural characteristics on separate wires. Their impact may affect the timing of the design and therefore the performance of the system in which the specific design is integrated. For example, a possible resistance rise of 20% due to EM could impose a delay overhead that could violate the desired timing constraint. In such cases, the system cannot function according to the initial performance specifications. Such a timing failure due to EM can shorten the system s desired lifetime. This class of failures in interconnects is rather different from those that occur the manufacturing process of ICs, as they progressively impact the system s lifetime and can be largely predicted before the design is fabricated. The prediction of timing failures due to interconnect reliability effects forms the motivating aspect of the presented work, which examines the impact of EM on the performance of an MP-SoC system, based on two LEON3 SPARC processors. For this case study, EM was selected among the aforementioned reliability effects, because it has the greater impact on delay, compared to SM and TDDB. This impact is estimated by the presented interconnect reliability framework, which computes the system s delay degradation due to the wire resistance increase on the design s most timing-critical paths. Our flow extracts the wires of interconnects belonging on these paths and computes the resistance change of the wires affected by EM, as well as the years required for this change to occur. The new resistances are computed considering a certain system lifetime, assumed to be ten years in these experiments. The delay impact of EM on the system s performance is evaluated by performing a final timing analysis on the design, by annotating the parasitic file with the increased wire resistances. The outline of the paper starts presenting the related work presented recently in the literature and continues with our EM model. The next section, namely Section 4, presents the proposed reliability analysis framework, while Section 5 demonstrates the experimental results from the application of this framework to an MP-SoC platform. Finally, a discussion on the results and also hints for future work conclude the paper. 2 Related work The majority of recent works presented in the literature on the field of EM estimation and analysis can be separated into two classes, depending on the level of design abstraction on which they target. In perspective, the first class of methodologies and tools presented estimate the impact of EM on small components based on EM physical models. This approach is depicted on tools like those presented in [2], [3]

3 and [4]. These are tools based on analog simulation and they perform an EM characterization of components at a transistor-level granularity. Based on the same level of design abstraction, the works presented in [5] and [6] estimate the impact of EM on the wire tree interconnection structures of relatively small layouts and find the mostly affected wires. On the other hand, system-level approaches are presented in [7], [8] and [9] are based on pre-characterized coarse-grained components, but their models are rather abstract and they do not accurately estimate the system s performance drift over time. A system-level approach based on more accurate models is addressed in [10], where the developed tool performs a characterization of small components, based on analog simulation, and back-annotates them to an hierarchical design for the full-chip EM analysis. However, it focuses on hard breakdown failures on wires. On the contrary, the tool flow presented in [11] and [12] focuses on the impact of EM on the system s performance over time, by considering the design s critical path. In this work, we make a step forward toward the exploration of paths that are initially sub-critical, but which could become critical, considering the progressive impact of EM on the resistance of affected wires in such paths. Thus, we demonstrate an EM analysis framework, based on a generic interconnect reliability estimation flow, and we select the most critical register-to-register paths of a LEON3-based MP-SoC layout. The proposed EM tool chain extracts the wires of interconnects in the selected paths and computes the new resistances for each separate wire. The updated resistance values are annotated to the layout s parasitics, which are driven to the final timing analysis, step, in order to evaluate the EM impact on the nets of the specific paths. The EM model based on which the resistance change computations are performed is given in the next section, followed by the proposed reliability analysis framework. 3 The Electro-migration Modeling Electro-migration (EM) is one of the major interconnect reliability wear-out mechanisms in Cu interconnects, as it leads to an abrupt resistance step of wires that are longer than a specific length and progressively to a delay shifting that could be fatal for the system s lifetime, if the wires are on a timing critical path. This resistance step occurs progressively, after a certain period of the system s functionality, in wires exceeding a critical length, known as Blech Length. In EM modeling theory, the Blech Length is determined as the length threshold below which EM does not affect wires and it is strongly depends on the current density of the specific wire. The wires at which EM occurs are those with length L > ((jl) critical /j op ), where (jl) critical is assumed to be equal to 3700A/cm, according to [12], while j op is the operating current density of the wire. Hence, in the wires longer than the Blech Length, the mass transport of free electrons stresses the atoms of Cu and leads to the formation of voids to the wire s cathode, while it creates void extrusions to the anode. The void nucleation disrupts the wire s electrical conductivity and it is responsible for the wire resistance step, as it forces current to come through the wire s barrier, hence increasing its resistance significantly.

4 An example illustrating the EM phenomenon is shown in Fig. 1, where a copper wire of width W, length L and thickness H is shown, along with its barrier, of thickness t b. Figure 1. The structure of a copper wire, showing a void formation due to EM. As the current comes through the wire, the length of the void space gradually increases, until it reaches a critical value, L void, at which the atoms of copper in this region are depleted and the wire s resistance shows an abrupt step, R step, given by the equation: R step = ((ρ b /( t b *W+ t b *2H))-(ρ Cu /H*W))*L void (1) In Eq. 1, ρ b and ρ Cu stand for the resistivity of the barrier and the Cu respectively. The time required for R step to occur, namely t 50,op, is computed in years and depends on the operating current density and temperature, as follows: t 50,op = t 50,stress * (j stress /j op ) n * exp(e a /K((1/T op ) (1/T stress ))) (2) In Eq. 2, R slope,stress, j stress and T stress are the slope, the current density and the temperature under stress conditions, while j op and T op are the operating density and temperature respectively. Also, E a is the activation energy, K is the Boltzmann constant and n is the current density exponent. Once the wire s resistance rises from its initial value to R step, it increases with a slope per year, depending on current density and temperature, defined as: R slope,op = R slope,stress * (j op /j stress ) * exp(e a /K((1/T stress ) (1/T op ))) (3) The following figure illustrates the resistance behavior of a wire that suffers from EM over time and depicts the metrics defined in the three above equations. The presented EM model is the basis for our estimation framework, given in the next section. Figure 2. Resistance change of a copper wire over time due to EM impact.

5 4 The proposed interconnect reliability analysis framework In this paper, our reliability framework focuses on EM, because this is the most prominent phenomenon that affects the electrical characteristics of interconnects and impact the system s performance over time significantly. However, its structure is generic, so that relevant interconnect reliability effects can be integrated into the same tool flow. The generic interconnect reliability framework is shown in Fig. 3. The flow of Fig. 3 takes as input the layout of a design, implemented with a standardcell CMOS technology library and it is the platform on which the proposed methodology is evaluated. Hence, the tool flow reads the layout database and performs a static timing analysis on the design, to extract its critical path. Figure 3. The proposed generic interconnect reliability framework. The nets belonging to this path are considered as the key interconnects, as long as even a relatively small impact of the studied reliability effect on the electrical characteristics of their wires could violate the required performance constraints and shorten the system s lifetime. The wires of these nets are then extracted through the layout database and they are driven to the next step, which computes the impact of the studied reliability effect on the electrical characteristics of these wires. Finally, the updated electrical characteristics of the selected wires are annotated to the final timing

6 analysis step, in which we evaluate the impact of the reliability effect on the system s critical path delay. In this paper, this generic framework focuses on the analysis of EM and introduces a detailed methodology that estimates the system s delay degradation, because of the gradual resistance increment in the wires of the critical path. 4.1 The proposed EM flow Our system-level EM analysis framework is based on the generic reliability flow of Fig. 3. Thus, its input is an again an IC layout, on which we initially perform static timing analysis to find the design s critical path. The nets of the design included in this path are the key interconnects for the EM analysis. Then, the wires of these nets are extracted, by reading the layout database. Their physical dimensions are used for the Blech Length and the resistance change computations of Section 3, based on the current density estimation for each net. For the wires of each net exceeding the Blech Length, our tool flow computes the new resistances due to EM and updates the Standard Parasitic Exchange Format (SPEF) file with the new resistance values. The updated SPEF file is used as input to the final static timing analysis step. As far as there are wires longer than the Blech Length for a specific net, the increased resistances may incur a significant delay overhead in the design s critical path. Hence, the delay overhead shown in the produced timing report demonstrates the impact of EM on the system s performance. Also, as it is shown in the forthcoming section, the timing of sub-critical paths that are close to the longest one may also be affected. The analytic description of the EM flow steps is given below. Figure 4. The proposed interconnect reliability analysis flow for EM. Step 1 - Timing analysis and layout extraction: We perform timing analysis on the post-layout netlist of the design, in order to find the critical register-to-register path. The timing report is derived from Synopsys Design Compiler [14] timing analysis engine and it includes the delay of each standard cell and the nets connecting the standard-cells. These nets are considered as the key interconnect and their wires will be extracted, to perform the EM analysis for the longest path.

7 Therefore, we import the layout database in Cadence SoC Encounter [15], to extract the physical dimensions of wires corresponding to the selected, key nets. The extraction of wire length, width and thickness is achieved by using the Encounter Database Access command set. These dimensions will be used for the EM impact on the wire resistance. Also, we extract the total net capacitance, required for the current density estimation. Step 2 - Current density estimation: The current density of each net connecting two standard cells in the critical path is estimated through the standard-cell library information file (e.g. the.lib file), which keeps the timing information for each cell, depending on its output load capacitance. Hence, we read the look-up table of output load capacitances for the standard-cell that drives the specific net, to find the index of the capacitance which is greater or equal with the net s capacitance. This index is used to read the rise and fall time that corresponds to this load capacitance. The rise and fall times are used to compute the rise and fall current respectively, through the equation I = C net *V dd /transition_time, where C net is the total net capacitance, V dd is the operating voltage, defined in the standard-cell library, and transition_time represents either the rise or the fall time, computed as defined previously. However, wires are imposed to AC current stress during the circuit s operation. Therefore, we decided to determine the wire s current as an average value, defined as I ave = I rise - I fall. Then, the average current density, j ave, of each the net s wire is given by the equation j ave = I ave /A, where A is the wire s cross-section area. Based on j ave, we determine the Blech Length of the net s wires and then, we compute the resistance step due to EM, as well as the year required for this step to occur. Step 3 - Blech length and resistance change calculation: In our model, the Blech Length of a net s wire is computed by the expression {jl critical /j ave }, where jl critical is assumed to be 3700A/cm, while j ave is the net s operating average current density. For the wires exceeding Blech Length, our EM model computes R step, t 50 and R slope, according to Eq. 1, 2 and 3 of Section 3, after computing j ave. The above three steps are implemented by a Tcl script, which runs in SoC Encounter environment and uses the Encounter DB Access commands for the geometrical extraction of wires. The output of the script is a report dumped in an ASCII file, including the number of wires of each net above the Blech Length, as well as R step, R slope and t 50. Step 4 Parasitic resistance annotation and final timing analysis: This report is used for the computation of the new wire resistances due to EM and for the update of the layout s parasitics with the new resistances. This is performed through a Perl script that reads the nets from the text report, along with R step, R slope and t 50 for each wire of the specific net and computes the new wire resistance, considering a desired system lifetime, t sys_lifetime, of 10 years, as follows: R em = R initial + R jumping + R slope * (t sys_lifetime - t 50 ) (4) In the above equation, R initial is the initial resistance that is likely to be updated with the new one, R em. After computing R em, for each net s wire, our script finds the specific net in the SPEF file and replaces the resistance of the proper net segment (e.g. wire) with the new value. The SPEF file produced is driven to Design Compiler for the final static timing analysis. The new delay of the timing report and the reduction

8 on the setup timing slack evaluate the influence of EM on the design s longest path and therefore, on the system s performance over time. In the following section, we present the application of our EM framework to the case study of an MP-SoC system, based on two LEON3 processor cores. In this case study, we show that there can be more paths in the specific design, apart from the critical one, that may violate the required performance constraints, due to EM. 5 Application of the EM framework to a LEON3-based MP-SoC 5.1 The LEON3-based MP-SoC platform The presented EM analysis flow is applied to an MP-SoC system, based on two LEON3 SPARC processor cores. Each core is comprised of the integer unit, which implements the processor pipeline, and the cache controllers, while the caches have 2 sets of 8K bytes. The two processors are connected through the AMBA Advanced High-Performance Bus (AHB) controller and the peripherals are attached to the Advanced Peripheral Bus (APB). The system includes also an in-circuit Debug Support Unit (DSU), as well as an SDRAM controller. Regarding the peripherals, the design contains one Universal Asynchronous Receiver Transmitter (UART) controller attached to AHB and two connected to APB. The remaining peripherals are a general purpose timer, an interrupt controller and a parallel input/output interface. The AHB and APB peripherals, as well as the DSU, are configured as slaves, while the two LEON3 processors operate as masters. The design is implemented based on an RTL-to-GDSII flow. The design s VHDL code is automatically generated using the Aeroflex Gaisler Research [13] tools. The synthesis and place-and-route steps are performed in the Design Compiler and SoC Encounter tools respectively, based on the CMOS 90nm Synopsys SAED standardcell library, under nominal operating conditions. Also, the caches are mapped to the 32x128-bit and 8x128-bit SRAM cells of the library, while the 32x16-bit cells are used for the register files and the 32x64-bit cells for the four DSU memory blocks. For the post-layout static timing analysis, the post-layout Verilog netlist, derived from SoC Encounter, is back-annotated to Design Compiler, along with the parasitic information, included in the initial SPEF file. The minimum clock period at which design operates is 4.5ns and the setup timing slack of the critical path is 0.03ns. 5.2 Experimental results and discussion However, the complexity of the specific design and mainly, the small setup timing slack of the longest path motivated us to look also at sub-critical register-to-register paths, as a possible delay overhead due to EM could lead to timing violations. Thus, we extracted all the paths with slack less than 1ns, sorting them with descending order, depending on the slack.

9 Among those, the four more critical register-to-register paths, namely those with the less setup timing slack, were selected for the EM analysis. All the chosen paths start from a DSU register and they come through the first LEON3 processor, namely CPU0, before returning back again to another DSU flip-flop. It is noted that the corresponding paths from the DSU to the second LEON3 core, namely CPU1, are more relaxed, as their minimum slack starts from 0.95ns. This is due to the floorplan of the design, as DSU is placed closer to CPU1 rather than to CPU0 on the core area. For the experimental setup, the temperature used to derive the specific measurements was 373K (100 degrees), instead of the nominal value of 273K (25 degrees), as long as in MP-SoC based systems like our case study, temperature may be greater than the nominal value, when different tasks are executed in parallel by the two processors. In Table 1, we demonstrate the results from the EM analysis framework, for each of the selected four paths. The measurements include the timing slack before and after the EM impact annotation, considering the minimum clock period of 4.5ns as the timing constraint. The table also shows the additional delay, given in ns, that EM imposes on each path, along with the (%) percentage of delay degradation. Table 1. Delay degradation in the selected paths before and after the EM impact annotation. Examined Initial Delay Initial Slack Delay Delay path delay with EM Slack with EM overhead overhead (%) critical path path path path From Table 1, it is shown that in all the selected paths, the timing constraint is violated after the annotation of the updated resistances of wires affected by EM. Furthermore, the delay overhead because of EM is not the same at each selected path, as paths with larger initial setup slack show now larger delay degradation, compared to the critical one. Hence, the four paths are not affected in a uniform way, while their additional delay overhead is not correlated with their initial delay. This is due to the fact that the physical dimensions of wires in different paths are not the same, as well as the number of wires exceeding Blech Length. Also, there can be wires in sub-critical paths showing a larger resistance jump due to EM and hence, incurring larger delay, compared to those on the critical path. Such an effect is demonstrated in Table 1, where path2 shows the larger delay degradation, with a 24.64% percentage of additional delay overhead, and becomes now the critical path. The second more critical is path4 with a delay overhead of 19.75%, while the initially longest path becomes the third more critical, after the EM impact annotation. Thus, according to the results of Table 1, initially sub-critical paths should also be explored in complex designs, as they may become critical after a short period of time, because of the EM. This heterogeneous impact of EM is also depicted in Table 2, showing that the different number of wires longer than the Blech Length per path, along with the maximum R step, the minimum t 50 and the corresponding R slope, and it motivates the future extensions of this work, described in the concluding section.

10 Table 2. The EM framework results for the selected paths, where the similarity in R slope and t 50 is due to the fact that some parts of the four paths come through the same nets in the design. Examined Maximum Minimum t 50 R slope No. of wires over path R step (Ω) (years) (Ω/year) Blech Length critical path path path path Conclusion and hints for future work In this work, we presented an interconnect reliability framework that focuses on the impact of EM on the most timing-critical paths of a LEON3-based MP-SoC system and estimates the system s performance degradation over time, due to the increasing resistances on wires. This flow can be extended by estimating the EM influence on the paths of the two processors, considering the temperature variations across the design. Hence, a task migration scheme could be used, to distribute the temperature of each processor, thereby reducing the impact of EM on the respective timing paths. References 1. International Technology Roadmap for Semiconductors (ITRS), 2. R.Tu at al., Berkeley reliability tools-bert, IEEE TCAD, vol. 12, no.10, J. Hall et al., Spider-a cad system for modeling vlsi metallization patterns, IEEE TCAD, vol. 6, no. 6, April D. Frost et al., Reliant: a reliability analysis tool for vlsi interconnect, IEEE JSSC, T. Simunic et al., Optimization of reliability and power consumption in systems on chip, in Proceedings of PATMOS A.K et al., A simulation methodology for reliability analysis in multi-core socs, in Proceedings of the GLSVLSI J. Shin et al., A framework for architecture-level lifetime reliability modeling, in Proceedings of IEEE/IFIP DSN S. Alam et al., Circuit level reliability analysis of Cu interconnects, in Proc. ISQED S. Alam et al., Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations, Microelectronics Journal 38, X. Xuan et al., Aret for system level ic reliability simulation, in Proc. of the IRPS J. Guo et al., A Tool Flow for Predicting System Level Timing Failures due to Interconnect Reliability Degradation, in Proceedings of the GLSVLSI J. Guo et al., The Analysis of system level timing failures due to interconnect reliability degradation, IEEE Transactions on Device and Material Reliability, Aeroflex Gaisler Research, Synopsys Design Compiler manual, Cadence SoC Encounter manual,