Design of Datapath Controllers

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1 Design of Datapath Controllers Speaker: 俞子豪 Adviser: Prof. An-Yeu Wu ACCESS IC LAB

2 Outline vsequential Circuit Model vfinite State Machines vuseful Modeling Techniques P. 2

3 Model of Sequential Circuits v System outputs depend not only on current input v Depend on inputs v Depend on current state v Fundamental components v Combinational circuits v Memory elements Inputs Combinational Logic Outputs Current State Memory Elements Next State clock P. 3

4 Types of Memory Elements vflip-flop vlatch vregisters vothers vregister Files vcache vflash memory vrom vram P. 4

5 D-FF vs. D-Latch D v FF is edge sensitive (can be either positive or negative edge) v At trigger edge of clock, input transferred to output v Latch is level sensitive (can be either active-high or active-low) v When clock is active, input passes to output (transparent) v When clock is not active, output stays unchanged in out in D Q clk D Q FF clk Latch E out in clk out in clk out P. 5

6 FF Based, Edge Trigger Clocking v T d = delay of combinational logic v T cycle = cycle time of clock v Duty cycle does not matter v Timing requirements for T d v T dmax < T cycle T setup T cq v T dmin > T hold T cq Ł no setup time violation Ł no hold time violation clk FF Combinational Logic Td FF T cycle T cq T d T setup P. 6

7 Latch Based, Single Phase Clocking v Aka. Pulse Mode clocking v T cycle = cycle time of clock; T w = pulse width of clock v Timing requirements for T d v T dmax < T cycle T dq v T dmin > T w T dq Ł data latched correctly Ł no racing through next stage clk Latch Combinational Logic Td Latch T w T cycle T dq T d P. 7

8 v Flip-Flop Based Larger in area Comparison Larger clocking overhead (T setup, T cq ) + Design more robust Only have to worry about T dmax T dmin usually small, can be easily fixed by buffer + Pulse width does not matter v Latch Based Single Phase + Smaller area + Smaller clocking overhead ( only T dq ) Worry about both T dmax and T dmin Pulse width DOES matter (unfortunately, pulse width can vary on chip) P. 8

9 D Flip-Flop Flop with Positive-Edge Clock module flop (Q, D, C, S, R); output Q; // Flip-Flop Output input D; // Data Input input C; // Positive Edge Clock input E; // Clock Enable D C Q reg Q; // Register Type C) begin if (E) // Check Enable Q <= D; end endmodule D E C Q P. 9

10 D Flip-Flop Flop with Positive-Edge Clock module flop (Q, D, C, S, R); output Q; // Flip-Flop Output input D; // Data Input input C; // Positive Edge Clock input R; // Asynchronous Reset input S; // synchronous Set reg Q; // Register Type C or negedge R) begin if (!R) Q <= 1 b0; else if (S) Q <= 1 b1; else Q <= D; end endmodule S D C R Q P. 10

11 D-Latch Active High with Clear/Preset module flop (Q, D, G, C, P); output Q; // Flip-Flop Output input D; // Data Input input G; // Positive Gate input C; // synchronous Clear input P; // synchronous Preset reg Q; // Register Type or G or C or P) begin if (!C) Q <= 1 b0; else if (P) Q <= 1 b1; else if (G) Q <= D; end endmodule P D G C Q P. 11

12 Finite State Machine ACCESS IC LAB

13 What is FSM v A model of computation consisting of v a set of states, (limited number) v a start state, v input symbols, v a transition function that maps input symbols and current states to a next state. P. 13

14 v Memory Elements (ME) Elements of FSM v Memorize Current States (CS) v Usually consist of FF or latch v N-bit FF have 2 n possible states v Next-state Logic (NL) v Combinational Logic v Produce next state Based on current state (CS) and input (X) v Output Logic (OL) v Combinational Logic v Produce outputs (Z) Based on current state, or Based on current state and input P. 14

15 Mealy Machine v Output is function of both v Input and current state P. 15

16 Moore Machine v Output is function of current state only v Not function of inputs P. 16

17 Mealy Finite State Machine A serially-transmitted BCD (8421 code) word is to be converted into an Excess-3 code. An Excess-3 code word is obtained by adding 3 to the decimal value and taking the binary equivalent. Excess-3 code is self-complementing [Wakerly, p. 80], i.e. the 9's complement of a code word is obtained by complementing the bits of the word. Decimal Excess-3 Digit Code Code (BCD) = 8 bcd LSB MSB B out = 8 Excess-3 MSB MSB t clk LSB Excess-3 Code Converter B out t P. 17

18 Mealy Finite State Machine The serial code converter is described by the state transition graph of a Mealy FSM. State Transition Graph 0/1 S_0 1/0 S_1 1/0 S_2 0/1 S_3 S_4 0/0, 1/1 0/1 0/0, 1/1 1/0 S_5 S_6 input / output Next State/OutputTable next state/output state input 0 1 S_0 S_1 / 1 S_2 / 0 S_1 S_3 / 1 S_4 / 0 S_2 S_4 / 0 S_4 / 1 S_3 S_5 / 0 S_5 / 1 S_4 S_5 / 1 S_6 / 0 S_5 S_0 / 0 S_0 / 1 S_6 S_0 / 1 - / - v v v v 0/0, 1/1 0/1 The vertices of the state transition graph of a Mealy machine are labeled with the states. The branches are labeled with (1) the input that causes a transition to the indicated next state, and (2) with the output that is asserted in the present state for that input. The state transition is synchronized to a clock. The state table summarizes the machine's behavior in tabular format. P. 18

19 Design of a Mealy Finite State Machine To design a D-type flip-flop realization of a FSM having the behavior described by a state transition graph, (1) select a state code, (2) encode the state table, (3) develop Boolean equations describing the input of a D-type flip-flop, and (4) using K-maps, optimize the Boolean equations. Encoded Next state/ Output Table state next state output Next State/Output Table next state/output state input 0 1 S_0 S_1 / 1 S_2 / 0 S_1 S_3 / 1 S_4 / 0 S_2 S_4 / 0 S_4 / 1 S_3 S_5 / 0 S_5 / 1 S_4 S_5 / 1 S_6 / 0 S_5 S_0 / 0 S_0 / 1 S_6 S_0 / 1 - / - State Assigment S_0 S_1 0 1 S_6 S_4 1 0 S_2 1 1 S_5 S_3 q + 2 q + 1 q + 0 input input S_ S_ S_ S_ S_ S_ S_ P. 19

20 Design of a Mealy Finite State Machine S_0 S_0 S_1 S_ S_6 S_6 S_4 S_ S_5 S_5 S_3 S_3 x x 1 1 S_2 + = ' S_ S_0 S_0 S_ x x 0 0 S_1 S_6 S_6 S_4 S_4 S_5 S_5 S_3 S_3 S_2 S_ S_0 S_0 S_1 S_ S_6 S_6 S_4 S_ S_5 S_5 S_3 S_3 x x 1 1 S_2 + = S_ x x 1 0 S_0 S_0 S_1 S_1 S_6 S_6 S_4 S_4 S_5 S_5 S_3 S_3 S_2 S_2 Note: We will optimize the equations individually. In general -this does not necessarily produce the optimal (area, speed) realization of the logic. We'll address this when we consider synthesis. + = ' ' + ' ' + + = ' ' + ' ' + + = ' ' ' ' + = ' ' ' ' + = ' ' + ' ' + B out = ' ' + P. 20

21 Design of a Mealy Finite State Machine Realization of the sequential BCD-to-Excess-3 code converter (Mealy machine): + = ' ' + ' ' + + = ' ' + ' ' + + = ' ' ' ' ' D Q + = ' ' ' ' Q ' D Q Q ' Bin ' ' ' ' D Q Q ' ' B out clk P. 21

22 Design of a Mealy Finite State Machine Simulation results for Mealy machine: B_in B_out P. 22

23 Building Behavioral Models ACCESS IC LAB

24 Modeling FSM in Verilog vsequential Circuits vmemory elements of States (CS) vcombinational Circuits vnext-state Logic (NL) voutput Logic (OL) vthree coding styles v(1) Separate CS, OL and NL v(2) Combines NL+ OL, separate CS v(3) Combine CS + NL, separate OL P. 24

25 Coding Style 1 Separate CS, NL, OL v CS v NL v OL P. 25

26 v CS Coding Style 2 Combine NL+OL; Separate CS v NL+OL P. 26

27 v CS+NL Coding Style 3 Combine CS+NL; Separate OL v OL P. 27

28 Behavioral Models of FSM Example1 brake=0 accelerator=1 brake=0 accelerator=1 low speed medium speed brake=1 brake=1 brake=1 stopped high speed brake=1 brake=0 accelerator=1 brake accelerator clock speed brake=0 accelerator=1 P. 28

29 Verilog Coding 1 (CS, NL, OL) module speed_machine ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] current_state, next_state; // state encoding parameter stopped = 2`b00; parameter s_slow = 2`b01; parameter s_medium = 2`b10; parameter s_high = 2`b11; // CS ( posedge clock ) current_state <= next_state; // OL, Output Logic assign speed = current_state; // NL, Next-state Logic always@( state or accelerator or brake ) if ( brake == 1`b1 ) case ( current_state ) stopped: next_state <= stopped; s_low: next_state <= stopped; s_medium:next_state <= s_low; s_high: next_state <= s_medium; default: next_state <= stopped; endcase else if ( accelerator == 1`b1 ) case ( current_state ) stopped: next_state <= s_low; s_low: next_state <= s_medium; s_medium:next_state <= s_high; s_high: next_state <= s_high; default: next_state <= stopped; endcase else next_state <= current_state; endmodule P. 29

30 Verilog Coding 3 (CS+NL, OL) module speed_machine2 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define s_low 2`b01 `define s_medium 2`b10 `define s_high 2`b11 // OL is empty // because speed itself is state // NL + CS ( posedge clock ) if ( brake == 1`b1 ) case ( speed ) `stopped: speed <= `stopped; `s_low: speed <= `stopped; `s_medium:speed <= `s_low; `s_high: speed <= `s_medium; default: speed <= `stopped; endcase else if ( accelerator == 1`b1 ) case ( speed ) `stopped: speed <= `s_low; `s_low: speed <= `s_medium; `s_medium:speed <= `s_high; `s_high: speed <= `s_high; default: speed <= `stopped; endcase endmodule P. 30

31 State encoding P. 31

32 vfsm Design Conclusion vpartition FSM and non-fsm logic vpartition combinational part and sequential part vuse parameter to define names of the state vector vassign a default (reset) state P. 32

Chapter 6. Synchronous Sequential Circuits

Chapter 6. Synchronous Sequential Circuits Chapter 6 Synchronous Sequential Circuits In a combinational circuit, the values of the outputs are determined solely by the present values of its inputs. In a sequential circuit, the values of the outputs