FSM Examples. Young Won Lim 11/6/15

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1 /6/5

2 Copyright (c) 2 25 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice and Octave. /6/5

3 Latches and FF's 3 /6/5

4 Inputs and Outputs L B Traffic Lights - Outputs L A L B Sensor - Inputs T B T A T B L A T A T A L A T B L B 4 /6/5

5 States T A = L A L B L A T A = L A L B L A L B L B T B = L B L B L A L A T B = L A L A L B L B 5 /6/5

6 Moore State Transition Table S S T A T B S' S' S S T A T B S' X X X X X X X X S S S S T B S S T B X X X X X X X X S' = S S + S S = S + S S S T A T B S' S S T A S S T B X X X X X X X X S' = S S T A + S S T B 6 /6/5

7 States S S 2 L A L A L B L B S S 2 L A S S 2 L A L A =S L A =S S S S 2 L B S S 2 L B L B =S L A =S S 7 /6/5

8 Moore () inputs T A NextSt Compute NextSt from CurrSt, Ta, Tb T B Next State S' Current State S CurrSt This NextSt becomes a new CurrSt clk S' states : S : S : S2 : S3 S S S outputs L A L A L B L B outputs (LA/LB) : Green : Yellow : Red : X Compute NextSt CurrSt <= NextSt 8 /6/5

9 Moore inputs T A Inputs T A T B T B Current State S S Next State Current State S' = S + S Next States S' S S' = S S T A + S S T B S' = S + S S' = S S T A + S S T B S' S clk states : S : S : S2 : S3 outputs (LA/LB) : Green : Yellow : Red : X S S L A =S L A =S S L B =S L B =S S outputs Current State S S L A L A L Outputs B L L A =S L B B=S L A =S S L B =S S 9 /6/5

10 Verilog Gate Level Design - testbench `timescale ns/ps module traffic_controller_testbench; parameter cycle = 4; reg clock; always begin #(cycle/2) clock=~clock; end traffic_controller DUT (.clock(clock),.reset(reset),.ta(ta),.tb(tb),.la(la),.lb(lb) ); reg reset; reg TA, TB; wire [:] LA, LB; initial begin clock = ; reset = ; TA = ; TB = ; #; #(cycle) reset = ; #(cycle) TB = ; #(cycle) TA = ; #(cycle*3) TA = ; TB = ; #(cycle*3) TA = ; end initial begin $dumpfile("traffic.vcd"); $dumpvars(, DUT); #(cycle * ); $finish; end endmodule /6/5

11 Verilog Gate Level Design traffic_gate.v module traffic_controller(clock, reset, TA, TB, LA, LB); input clock, reset; input TA, TB; output [:] LA, LB; reg [:] S; wire [:] NextS; clock) begin: SEQ if (reset) #8 S = 2'b; else #8 S = NextS; end not #8 (Sb, S[]); not #8 (Sb, S[]); not #8 (TAb, TA); not #8 (TBb, TB); xor #8 (NextS[], S[], S[]); or #8 (NextS[], NS, NS2); and #8 (NS, Sb, Sb, TAb); and #8 (NS2, S[], Sb, TBb); buf #8 (LA[], S[]); and #8 (LA[], Sb, S[]); not #8 (LB[], S[]); and #8 (LB[], S[], S[]); endmodule /6/5

12 VCD Output with zero delay 2 /6/5

13 VCD Output with gate delays 3 /6/5

14 VCD Output with gate delays Output Delay 4 /6/5

15 Divide By N Counter reset S S Y= Y= Input: none Output: Y= every 3 cycles S2 Y= State Transition Table Curr St S S S2 Next St S S2 S Output Table Curr St S S S2 Output 5 /6/5

16 Encoding States State Transition Table Output Table State Transition Table Output Table Curr St Next St Curr St Output Curr St Next St Curr St Output S S S2 S S2 S S S S2 S S S2 S S2 S S S S2 S S S' S' S S Y S 2 S' S Y S S S' 2 S' S 2 S S' =S S Y =S S S' 2 =S 2 S S S Y =S 2 S S S S' =S S S' =S 2 S S S' =S 2 S S S S 2 6 /6/5

17 Resolution Time 7 /6/5

18 FF Timing (Ideal) D 3: Q 3: Inputs to FFs Outputs of FFs D 3 Q 3 D 3 Q 3 Inputs to FFs D 2 D Q 2 Q Outputs of FFs D 2 D Register Q 2 Q D Q D Q CLK 8 /6/5

19 Sequence of States (t) th edge (t+) th edge (t+2) th edge (t+3) th edge (t+4) th edge (t+5) th edge D 3: Inputs to FFs Q 3: Q(t) Q(t+) Q(t+2) Q(t+3) Q(t+4) Q(t+5) Outputs of FFs (t) th edge (t+) th edge (t+2) th edge (t+3) th edge (t+4) th edge (t+5) th edge D 3:?????? Find inputs to FFs Q 3: Q(t) Q(t+) Q(t+2) Q(t+3) Q(t+4) Q(t+5) which will make outputs in this sequence 9 /6/5

20 When NextSt becomes CurrSt Compute NextSt from CurrSt, Ta, Tb NextSt CurrSt This NextSt becomes a new CurrSt Compute NextSt CurrSt <= NextSt 2 /6/5

21 Finding FF Inputs D 3:?????? Inputs to FFs Q 3: Q(t) Q(t+) Q(t+2) Q(t+3) Q(t+4) Q(t+5) Outputs of FFs D 3 D 2 Q 3 Q 2 During the t th clock edge period, Compute the next state Q(t+) using the current state Q(t) and other external inputs D Q Place it to FF inputs D Q After the next clock edge, (t+) th, the computed next state Q(t+) becomes the current state Inputs 2 /6/5

22 Method of Finding FF Inputs D 3: Q 3: Q(t+) Q(t+2) Q(t+3) Q(t+4) Q(t+5) Q(t+6) Q(t) Q(t+) Q(t+2) Q(t+3) Q(t+4) Q(t+5) Find the boolean functions D3, D2, D, D in terms of Q3, Q2, Q, Q, and external inputs for all possible cases. Q 3 Q 2 Q Q I D 3 Q 3 Q 2 Q Q I D 3 D 3 Q 3 D 2 Q 2 D Q Q 3 Q 2 Q Q I D 3 Q 3 Q 2 Q Q I D 3 D Q Inputs 22 /6/5

23 State Transition D 3: Q 3: Q(t+) Q(t) Q(t+) Compute the next state using the current state and external inputs in the current clock cycle Q(t+) Q(t) Q(t+) Q(t) Q(t+) Inputs Inputs After the next clock edge, the computed next state (FF Inputs) becomes the current state (FF Outputs) 23 /6/5

24 Moore INPUT Next State Combinational Logic State Register Output Combinational Logic OUTPUT clock 24 /6/5

25 Mealy Machine INPUT Next State Combinational Logic State Register Output Combinational Logic OUTPUT clock 25 /6/5

26 References [] [2] M. M. Mano, C. R. Kime, Logic and Computer Design Fundamentals, 4 th ed. [3] J. Stephenson, Understanding Metastability in FPGAs. Altera Corporation white paper. July 29. /6/5