Sequential Circuit Timing. Young Won Lim 11/6/15

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2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice and Octave.

3 Latches and FF's 3

4 Register D 3 D Q Q 3 D 2 D Q Q 2 D 1 D Q Q 1 D 0 D Q Q 0 CLK CLK without delay without delay

5 Types of Diagrams a timing diagram without delays no delay (ideal case) no delay (ideal case) a timing diagram with delays input delay output delay Clk->Q 5

6 DFF Testbench module dff(d, clk, rst, q, qb); input d, clk, rst; output q, qb; reg q; clk) begin if (~rst) q = 0; else q = d; end assign qb = ~q; endmodule Nonblocking Assignments Blocking Assignments <= = initial begin clk =0; d =0; rst =1; rst =0; #20 rst = 1; #10 d <= 0; #10 d <= 0; $finish; end #10 d = 1; #10 d = 0; #10 d = 1; #10 d = 0; #10 d = 1; #10 d = 1; `timescale 1ns/100ps module dff_tb; reg d, clk, rst; dff U1 (d, clk, rst, q, qb); always #10 clk = ~clk; initial begin $dumpfile("test.vcd"); $dumpvars(0, dff_tb); end endmodule 6

7 Testbench with Nonblocking Assignments module dff(d, clk, rst, q, qb); input d, clk, rst; output q, qb; reg q; clk) begin if (~rst) q = 0; else q = d; end assign qb = ~q; endmodule initial begin clk =0; d =0; rst =1; rst =0; #20 rst = 1; #10 d <= 0; #10 d <= 0; $finish; end `timescale 1ns/100ps module dff_tb; reg d, clk, rst; dff U1 (d, clk, rst, q, qb); always #10 clk = ~clk; initial begin $dumpfile("test.vcd"); $dumpvars(0, dff_tb); end endmodule 7

8 DFF Testbench Waveforms Nonblocking Assignments #10 d <= 0; #10 d <= 0; samples the unchanged d input values at the posedge of clk Blocking Assignments #10 d = 1; #10 d = 0; #10 d = 1; #10 d = 0; #10 d = 1; #10 d = 1; samples the changed d input values at the posedge of clk 8

9 Blocking Assignments #10 d = 1; #10 d = 0; #10 d = 1; #10 d = 0; #10 d = 1; #10 d = 1; clk) begin if (~rst) q = 0; else q = d; end clk:0 1 d:0 1 d:1 clk) At the posedge of clk clk has changed to 1 Also, d has changed to its new value 9

10 Nonblocking Assignments Nonblocking Assignments #10 d <= 0; #10 d <= 0; In each of time slot which is delayed by 10 time units, there is only one assignment that can be scheduled simultaneously, (1) Allowing scheduling of assignments without waiting for its completion (2) Executed last in the time step in which it is scheduled (after all blocking assignments' execution) Regular Events samples the unchanged d input values at the posedge of clk Nonblocking Update Events Monitor Events Evaluate So, the input d update is done Update after the posedge clk 10

11 FF Input and Output Delays No delay No delay t d1 t d2 Inputs with delays t d3 Output with a delay 11

12 Reg to Reg 12

13 Clock Skew Clock skew Clock Source 13

14 Path Delay X X delay due to combinational blocks Y Y 1

15 Setup & Hold Time (1) Inputs with delays Output with a delay set up time hold time 15

16 Setup & Hold Time (2) 16

17 Clock Gating CLK EN possible clock skew problem EN 17

18 Max Path / Min Path Max path contamination delay propagation delay min path t c d the output is changing t c d t c d t delay 18

19 Rise / Fall Times t r Rise Time t pd f Fall Time Rise Time t pd r Fall Time t f v in v out v in t f t r = 2.2 τ n 2.2 τ p β n β p > 1 τ n τ p = R nc out R p C out R n R p < 1 = R n R p < 1 β n = 1.0 β p β n = 1.5 β p β n = 2.0 β p v out t pdf t pdr 19

20 PVT Variation Process Voltage Temperature High temperature Low temperature 20

21 FF Output Delay t c cq contamination delay propagation delay t p cq t c cq t p cq flipflop clock-to-q t c cq t delay t p cq 21

22 Path Delay t c d contamination delay propagation delay t c d combinational logic delay t c d t delay 22

23 Reg-to-Reg Delay (1) t c cq t FF t p cq t c cq t p cq t c d t c d t comb t c cq t p cq t c cq + t cd t delay t p cq + t pd t c d 23

24 Reg-to-Reg Delay (2) t c cq t FF t p cq t c d t comb t c cq t c d t c cq + t cd t delay t p cq + t pd t p cq 2

25 Setup Time / Hold Time Setup Time OK Setup Time Violation t p cq t p cq Hold Time OK Hold Time Violation t c cq t c d t c cq + t c d 25

26 Setup Time / Hold Time Setup Time Violation This part has been stabilized t p cq This is the intended operation Hold Time Violation Since the delay is too small signal passes through the 2nd FF t c cq + t c d 26

27 Resolution Time 27

28 References [1] [2] M. M. Mano, C. R. Kime, Logic and Computer Design Fundamentals, th ed. [3] J. Stephenson, Understanding Metastability in FPGAs. Altera Corporation white paper. July 2009.