CMOS Inverter. Young Won Lim 3/31/16
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1 CMO Inverter
2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the NU Free ocumentation License, Version 1.2 or any later version published by the Free oftware Foundation; with no Invariant ections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "NU Free ocumentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice and Octave.
3 Operation Modes In nlin nat nlin I ds V ds nat I ds = c noff Vn noff I ds = 0 Inverter (2B) 3
4 nmo Bias noff nlin Inverter (2B) 4
5 pmo Bias N N poff N p p N p p plin Inverter (2B) 5
6 Pinch-Of nlin More reverse biased More reverse biased - Constant flowing capacity nat Most of Vds Most of Vds To prevent forward biased junction Inverter (2B) 6
7 Notation Ip In Vp Vn Current Notation Voltage Notation V i n = V p V dd = V n V out = V p V dd = V n Inverter (2B) 7
8 Input Voltage V p = V p V p V in = Vp Ip Vp V p = V p V p = V in V dd = V dd V i n V i n = V p V dd = V n V n = V n V n = V in V ss V in = Vn In Vn Inverter (2B) 8
9 Output Voltage Vp VQ Vn VQ V Q = V p V p V Q = V n V = V p V dd = V n V ss = V n V out = V p V dd = V n Inverter (2B) 9
10 Characteristic Curves V in = Vp Ip Vp In Vp negative Vn Ip negative V in = Vn In Vn Inverter (2B) 10
11 Flip up pmo curves (-1) * Ip Ip In Vp Vn V in = Vp Ip Vp V in = Vn In Vn Inverter (2B) 11
12 hift right pmo curves -Ip Vp Vdd In V in = Vp Vp Vdd Vp V Q = V p V dd V in = Vn V Q Vn Vn = V n Inverter (2B) 12
13 Overlay pmo & nmo curves -Ip In V i n = V p V dd = V n V out = V p V dd = V n Vn Vp Vdd V in = Vp - Ip Vp V in = Vn In Vn Inverter (2B) 13
14 Intersection Points V n V i n = V p V dd = V n Ip In V out = V p V dd = V n V i n V p V n V dd 0 V p V in = Vp Vn Vp Vn 0 Vn Vp Vdd V i n V ss Inverter (2B) 14
15 Mode Changes -Ip In V n pat pat poff pat plin plin plin nlin nlin nat nat nat noff 0 V p V i n V p V n plin noff plin nat pat nat pat pat poff nat nlin nlin Vp Vdd Vn V in = Vp Vn Vn Vp Vn Inverter (2B) 15
16 Input witching 1 0 in nmo out v in ecreasing input voltage H v out Increasing output voltage H H nlin L L L time time v out Increasing output voltage nat noff L noff H nat v in nlin ecreasing input voltage Inverter (2B) 16
17 Input witching 0 1 in nmo out v in Increasing input voltage H v out ecreasing output voltage H H nlin L L L time time v out ecreasing output voltage nat noff L noff H nat nlin Increasing input voltage v in Inverter (2B) 17
18 [V IL, V IH ] & [V OL, V OH ] plin noff the worst case output when the worst L input is applied V OH pat nat the worst case output when the worst H input is applied V OL poff nlin V IL V IH can be considered as a logic L input can be considered as a logic H input Inverter (2B) 18
19 Noise Margin Noise plin noff V OH V IH V OL V IL V OH pat nat V OH NM H V IH V OL poff nlin V IL V IH V IL NM L can be considered as a logic L input can be considered as a logic H input V OL Inverter (2B) 19
20 imple Transistor Model Cutoff, subthreshold, or weak-inversion mode When V < V t : I d = 0 Triode mode or linear region (the ohmic mode) When V > V t and V < ( V V t ) I d = k ' W [ L (v v )v 1 gs t ds 2 v ] 2 ds aturation or active mode When V > V t and V ( V V t ) I d = 1 2 k ' W L (v gs v t )2 Inverter (2B) 20
21 Linear and aturation Models linear region I When V > V t and V < ( V V t ) I d = k ' W [ L (v v )v 1 gs t ds 2 v ] 2 ds 2(v gs v t ) (v gs v t ) V aturation or active mode I When V > V t and V ( V V t ) I d = 1 2 k ' W L (v gs v t )2 V Inverter (2B) 21
22 Bias Conditions Cutoff V < V t : Linear region V > V t V < ( V V t ) I V aturation V > V t V > ( V V t ) V Inverter (2B) 22
23 Characteristic Curve Inverter (2B) 23
24 References [1] [2] [3] W. Wolf, Modern VLI esign : ystems on ilicon [4] N. Weste,. Harris, CMO VLI esign: A Circuits and ystems Perspective [5] J. P. Uyemura, Introduction to VLI Circuits and ystems [6] [7] [8] [9] [10] [11]
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