TMS320C6201 Test and Evaluation Board Technical Reference

Transcription

1 TMS00 Test and valuation oard Technical Reference Literature Number: SPRU ecember Printed on Recycled Paper

2 IMPORTNT NOTI Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. ertain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ( ritical pplications ). TI SMIONUTOR PROUTS R NOT SIGN, INTN, UTHORIZ, OR WRRNT TO SUITL FOR US IN LIF-SUPPORT PPLITIONS, VIS OR SYSTMS OR OTHR RITIL PPLITIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local S sales office. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. opyright, Texas Instruments Incorporated

3 Preface Read This First bout This Manual How to Use This Manual Notational onventions This manual describes the operation of the TMS00 ( 0) test and evaluation board (T). The 0 T is a low-cost desktop card that helps you evaluate certain characteristics of the 0 digital signal processor (SP) to determine if the SP meets your application requirements. You can create your software to run on the board and expand the system using the prototype area. This manual tells you how to install and operate the 0 T with your system. It also describes key features of the T and helps you understand the T s key components. This book contains the following types of information: Introductory material, consisting of hapters and. hapter provides an overview of the 0 T and its components. hapter tells you how to install the T. Topical material, consisting of hapter, provides descriptions of hardware functions. Reference material, consisting of ppendixes and, provides PL code and schematics. This document uses the following conventions. Program listings, program examples, and interactive displays are shown in a special typeface. evice names are abbreviated with a, followed by the last two to four alphanumeric characters in the name. For example, TMS0x is written as x and TMS00 is written as 0. iii

4 Information bout autions / Related ocumentation / Related ocumentation From Texas Instruments Information bout autions This book contains cautions. This is an example of a caution statement. caution statement describes a situation that could potentially damage your software or equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related ocumentation You can use the following book to supplement this user s guide: Programming tmel s T Flash Family, Flash pplication Note (N-) (tmel literature number 0) Related ocumentation From Texas Instruments The following books describe the x devices and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response enter at (00) -. When ordering, please identify the book by its title and literature number. XSx mulator Installation Guide (literature number SPNU00) describes the installation of the XS0, XS0PP, and XS0WS emulator controllers. The installation of the XS emulator is also described. JTG/MPS mulation Technical Reference (literature number SPU0) provides the design requirements of the XS0 emulator controller, discusses JTG designs (based on the I. standard), and modular port scan device (MPS) designs. TMS0x Source ebugger User s Guide (literature number SPRU) tells you how to invoke the x simulator and emulator versions of the source debugger interface. This book discusses various aspects of the debugger, including command entry, code execution, data management, breakpoints, profiling, and analysis. iv

5 Related ocumentation From Texas Instruments TMS0x Source ebugger User s Guide (for SPRstations) (literature number SPRU) tells you how to invoke the x simulator and emulator versions of the source debugger interface for SPRstations. This book discusses various aspects of the debugger, including command entry, code execution, data management, breakpoints, profiling, and analysis. TMS0xx Technical rief (literature number SPRU) gives an introduction to the xx digital signal processor, development tools, and third-party support. TMS00 igital Signal Processor ata Sheet (literature number SPRS0) describes the features of the TMS0xx and provides pinouts, electrical specifications, and timings for the device. TMS0xx Peripherals Reference Guide (literature number SPRU0) describes common peripherals available on the TMS0xx digital signal processors. This book includes information on the internal data and program memories, the external memory interface (MIF), the host port, serial ports, direct memory access (M), clocking and phase-locked loop (PLL), and the power-down modes. TMS0xx PU and Instruction Set Reference Guide (literature number SPRU) describes the xx PU architecture, instruction set, pipeline, and interrupts for the TMS0xx digital signal processors. TMS0xx Programmer s Guide (literature number SPRU) describes ways to optimize and assembly code and includes application program examples. TMS0x Optimizing ompiler User s Guide (literature number SPRU) describes the x compiler. This compiler accepts NSI standard source code and produces assembly language source code for the x generation of devices. This book also describes the assembly optimizer, which helps you optimize your assembly code. TMS0x ssembly Language Tools User s Guide (literature number SPRU) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the x generation of devices. Read This First v

6 F Warning / Trademarks F Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part of F rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Trademarks 0 Hotline On-line, XS0, and XS0WS are trademarks of Texas Instruments Incorporated. L is a trademark of ata I/O. T and P are trademarks of International usiness Machines orporation. PL is a registered trademark of dvanced Micro evices, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SPR and SPRstation are trademarks of SPR International, Inc., but licensed exclusively to Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, licensed exclusively through X/Open ompany Limited. Windows and Windows NT are registered trademarks of Microsoft orporation. vi

7 If You If You Need Need ssistance... If You Need ssistance... World-Wide Web Sites TI Online Semiconductor Product Information enter (PI) SP Solutions 0 Hotline On-line North merica, South merica, entral merica Product Information enter (PI) () -0 TI Literature Response enter U.S.. (00) - Software Registration/Upgrades () -0 Fax: () - U.S.. Factory Repair/Hardware Upgrades () - U.S. Technical Training Organization () -0 SP Hotline () -0 Fax: () - mail: dsph@ti.com SP Modem S () - SP Internet S via anonymous ftp to ftp://ftp.ti.com/pub/tms0bbs urope, Middle ast, frica uropean Product Information enter (PI) Hotlines: Multi-Language Support Fax: mail: epic@ti.com eutsch + 0 or nglish Francais Italiano PI Modem S uropean Factory Repair + 0 urope ustomer Training Helpline Fax: sia-pacific Literature Response enter + Fax: + 00 Hong Kong SP Hotline + Fax: + 00 Korea SP Hotline + 0 Fax: + Korea SP Modem S + Singapore SP Hotline Fax: + 0 Taiwan SP Hotline + 0 Fax: + Taiwan SP Modem S + Taiwan SP Internet S via anonymous ftp to ftp://dsp.ee.tit.edu.tw/pub/ti/ Japan Product Information enter (in Japan) Fax: (in Japan) or (INTL) --0 Fax: +0-- or (INTL) -- SP Hotline +0-- or (INTL) -- Fax: or (INTL) --0 SP S via Nifty-Serve Type Go TISP ocumentation When making suggestions or reporting errors in documentation, please include the following information that is on the title page: the full title of the book, the publication date, and the literature number. Mail: Texas Instruments Incorporated mail: dsph@ti.com Technical ocumentation Services, MS 0 P.O. ox Houston, Texas - Note: When calling a Literature Response enter to order documentation, please specify the literature number of the book. Read This First vii

8 ontents ontents Overview of the TMS00 Test and valuation oard Provides an overview of the TMS00 test and evaluation board, including its key features and major functions.. Key Features of the TMS00 T Functional Overview of the TMS00 T Installing the TMS00 Test and valuation oard escribes the minimum hardware configuration required for the TMS00 test and evaluation board.. The TMS00 T Host Requirements TMS00 T Kit omponents TMS00 T onnection TMS00 T Installation TMS00 Test and valuation oard Operation escribes the TMS00 test and evaluation board and its various interfaces and key components.. ustom Power Supply Power Requirements Reset Generation lock Generation Interrupt Generation xternal Memories Host Port onnection Serial Ports and Timers onnection mulation Port onnection Prototyping rea Shunt Jumpers and IP Switches TMS00 T PL quations ontains the programmable logic source for the TMS00 T PL equations. TMS00 T Schematics ontains the schematics for the TMS00 T. ix

9 Tables Figures TMS00 T onnectivity TMS00 T ttaching ord Into Power Supply onnecting the Power Supply to the T onnecting the mulator to the T Power Supply onnector Tables efault T Shunt Jumper Settings efault T IP Switch Settings T Fuse Ratings T Memories T Shunt Jumpers T IP Switches x

10 hapter Overview of the TMS00 Test and valuation oard The TMS00 test and evaluation board (T) helps you evaluate certain characteristics of the TMS00 ( 0) fixed-point digital signal processor (SP) to ensure that it meets your application requirements. The T is self-contained, only requiring connections to an power supply and to your own emulation hardware and software. The T is platform independent and uses either an XS0 emulator controller for a P or an XS0WS emulator controller for a UNIX workstation. The 0 T carries a 0 SP on board to allow full-speed verification of 0 code. You can also use the T to design your own prototype systems. The 0 SP has Kbyte on-chip SRM that consists of Kbyte internal program/cache and Kbyte internal data memory. The T uses the 0 s -bit external memory interface to facilitate accesses to on-board synchronous and asynchronous memories. P or UNIX windows-oriented debugger simplifies code development and debugging. For more information about the debugger, see the TMS00 Source ebugger User s Guide or the TMS0x Source ebugger User s Guide for SPRStation. The T also has a 0 -bit host access port, a serial and timer access port, an I Standard.-compliant JTG connector for accessing the 0 s scan-based emulation features, and a through-hole area for design prototyping. You can also use the T as a reference when designing your own systems. Topic Page. Key Features of the TMS00 T Functional Overview of the TMS00 T Overview of the TMS00 Test and valuation oard -

11 Key Features of the TMS00 T. Key Features of the TMS00 T The 0 T has the following features: 0 capable of executing 00 million instructions per second (MIPS) Varied instruction cycle times of the 0: -ns instruction cycle time when using the SP s internal memories -ns instruction cycle time when using synchronous dynamic RM (SRM) and one-half rate external synchronous burst static RM (SSRM).-ns instruction cycle time when using the T s external SSRM, regardless of which other T memories are used K bytes.-ns SSRM M bytes -ns SRM K bytes -ns asynchronous static RM (SRM) K bytes 00-ns flash programmable erasable ROM (PROM) -bit host port header ccess to the 0 s serial ports and timers via a header mulator connector Prototyping area -

12 Functional Overview of the TMS00 T. Functional Overview of the TMS00 T Figure shows the basic block diagram and interconnects of the 0 T. The interconnects include the external memory, host port, emulation interfaces, and serial ports and timers. The 0 SP interfaces to the memories through a -bit data bus. Headers are situated between the synchronous and asynchronous memories to allow easy examination of the external memory interface s address, data, and control signals. The T s control signals are also available at these headers. dditional headers between the asynchronous memories and the prototyping area allow for access to asynchronous control signals and the data bus, which may be used in the prototyping area. Use the host port header to connect your host processor to the 0 s host port interface. This allows your host processor to access the 0 s internal memory. The serial ports and timers header allows access to the 0 s serial ports and timers. n emulation connector provides access to the I Standard. (JTG) scan-based emulation port of the 0. This port is a superset of the I. standard and is used by either an XS0 or an XS0WS emulator. Overview of the TMS00 Test and valuation oard -

13 Functional Overview of the TMS00 T Figure. TMS00 T onnectivity SSRM K JTG emulator connector Host port interface header mulation port Host port data H[:0] Host control 0 ontrol ddress [:] ata [:0] SRM M Serial ports and timers access header Serial ports[:0] Timers[:0] OOTMO[:0] uffering and observation headers SRM K OOTMO configuration IP switches PROM K uffering and prototype area headers -

14 hapter Installing the TMS00 Test and valuation oard This chapter provides installation instructions for the 0 T. Topic Page. The TMS00 T Host Requirements TMS00 T Kit omponents TMS00 T onnection TMS00 T Installation

15 The TMS00 T. The TMS00 T The 0 T is inches x inches and is intended for desktop use. It meets the following specifications: Instruction cycles of. ns (frequency equal to MHz). This is accomplished using a.-mhz oscillator and operating the 0 s phaselocked loop (PLL) clock in multiply-by-four mode. onfiguration of the 0 boot process using the T s on-board IP switches. These switches are set for the following: Use of the 0 s memory map Memory at address 0 is 0 internal RM oot-load startup process using -bit PROM with default timing in external address space Use of the emulator s TLK signal Figure shows the layout of the 0 T. -

16 Installing the TMS00 Test and valuation oard - Figure. TMS00 T Shunt jumpers JP Reset switch S Serial ports and timers access header J xternal emulator (TLK) clock J Host port header J mulation connector J Power connector J0 xternal 0 clock J Oscillator U OOTMO configuration IP switches S The TMS00 T

17 Host Requirements / TMS00 T Kit omponents / TMS00 T onnection. Host Requirements The T is platform independent and can be used with an XS0 emulator controller for a P or an XS0WS emulator controller for a UNIX workstation. The XSx mulator Installation Guide lists the minimum hardware requirements for your emulator. The installation instructions included with your emulator software lists the minimum software requirements for your emulator.. TMS00 T Kit omponents The kit contains the following items: 0 T ustom power supply TMS00 Test and valuation oard Technical Reference (this document) iskette containing T-related files. TMS00 T onnection efore you apply power to the T or connect the T to your emulator, see Table and Table to ensure that all shunt jumpers and IP switches are set to their default positions. Table and Table contain complete descriptions of all shunt jumpers and IP switches used on the T. See these tables before you change any default settings. -

18 TMS00 T onnection Table. efault T Shunt Jumper Settings indicates HIGH (), indicates LOW (0) Name Position Setting escription ROM protect JP Flash PROM write disabled TLK select JP Use XSx emulator s TLK signal NMI JP. Nonmaskable interrupt inactive XT_INT XT_INT XT_INT XT_INT JP. JP. JP. JP. Interrupts XT_INT XT_INT inactive PLLFRQ PLLFRQ PLLFRQ JP. JP. JP. MHz < LKOUT MHz LKMO0 LKMO JP. JP.0 PLL multiply-by-four mode RSV0 RSV RSV RSV RSV JP. JP. JP. JP. JP. Reserved MU0 MU JP. JP. TI emulation support LNIN JP. Little-endian mode addressing RY JP. xternal controller ready (to avoid stalling) HOL JP.0 onnects 0 to the system Unused Unused JP. JP. No Shunt No Shunt TINP0 TINP JP. JP. Timer inputs Installing the TMS00 Test and valuation oard -

19 TMS00 T onnection Table. efault T IP Switch Settings OFF indicates HIGH (), ON indicates LOW (0) Name Position Setting escription OOTMO0 OOTMO OOTMO OOTMO OOTMO S. S. S. S. S. OFF ON OFF OFF ON oot configuration settings for memory map with internal RM at address 0 and -bit PROM boot process SWUSR S. OFF User-defined input to U PL -

20 TMS00 T Installation. TMS00 T Installation The 0 T is connected to a power supply and an emulator. The following steps show how to connect the T to both. Never disconnect or reconnect any cables or other hardware devices while power is applied to the emulator or T. oing so can cause damage to your emulator and/or T. Step : Step : Step : Install your emulation hardware and software. nsure the emulator power is off. If you have an XS0WS emulator controller (for a UNIX workstation), switch off the power. If you have an XS0 emulator controller (for a P), power down the emulator by shutting down Windows and turning off your P. Insert the female end of the line cord into the power supply. Figure. ttaching ord Into Power Supply Power supply cord Installing the TMS00 Test and valuation oard -

21 TMS00 T Installation Step : onnect the power supply s male -pin connector into J0 of the T. Figure. onnecting the Power Supply to the T Power supply Shunt jumpers JP Reset S Power connector J0 Serial ports and timers access header J Host port header J mulation connector J J J Oscillator U IP switches S -

22 TMS00 T Installation Step : With moderate downward pressure, connect the -pin keyed connector from your emulator to J on the T. Figure. onnecting the mulator to the T Serial ports and timers access header J Shunt jumpers JP Reset S J Power connector J0 J Oscillator U IP switches S mulator connector Host port header J mulation connector J Installing the TMS00 Test and valuation oard -

23 TMS00 T Installation Step : Step : Turn on power to the emulator. If you have an XS0WS emulator controller (for a UNIX workstation), switch on the power. If you have an XS0 emulator controller (for a P), turn on your P. Plug the male end of the power supply s line cord into an outlet. This applies power to the T. n L on the power supply and one on the T indicates that power is applied. If you need to disconnect the T, unplug the T, then turn off power to the emulator (using the power switch if you have an XS0WS or by shutting down Windows and turning off your P if you have an XS0). -0

24 hapter TMS00 Test and valuation oard Operation This chapter describes the 0 T, its key components, and how they operate. It also provides additional information on the T s various interfaces. The 0 T consists of the following components: ustom power supply TMS00 T Memory control Power Reset generation lock generation Interrupt generation 0 external memory interface 0 host port interface Serial ports and timers interface mulation interface Prototyping area Shunt jumpers and IP switches.-in floppy diskette Topic Page. ustom Power Supply Power Requirements Reset Generation lock Generation Interrupt Generation xternal Memories Host Port onnection Serial Ports and Timers onnection mulation Port onnection Prototyping rea Shunt Jumpers and IP Switches

25 Power ustom Requirements Power Supply / Power Requirements. ustom Power Supply Figure. Power Supply onnector custom power supply provides.-,.-, and.0-v regulated supply voltages to the T when connected to an wall outlet. n L on top of the power supply illuminates when it has been properly connected to power. The L blinks when the power supply is connected to a wall outlet where the outlet is not connected to the T. The T s power supply must be loaded to regulate the voltages measured at its outlet. Voltages at the outlet without the load of the T appear unstable. Front view Gnd.0 V Gnd. V Gnd. V. Power Requirements Table. T Fuse Ratings Voltage Label L (located next to the power jack on the T) illuminates when power is applied to the -pin power jack J0. See Figure for details about applying power to the T. Table lists the appropriate fuse current ratings to protect the T components. Schematic reference designation Rating Purpose of Supply Voltage. V F.0 0 internals. V F.0 0 I/Os and T.-V components. P_V F 0. Prototype area.-v components.0 V F 0. T.0-V components.0 P_V F. Prototype area.0-v components -

26 Power Requirements / Reset Generation / Reset lock Generation Use only fuses with ratings listed in Table to avoid damage to the T. o not draw more current than allowed by the fuses. This can damage the power supply and the T.. Reset Generation t power up, power down, and during brownout conditions, a supply voltage supervisory circuit forces the 0 SP into a reset condition. Pressing the push-button switch S also forces a reset. In either case, the 0 s reset line is active (low) for a period of at least 00 ms.. lock Generation The 0 SP operates at frequencies up to 00 MHz. Two options for generation of the clock signal LKIN are provided on the T. -Ω resistor installed in location R selects oscillator U. Removing R and installing it as R selects the SM connector J as the source for the LKIN signal. These options, combined with the 0 s internal phase-locked loop (PLL), allow you to experiment with different clock frequencies. Use of the PLL in the multiply-by-four mode for a LKOUT frequency other than MHz requires the replacement of components R,, and. See the TMS00 igital Signal Processor ata Sheet for more information. The factory default configuration of the T uses a.-mhz oscillator to provide input to the 0 s PLL, which is set to operate in multiply-by-four mode. R is installed to select U as the source for the 0 s PLL. Shunt jumpers JP.0 (LKMO) and JP. (LKMO0) select the clock multiply-by-four mode. Shunt jumpers JP. (PLLFRQ) JP. (PLLFRQ) select a LKOUT frequency range of MHz. The oscillator and the PLL provide a LKOUT signal that has a period of approximately. ns, a frequency of MHz, and a duty cycle of approximately 0%. TMS00 Test and valuation oard Operation -

27 Interrupt lock Generation / Interrupt Generation / xternal Memories You can operate the 0 internally at frequencies up to 00 MHz by reconfiguring shunt jumpers JP.0 JP. and replacing the LKIN source. You must also replace oscillator U with a different frequency.0-v oscillator. You can use SM connector J by removing and installing the Ω resistor R in the location of R. When changing frequencies, see the TMS00 igital Signal Processor ata Sheet to achieve optimal performance for your desired configuration of the T.. Interrupt Generation Pressing the push-button switch S generates a manual reset of the 0. Shunt jumpers JP. (NMI) and JP. (XT_INT) JP. (XT_INT) pull the 0 s external interrupts up or down. The factory default shunt jumper settings must be pulled low because these interrupts are rising-edge sensitive. Figure, page -, shows solder connections for the interrupts at the upper right of the prototype area, to the right of U. You must remove the appropriate interrupt shunt jumper(s) to control these interrupts with non-t circuitry (for example, prototype circuitry).. xternal Memories The T provides four different types of memory for program execution and data storage. The T s memory types, their speeds and organizations, and the selected 0 chip enable signal are listed in Table : Table. T Memories Memory Type esignation Timing (ns) Organization Total 0 SSRM U0. K x bits K SRM U U M x bits M 0 SRM U0 U K x bits K ROM U U 00 K x bits K See the TMS00 igital Signal Processor ata Sheet for a description of the chip enable signals and the processor memory map. -

28 Host Port onnection / Serial Ports and Timers onnection / mulation Host Port onnection. Host Port onnection Header J connects to the T and an off-board (user supplied and programmed) host. The header is an MP 00 and the mating connector part number is MP 00.. Serial Ports and Timers onnection Header J allows access to the 0 s serial ports and timers. The header is an MP 00 and the mating connector part number is MP 00. Note: Timer input 0 (TINP0) and timer input (TINP) are pulled high by the factory default configuration of shunt jumpers JP. and JP., respectively.. mulation Port onnection mulation connector J connects the 0 s emulation port and either the XS0 or XS0WS emulator. Shunt jumpers JP. and JP. pull the MU0 and MU signal up or down. The factory default configuration causes these signals to be pulled up. For more information about emulation signals, see the JTG/MPS mulation Technical Reference. SM connector J allows you to provide an alternative TK signal. To use the alternative TK signal, shunt jumper JP must be moved from its factory default position to connect pins and. TMS00 Test and valuation oard Operation -

29 Prototyping rea.0 Prototyping rea Figure shows the through-hole area for prototyping located at the left end of the T. This area includes two sockets for user-programmable.-v dc V0 PL devices (U and U). Fused.-V dc (P V ) and.0-v dc (P V ) supply connections are provided at both the top and bottom edges of the prototyping area. Fuses protect against attempts to draw more current than is allowed by the power supply s design. Ground connections are provided at the extreme left end of the prototyping area. onnectors J and J provide connectivity to the 0 s external memory interface s data, address, and control busses. These -bit connectors provide a direct connection with the modern test equipment cables. (The header part number is MP 00 and the mating connector part number is MP 00.) ll bits of data are available at J. Only bits of address are available at J because the T s prototyping area shares the 0 s external address space with the on-board PROM. onsequently, only asynchronous devices may be interfaced to J and J. PL U logic equations (ppendix ) control buffers between the asynchronous memory portion of the T and the T s prototyping area. The 0 s external interrupts are available as test points NMI and XT_INT XT_INT. See section., Interrupt Generation, for details about the use of these test points. Use only fuses with ratings given in Table to avoid damage to the T. o not draw more current than allowed by the fuses. This can damage the power supply and the T. -

30 Shunt Jumpers and IP Switches. Shunt Jumpers and IP Switches Table. T Shunt Jumpers Name Position escription You can configure the on-board 0 and T devices by changing the settings of shunt jumpers and IP switches described in Table and Table. ROM protect JP Write protects Flash PROM Writes disabled Writes enabled TLK select JP Selects JTG clock SM connector (J) mulation connector (J) NMI JP. Nonmaskable interrupt ctive Inactive NON ontrolled by other logic (prototyping area) XT_INT XT_INT XT_INT XT_INT PLLFRQ PLLFRQ PLLFRQ LKMO0 LKMO JP. JP. JP. JP. JP. JP. JP. JP. JP.0 xternal interrupts: edge-driven (rising edge) ctive Inactive NON ontrolled by other logic (prototyping area) Selects one of three frequency ranges for the 0 LKOUT signal JP. JP. JP. Frequency Range MHz 0 MHz 0 00 MHz lock mode select. Selects the multiplication factor of the input clock frequency. LKOUT is x or x LKIN: JP.0 JP. lock Mode PLL multiply-by-one mode Reserved Reserved PLL multiply-by-four mode TMS00 Test and valuation oard Operation -

31 Shunt Jumpers and IP Switches Table. T Shunt Jumpers (ontinued) Name Position escription RSV0 RSV RSV RSV RSV MU0 MU JP. JP. JP. JP. JP. JP. JP. Reserved TI emulation support LNIN JP. Selects endianess of addressing ig endian Little endian RY JP. synchronous memory ready signal HOL JP.0 Hold request from host (external memory interface bus arbitration) UNUS UNUS TINP0 TINP JP. JP. JP. JP. Unused Unused Timer input 0 Timer input Note: indicates HIGH () indicates LOW (0) Table. T IP Switches Name Position escription OOTMO0 OOTMO S. S. oot mode configuration. See the TMS0xx Peripherals Reference Guide for a complete description. OOTMO OOTMO OOTMO S. S. S. SWUSR S. User-defined input to U PL -

32 ppendix TMS00 T PL quations This appendix contains the programmable logic source for the TMS00 test and evaluation board PL equations. These were compiled with T I/O L version.0. -

33 Running TMS00 Title ttribute T PL Reference quations module U_ML Title PL NM Memory Logic lock (PL ML) PL # U, 00 * WG NM TMS00 Test & valuation oard SSY # OMPNY Texas Instruments, Incorporated SYNTHSIS TOOL: L esign nvironment v.0 U device PV0 ; The PLLVV0 is a pin PL N clkout ce_ awe_ aoe_ ea ce_ N tp tp tp tp swuser N reset_ a_dir a_oe_ romce_ p_ce_ p_dir N p_dboe_ p_aboe_ tp tp tp V pin ; NO ONNT pin ; lock out from 0 pin ; hip enable from 0 pin ; synchronous write enable from 0 pin ; synchronous output enable from 0 pin ; MIF address bit from 0 pin ; hip enable from 0 pin ; NO ONNT pin ; Test point() input undefined pin 0; Test point() input undefined pin ; Test point() input undefined pin ; Test point() input undefined pin ; Switch input user defined pin ; Ground pin ; NO ONNT pin ; Reset pin ; synchronous direction pin ; synchronous buffer output enable pin ; ROM hip nable pin 0; Prototype chip enable pin ; Prototype buffer direction pin ; NO ONNT pin ; Prototype data buffer output enable pin ; Prototype addr buffer output enable pin ; Test point() output undefined pin ; Test point() output undefined pin ; Test point() output undefined pin ; Power -

34 TMS00 Running Title ttribute T PL Reference quations quations ecause the TMS00 may be in part of a write cycle (i.e., setup or hold time) when awe_ is inactive, the aoe_ signal should be used to determine the direction of the access. axoez axwez ccess 0 0 Invalid combination with the SP Should not happen so disable the buffers 0 Read from asynchronous type to the SP Should cause buffers to output towards the SP 0 Write (strobe) to asynchronous type from the SP Should cause buffers to output towards async type ould be part of a write cycle (i.e., write setup or hold time) Should cause buffers to output towards async type a_dir = aoe_; > (i.e., SP to external memories) when, > (i.e., external memories to SP) when 0 a_oe_ = (ce_ & ce_ & awe_ & aoe_) # (!awe_ &!aoe_); romce_ = ce_ # ea; Select flash ROM when ea = 0 p_ce_ = ce_ #!ea; Select Prototype area when ea = p_dir =!(!ce_ & ea) # aoe_; p_dboe_ = (awe_ & aoe_) # (!awe_ &!aoe_) # ce_ #!ea; p_aboe_ = 0; Test_Vectors ([ ce_, ce_,aoe_, awe_] > [a_dir, a_oe_]) [,, 0, 0 ] > [ 0, ]; [,, 0, ] > [ 0, 0 ]; [,,, 0 ] > [, 0 ]; [, 0,, ] > [, 0 ]; [ 0,,, ] > [, 0 ]; [,,, ] > [, ]; TMS00 hapter Title ttribute T PL Reference quations -

35 Running TMS00 Title ttribute T PL Reference quations Test_Vectors ([ce_, ea, aoe_, awe_] > [romce_, p_ce_, p_dir, p_dboe_, p_aboe_]) [ 0, 0, 0, 0 ] > [ 0,,,, 0 ]; [ 0, 0, 0, ] > [ 0,,,, 0 ]; [ 0, 0,, 0 ] > [ 0,,,, 0 ]; [ 0, 0,, ] > [ 0,,,, 0 ]; [ 0,, 0, 0 ] > [, 0, 0,, 0 ]; [ 0,, 0, ] > [, 0, 0, 0, 0 ]; [ 0,,, 0 ] > [, 0,, 0, 0 ]; [ 0,,, ] > [, 0,,, 0 ]; [, 0, 0, 0 ] > [,,,, 0 ]; [, 0, 0, ] > [,,,, 0 ]; [, 0,, 0 ] > [,,,, 0 ]; [, 0,, ] > [,,,, 0 ]; [,, 0, 0 ] > [,,,, 0 ]; [,, 0, ] > [,,,, 0 ]; [,,, 0 ] > [,,,, 0 ]; [,,, ] > [,,,, 0 ]; end -

36 ppendix TMS00 T Schematics This appendix contains the schematics for the TMS00 T. -

37 - NOTS, UNLSS OTHRWIS SPIFI:.. RSISTN VLUS R IN OHMS. PITN VLUS R IN MIROFRS.. HIGHST RFRN SIGNTOR US:. RMI PS. TNTLUM PS T. IOS. FUSS F. ONNTORS/HRS J F. SHUNTS JP G. FILTR L H. RSISTORS R0 I. SWITHS S J. TST POINTS K. I S U RV RVISIONS SRIPTION N00() M. WKINS FORML RLS N0() M. WKINS Nxxxxx() M. WKINS T PPROV J. LRK J. LRK TMS00 T Schematics. UNUS RFRN SIGNTORS:. RSISTORS R,R. SWITHS S,S,S. TST POINTS. I S U,U,U,U,U. U UI OMPRIS SINGL TMS00. THIS IS ONTT G VI THT IS TOO LRG TO SHOW ON SINGL SHT. THIS RVISION OF TH OR IS OMPTIL WITH RV.X OF TH 0 SILION. LL FOUR SHIL ONNTIONS OF J N J MUST ONNT TO TH GROUN PLN.. SHUNTS FOR NMI N XT_INT XT_INT, S PPROPRIT, MUST NOT PULL UP(V) OR OWN() FOR ONTROL OF THS SIGNLS.. PG ORR N NUMRING MY HNG TWN RVISIONS OF TH SHMTIS RVISION STTUS OF SHTS RV SH RV SH RV SH NXT SSY PPLITION US ON WN G. ONNLLY HK M. VIS NGR G. ONNLLY NGR MGR R. LRNR Q J. WHISONNT MFG M. JKSON RLS J. LRK T 0 T T T T T T TXS INSTRUMNTS SOFTWR VLOPMNT SYSTMS SMIONUTOR GROUP HOUSTON, TXS Title TMS00 TST & VLUTION OR Size ate: ocument Number 00 Wednesday, October, Sheet of Rev

38 TMS00 T Schematics - TMS00 T Schematics V LOK XT. 0 LOK XT. JTG V V V V (P) (S) (RS) 0 LOK/ONTROL LOK INUM RSV NMI INUM0 RSV XT_INT INUM P PLLFRQ XT_INT PLLFRQ XT_INT RSV XT_INT INUM RSV0 RST LKMO0 RSV IK PLLFRQ LKOUT LKOUT LKMO MU MU0 0K R0 0K R0 0K R0 RSV RSV RSV RSV RSV P RSV RSV G RSV T RSV0 PLLG PLLV W TO F0 LKOUT F LKOUT INUM W INUM INUM INUM0 Y IK Y MU W MU0 T TRST R TK R TI L TMS 0 PLLFRQ PLLFRQ PLLFRQ PLLF LKMO LKMO0 0 LKIN U XT_INT V XT_INT W XT_INT U XT_INT L NMI K RST U 0_LOK_ONTROL / OUT V OS U 0 HR X J OUT IN F L SM J SM J HR X JP NO_POP R R R + 0 T Y Y Y Y Y Y Y Y 0 V O O LVTH0 U of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

39 - OOTMO0 OOTMO OOTMO OOTMO OOTMO TMS00 T Schematics SWUSR V R R R R R R0 0K 0K 0K 0K 0K 0K U OOTMO OOTMO OOTMO OOTMO OOTMO0 K TINP K TINP0 M F M M M0 H TOUT M TOUT0 M M M M0 TOUT TOUT0 0_OOT_ONTROL S TINP0 TINP TXS INSTRUMNTS Title Size TMS00 TST & VLUTION OR ocument Number 00 Rev 0 OOT ONTROL ate: Wednesday, October, Sheet of

40 TMS00 T Schematics - TMS00 T Schematics V V 0 HPIF LOK H H H0 H H H H0 H H H H H0 H H H H H H H H H H H H H H H H H H H0 HNTRL HNTRL0 HHWIL H H0 HR/W HS HS HS HS HINT H HRY H[0..] HS H0 H H H H H H0 H H H H H H H H 0 H F HNTRL HNTRL0 HHWIL H H0 HR/W HS HS HS J HRY H HINT U 0_HPIF MITOR J 0K R 0K R of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

41 - TINP TOUT0 TINP0 TOUT J MITOR OOTMO0 OOTMO OOTMO OOTMO OOTMO UF L LKS LKS0 H M LKR LKR0 F L LKX LKX0 J R R0 G R X X0 P FSR FSR0 F P FSX FSX0 0_MSP TMS00 T Schematics TXS INSTRUMNTS Title Size TMS00 TST & VLUTION OR ocument Number 00 Rev 0 SRIL IF ate: Wednesday, October, Sheet of

42 TMS00 T Schematics - TMS00 T Schematics V 0 US LOK 0 SSLK SLK [..] [0..] HOL HOL R LNIN RY SSW SSO SSS S0 SW SS SRS W O SLK SSLK F SRS SS F SW F SSO O W S0 0 SSS SSW Y R HOL H LNIN 0 F F 0 F 0 F 0 0 F F F F F 0 HOL W RY 0 Y 0 J K 0 L K M M P P R T R U 0 U T V V W V W Y U 0_MIF R R0 R R 0K R 0K R 0K R 0K R0 0K R 0K R 0K R 0K R 0K R 0K R 0K R 0K R R R R0 R R R R R R R R R R R R R R R0 R R R R R R R R R R0 R R R R R R R of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

43 TMS00 T Schematics - V V SSRM [0..] [..] SSW SSS SSO SSLK ZZ N N N N N N 0 QP QP 0 QP QP 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q MO GW# W# S# SP# V# O# # # LK W# W# W# W# GVTGT U0 of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

44 TMS00 T Schematics - TMS00 T Schematics V V V V V V V V SRM S SLK SLK SLK SLK [..] [0..] SW SS SRS S0 SW SS SRS S0 SW SS SRS SW SS SRS 0 S Q Q Q Q Q Q Q Q Q Q Q Q0 0 VQ VQ VQ VQ V V LK K W S RS S QM TMSG U Q Q Q Q Q Q Q Q Q Q Q Q0 0 VQ VQ VQ VQ V V LK K W S RS S QM TMSG U Q Q Q Q Q Q Q Q Q Q Q Q0 0 VQ VQ VQ VQ V V LK K W S RS S QM TMSG U Q Q Q Q Q Q Q Q Q Q Q Q0 0 VQ VQ VQ VQ V V LK K W S RS S QM TMSG U of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

45 -0 LKOUT W O SWUSR RST V U N V LK/I0 N I I/O0 I I/O I I/O 0 I I/O I I/O I I/O 0 I I/O I I/O I I/O I0 I/O I N N _IR _O ROM P_ P_IR P_O P_O TMS00 T Schematics PLLVV0 J TXS INSTRUMNTS Title Size TMS00 TST & VLUTION OR ocument Number 00 Rev MMORY LOGI ate: Wednesday, October, Sheet of

46 TMS00 T Schematics - TMS00 T Schematics V V RIVN US T _IR _O _[0..] [0..] 0 _0 0 _ IR O IR O V V V V U SNLVH IR O IR O V V V V U SNLVH of Sheet ate: Rev ocument Number Size Title Wednesday, October, 0 TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

47 TMS00 T Schematics - V V RIVN US R _M _M _M _M0 M M M M0 _ _ _ _0 0 _[..] [..] _ _ _ _0 0 _0 0 _0 0 0 O O O O Y Y 0 Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0 0 V V V V U SNLVH 0 O O O O Y Y 0 Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0 0 V V V V U SNLVH of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

48 TMS00 T Schematics - TMS00 T Schematics V RIVN ONTROL V _HOL HOL SLK _LKOUT _R _SSW _LKOUT _SLK W _SSO R SW LKOUT _SW _W SSO _SSS S0 _S0 LKOUT SRS SSS O _O _SRS _SS SS SSW SSLK _SSLK 0K R0 0 O O O O Y Y 0 Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0 0 V V V V U SNLVH of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

49 TMS00 T Schematics - V SHUNTS & OSRVTION ONNTORS P_ ROM _IR _R _LKOUT HOL _HOL _LKOUT _M _M _M _M0 TINP TINP0 _[..] _LKOUT P _SSLK _ 0 RSV _SLK _[0..] O MU HOL RY _ _ _ _0 _SSO _SSW _SSS _S0 _SW _SS _SRS _W _O _ _ _0 RST NMI INUM INUM INUM INUM0 IK RY LNIN MU0 RSV RSV0 RSV RSV LKMO LKMO0 PLLFRQ PLLFRQ PLLFRQ XT_INT XT_INT XT_INT XT_INT 0 0 _0 _0 _0 _0 0K R 0 0 JP 0 0 JP 0 0 JP MITOR J MITOR J MITOR J 0K R 0K R 0K R 0K R NO_POP R NO_POP R 0K R 0K R 0K R.K R0.K R 0K R 0K R 0K R 0K R 0K R 0K R 0K R 0K R0 0K R 0K R 0K R 0K R 0K R 0K R 0 of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

50 TMS00 T Schematics - TMS00 T Schematics V V SRM _O _W _ _[0..] _[..] _ _ _O _W _ _0 _ _0 0 _0 0 _0 0 _ I/O I/O I/O I/O I/O I/O 0 I/O0 I/O I/O I/O I/O I/O 0 I/O I/O I/O I/O V V NU O W 0 U L TVJ U I/O I/O I/O I/O I/O I/O 0 I/O0 I/O I/O I/O I/O I/O 0 I/O I/O I/O I/O V V NU O W 0 U L TVJ U0 of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

51 TMS00 T Schematics - V V V V V FLSH ROM _O _O _O ROM_W ROM ROM_W ROM ROM_W ROM ROM_W _[0..] _[..] _W ROM_W _O ROM _0 _0 0 _0 _0 0 _0 _0 HR X JP I/O I/O 0 I/O I/O I/O I/O I/O I/O0 V W O TLV J U I/O I/O 0 I/O I/O I/O I/O I/O I/O0 V W O TLV J U I/O I/O 0 I/O I/O I/O I/O I/O I/O0 V W O TLV J U I/O I/O 0 I/O I/O I/O I/O I/O I/O0 V W O TLV J U 0K R0 of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

52 TMS00 T Schematics - TMS00 T Schematics PROTOTYP R RIVN US T V V _[0..] P_[0..] P_IR P_O _0 0 _0 _0 _ P_ P_ P_ P_0 P_0 P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ IR O IR O V V V V U SNLVTH IR O IR O V V V V U SNLVTH of Sheet ate: Rev ocument Number Size Title Wednesday, October, Texas Instruments TMS00 TST N VLUTION OR 00

53 TMS00 T Schematics - PROTOTYP R RIVN US R/TRL PL PL V V V V V P_O P_R _R P_[..0] P_ P_ P_ P_0 _O _W P_O P_W _[..] _ _ _ _0 P P_ P _ P_0 _0 P P P P P P P_0 _0 P P P P P P P P N N N N I/O I/O I/O I/O I/O I/O 0 I/O I/O I/O I/O0 V I I0 I I 0 I I I I I I I LK/I0 PLLVV0 J U I I0 I I I I I I I I I LK/I0 IO IO IO IO IO IO IO IO IO IO0 0K R 0K R 0K R 0K R 0K R 0K R N N N N I/O I/O I/O I/O I/O I/O 0 I/O I/O I/O I/O0 V I I0 I I 0 I I I I I I I LK/I0 PLLVV0 J U I I0 I I I I I I I I I LK/I0 IO IO IO IO IO IO IO IO IO IO0 0 O O O O Y Y 0 Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0 0 V V V V U SNLVTH 0 O O O O Y Y 0 Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0 0 V V V V U0 SNLVTH of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST N VLUTION OR 00

54 TMS00 T Schematics - TMS00 T Schematics P_V P_V PROTOTYP R ONNTORS XT_INT XT_INT XT_INT XT_INT NMI P_[..0] P_ _LKOUT _HOL HOL RY P_R P_ P_ P_ P_0 P_O P_W P_[0..] _HOL HOL P_R RY P_ P_O P_W P_ P_ P_ P_0 P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_0 P_ P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P LKOUT P_0 P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_V P_V MITOR J MITOR J XT_INT XT_INT XT_INT XT_INT NMI P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_ P_W _HOL P_ P_R _LKOUT P_ P_ P_0 HOL RY P_O P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_0 P_ P_ P_ P_ P_ P_ P_ P_ P_0 P_ P_ P_ P_ of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST N VLUTION OR 00

55 TMS00 T Schematics -0 POWR SUPPLY LO FOR VOLT V V P_V P_V FUS PROTOTYP POWR POWR_ON V V V V V V FUS MIN POWR 0 POWR & LOKS RST L V V V V V N V J V V V P V J V V V V V V V V V V V V V F V M V V N V Y V V V V V V F V V F V V 0 V H V V F V V K V V M V F V P V V U V V T V V T V V V V V V V V V V F V W V V U V N V T V M V R V K V N V 0 V L V 0 V J V 0 V H V V G V V G V V V V V V V V V V V V 0 V V V UH 0_POWR N N N 0 N N R N N G N H N H N J N K N UG 0_N P N P N F F F F F F G F G J N U V V Y F F0 0 Y U T R N L M L G F U 0_GROUN 0 0 R0 0 R0 0 R0 0 R0 NO POP J S.0V.V.V POWR J0 RST PFO RST MR PFI V M0TR U. F 0. F.0 F 0. F.0 F 0K R 0K R K R00 of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

56 TMS00 T Schematics - TMS00 T Schematics 0 THRML LLS V V V V V V V V V0 V U U U U U U U U U0 U T T T T T T T T T0 T R R R R R R R R R0 R P P P P P P P P P0 P N N N N N N N N N0 N M M M M M M M M M0 M L L L L L L L L L0 L K K K K K K K K K0 K J J J J J J J J J0 J 0_THRML_LLS UI of Sheet ate: Rev ocument Number Size Title Wednesday, October, 0 TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

57 TMS00 T Schematics - V V V V V V V OUPLING + NO_POP T + NO_POP T0 + T + T + T + T + T + T +. T +. T of Sheet ate: Rev ocument Number Size Title Wednesday, October, TXS INSTRUMNTS TMS00 TST & VLUTION OR 00

58 Index Index SRM -, -, - assistance from Texas Instruments attaching cord to power supply - emulator to T - power supply to T - boot process -, - OOTMO0 OOTMO IP switches -, -, - cautions iv, -, -, - changing default settings - LKIN signal - clock - connecting cord to power supply - emulator to T - power supply to T - connections emulation port - host port header - required - serial ports and timers access header - connectivity - conventions, notational iii custom power supply -, - vii data bus - outlet - debugger - defaults changing - IP switch - oscillator - shunt jumper - design prototyping - dimensions, T - IP switches OOTMO0 OOTMO -, -, - changing default settings - default settings -, - descriptions - on the T layout diagram - SWUSR - disconnecting the T -0 documentation about this manual iii how to use this manual iii related iv to v SP, features - emulation signals - emulator -, - emulator connector -, -, - external 0 clock - external emulator (TLK) clock - external memories - Index-

59 Index F F warning vi flash memory -, -, - fuse ratings - G generation clock - interrupt - reset - ground connections - H headers - See also individual header names host access port - host port header description -, - in connectivity diagram - on the T layout diagram - size - host requirements - I information about cautions iv installation connecting cord to power supply - connecting emulator to T - connecting power supply to T - T - to -0 instruction cycle time -, - interrupt generation - J JTG connector - K kit components - L layout, T - Ls -0, - M manual reset - memory connectivity - types - memory map -, - multiply-by-four mode -, - N non-t circuitry - notational conventions O iii operation, T - to - oscillator -, - P PL equations - to - PROM -, -, -, - PLL -, - power connector - power requirements - power supply -, - programmable devices - prototyping area -, - R reconfiguring on-board devices - shunt jumpers - related documentation iv to v requirements host - power - reset line - reset switch - resetting the 0 SP -, - ROM - Index-

60 Index S SSRM -, -, - scan-based emulation - schematics - to - SRM -, -, - serial ports and timers access header description -, - in connectivity diagram - on the T layout diagram - shunt jumpers changing default settings -, - default settings - descriptions - to - on the T layout diagram - reconfiguring - SM connector -, - specifications, T - SWUSR IP switch - T TK signal - TLK signal -, - T components - connectivity diagram - disconnecting -0 functional overview - to - fuse ratings - headers - to - installation - to -0 interconnects - to - key features - kit components - layout - Ls -0, - memory -, - operation - to - purpose iii, - required connections - schematics - to - specifications - test points - W warning, F X vi XS0 -, -, - XS0WS -, -, - Index-