Non-Destructive Micro-Raman Analysis of Si Near Cu Through Silicon Via

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1 Electron. Mater. Lett., Vol., No. (), pp. 1-9 DOI: 1.17/s Non-Destructive Micro-Raman Analysis of Si Near Cu Through Silicon Via Jae Hyun Kim, 1,2 Woo Sik Yoo, 3 and Seung Min Han 1, * 1 Graduate School of Energy Environment Water Sustainability, Korea Advanced Institute of Science and Technology, Daejeon 34141, Korea 2 Metrology and Inspection Technology Team, SK hynix, Icheon 17336, Korea 3 WaferMasters, Inc., San Jose 95112, USA (received date: 2 November 216 / accepted date: 15 December 216) Silicon near Cu through-silicon vias (TSVs) develops stresses during processing steps, and the local stress of Si around Cu TSVs of sizes ranging from 4 to 8 µm was characterized using micro-raman spectroscopy as a function of processing steps. Micro-Raman measurements showed that the max stress sum, σ r + σ θ, is size dependent, where the stress sum of 88.7 MPa in the compressive direction was measured in Si for 8 µm sized Cu via, and this max stress sum, σ r + σ θ, decreased to 21 MPa in compression for 4 µm sized Cu via. With the deposition of oxide/nitride overlayers, the stress sum was found to switch sign to MPa in the tensile direction for 8 µm sized Cu via after deposition of the SiN overlayers with residual compressive stress caused by ion bombardment. The measured stresses by micro-raman was used to determine the keep-off-zone that can be used in device design to ensure reliability, and compared against the TCAD simulations results. Keywords: Cu TSV, Si stress, micro-raman, TCAD 1. INTRODUCTION As silicon complementary metal-oxide-semiconduct-or (CMOS) devices are continuously scaled to approach 1 nm, [1] the industry is facing difficult technical challenges, not only in the process development, but also in quality control and/or device reliability. The international technology roadmap for semiconductors (ITRS) targets is likely to be delayed or revised due to the difficulties in overcoming these challenges. While conventional (front-end-of-line (FEOL)) scaling is close to being realized, improvement of device performance and functionality through back-end-of-line (BEOL) packaging technology is needed. Recent developments in three-dimensional integrated circuit (3-D IC) has gained strong interest since circuit real estate can be significantly reduced. [2-4] In suitable integration of memory and logic devices through 3-D packaging is currently being developed, *Corresponding author: smhan1@kaist.ac.kr KIM and Springer with through-silicon-vias (TSVs) being a prominent technology. [5] Development of TSV technologies thus far has been directed at the processing condition for Cu metallization followed by FEOL passivation layer deposition. However, such processing steps, in forming TSVs, leads to undesirable Si stress being induced near the TSVs due to the difference in coefficients of thermal expansion (CTE) between TSV Cu and Si during subsequent BEOL thermal cycling steps. The thermally induced stresses around the Cu TSVs can not only cause micro-cracks to form in the surrounding Si, [6] it can also affect the variation of carrier mobility in devices placed near the Cu TSVs. Depending on the specified tolerance for variation in transistor performance, [7-1] the keep-out-zone (KOZ) surrounding the TSVs is set by design rules for device layout, [1] where devices are only fabricated outside of this zone. Therefore, it is crucial to understand the stress distribution near TSVs in relation to dimensions (diameter, depth and pitch) at various stages of device integration processing steps. As the device technology node advances, 1

2 2 J. H. Kim et al. TSV diameter and pitch dimensions shrink and deepen; as a consequence, TSV volume and aspect ratio (AR: depth/ diameter) also change. TSV integration schemes, including process sequence and the number of processing steps, also vary with technology node [11] and integration scheme. Since the layout and dimensions of TSVs keep evolving, it is important to establish a proper local Si stress monitoring technique, which can be used in actual device design, development, and manufacturing. [12-14] Recognizing the need to determine the stress distribution near TSVs, many techniques have been used to measure TSV Cu and Si stress. [14-19] Synchrotron X-ray microdiffraction seemed to be the most powerful technique for analyzing crystal orientation and stress in TSV Cu and Si [15,17] since it can provide in-situ monitoring of strain during high temperature annealing. However, this technique requires special facilities and cannot be used as a practical in-line stress monitoring technique in a semiconductor production line. Micro-Raman spectroscopy is a nondestructive method and does not require any prior sample preparation. [13,14,16,2,21] By selecting a proper excitation wavelength, local stress in Si near the depth of the device channel can be characterized with a high spatial resolution of.5 μm. Micro-Raman spectroscopy measurements allow for stress measurement after each processing cycling step such as dielectric film deposition of SiO 2 and SiN at elevated temperatures. Since the stacks of dielectric layers on top of TSV are mostly transparent in the visible wavelength range, they have limited effect on the Raman signal intensity from Si even after considering interference fringes with no change in the Raman shift. These features, therefore, make micro- Raman spectroscopy a suitable in-line localized Si stress monitoring technique. In this study, local Si stress distribution near Cu TSVs with various via sizes with and without passivation layers were characterized using micro-raman spectroscopy and compared against FEM analysis using technology computer-aided design (TCAD) software. Effects of thermal cycling on the local Si stress distribution around Cu TSVs were characterized after depositing transparent SiO 2 and SiN thin films (>11 layers) on top of Cu TSVs. Si stresses, which are dependent on TSV size, were characterized and discussed from the perspective of the microstructural change in the Cu TSV. This is the first report on using micro Raman method to nondestructively characterize and analyze the stresses in Si as a function of via size then again as a function of processing steps. It should be noted that the Cu TSVs explored in this study is in the range of 4-8 μm, which is practical dimension for high density 3-D memory packaging, known as high bandwidth memory (HBM), that is currently being developed in the industry. [22] 2. EXPERIMENTAL PROCEDURE 2.1 Fabrication of Cu TSV array Cu TSV arrays with dimensions of 4-8 μm in diameter were fabricated on Si (1) wafer for all TSVs (Fig. 1(a)). The depth and spacing between Cu TSVs were fixed at 6 μm and 1 μm, respectively. The electroplated Cu was annealed at 1 C for 1 hr in a vertical furnace followed by 4 C for 1 min using a rapid thermal annealing (RTA) system. During the thermal annealing steps, Cu diffused up to the top surface to form a protrusion [23-25] since the larger CTE of Cu caused diffusion up the top surface of the via; the Cu vias then were planarized by chemical mechanical polishing (CMP) (Fig. 1(b)). [26] Transparent SiO 2 and SiN thin films (>11 layers) were finally deposited by plasma enhanced chemical vapor deposition (PECVD) at 4 C on Si wafers with Cu TSV arrays and cooled to room temperature (Fig. 1(c)). Highly compressive SiN films were deposited with a source gas flow ratio (NH 3 /SiH 4 ) of.85 under 1.3 Torr. R.F. (radio frequency) frequency and power density for PECVD were 38 khz and 5 mw/cm 2. [27] The curvature of Si wafers after the final SiN film were measured by 633 nm laser line scans along major crystalline axes at room temperature. The wafer radius of curvature is measured and the film stress is determined. The resulting microstructure of Cu vias was characterized using focused ion beam (FIB) cross section as shown in Fig. 1(d) that showed increase in grain size with increase in via diameter, as expected. The maximum Cu grain size in radial direction as computed by image processing software after RTA was 2.2 μm in a 4 μm TSV that increased to 7.8 μm in an 8 μm TSV. Micro X-ray diffraction imaging [28] (g = 224) was used to map the Cu TSVs that indicated no crack formations [28] in adjacent Si (Fig. 1(a)). As a result of the electroplating/thermal annealing/cmp processes, Si that surrounds the Cu TSVs is expected to develop thermo-mechanical stresses associated with the mismatch in the coefficient of thermal expansion (CTE) between Cu and Si, and significant grain growth occurs during thermal annealing. First, TSV Cu is filled by an electroplating process from chemicals with additives at room temperature that typically results in tensile stresses in the asdeposited fine grained Cu via. [15] The stress state of the Cu TSV then becomes largely compressive during the annealing step up to 4 C (CTE of Cu is greater than that of Si) that causes Cu to be extruded up the top surface. The extruded Cu is then polished using chemical-mechanical polishing methods. At elevated temperatures, plasticity in Cu via is expected and can therefore cause stress relaxation in Cu. [29] Therefore, a tensile residual stress will develop in Cu due to the build-up of compressive stress during the thermal annealing step. In addition, the Cu microstructure is changed

3 J. H. Kim et al. 3 Fig. 1. X-ray diffraction imaging (g = 224) map of TSVs of different sizes (a), schematic for opened Cu TSV via (b) and with dielectric overlayers (c). Cross-sectional FIB SEM image as a function of diameter (d). during thermal annealing that results in significant grain growth of the electroplated Cu as shown in Fig. 1(d). During grain growth, excess volume associated with the grain boundaries is removed and this will cause higher tensile stresses upon cooling to room temperature. It should be noted that it is the plasticity and grain growth of Cu that is expected to cause build-up of significant triaxial or hydrostatic tension in the Cu TSV due to the change in volume. [15,25] The volumetric tensile strain imposed in the Cu via is therefore expected to cause stresses to develop in the nearby Si. Using the logical cylindrical coordinate system for this case of cylindrical Cu via, the radial stress σ r is expected to be tensile where as the hoop stress σ θ is expected to be compressive as the Si material is being strained inwards radially towards the Cu via. The expected magnitude of the stresses in Si is expected to be dependent on the via size and this was measured using non-destructive micro-raman methods. 2.2 Micro-Raman measurement Micro-Raman shift in nearby Si was measured as a function of Cu via size at different positions as shown in Fig. 3(a). Among many Ar + laser spectral lines, the 488. nm spectral line [14] with moderate probing depth of ~49 nm was mainly used as the Raman excitation wavelength in this study. [12-14,16] Si results in Raman shift towards the higher wavenumber side (positive shift) for compression and lower wavenumber side (negative shift) for tension from the stress free Raman shift of 52.3 cm 1, respectively. The asmeasured wavenumber resolution for 488. nm excitation is.85 cm 1, but a positive +.1 cm 1 shift or 47 MPa in compression of the Raman signal from stress-free reference Si corresponds to stress sum of 47 MPa. Thus, measurement repeatability, greater than.1 cm 1 is required to make meaningful stress distribution analyses of Si nearby TSVs. All measurements were scanned along <11> direction of the TSVs with 4-8 μm TSV Cu samples. Raman shift values of measured spectra were used to estimate the thermally induced residual stress distribution near the TSVs as a function of distance relative to the center of the Cu TSV at various steps within the processing. Raman spectroscopy typically is performed in a backscattering configuration, and the longitudinal optical (LO) mode is used to determine the Raman shift in

4 4 J. H. Kim et al. frequency. For the Cu TSV in Si, the near-surface stress in Si is approximately biaxial, where σ r, σ θ are radial and circumferential stresses in Si. The sum stress, σ r + σ θ, is proportional to the Raman frequency shift, and the proportionality or sensitivity factor is calibrated using high resolution XRD measurements on biaxially stressed SiGe film on silicon wafer. [2,3] The resulting conversion equation is as follows: σ r ( rz, ) D/2 2π Eε T D ( υ) 2r Eε = T 2π ( 1 υ) υ 3z( R 2 z 2 ) cos 2 β R 2 + Rz R 5 z ( 1 2υ)sin 2 β R 2 + Rz R 3 ρdρdθ (2) σ r + σ θ ( MPa) = 47Δω 3 ( cm 1 ) 2.3 Finite Element Modeling using TCAD Technology computer-aided design (TCAD) software (Synopsys, Inc.) was used for FEM analysis of the TSVs. [31,32] Thermo-mechanical modelling of the Cu TSVs in a Si substrate, using FEM, has proven to be effective in determining the stress distribution in Cu and Si for both reliability and effects on mobility. The input to this elastic modelling consisted of three different materials (Cu, SiO 2, and Si) in which parameters were the CTE, Young s modulus elastic constants, and Poisson s ratio as shown in Table 1. Here, anisotropic constants for Si and elastic constant for Cu were used for TCAD simulations. Cu is assumed to be isotropic and stiffness (C ij ) for Si is taken from work by Hopcroft et al. [33] Since the Raman signal penetrates up to 49 nm from the wafer surface, the stress components are extracted from 49 nm below the wafer surface. A thermal process of cooling from a 4 C down to room temperature, ΔT = 4 C, was imposed to examine the trend in elastic stresses in different sized Cu TSV. The contribution from the thin Ta sidewall in between Cu and Si was ignored since the thin Ta layer is expected to have a negligible effect on the Si stress. [2] 3. RESULTS AND DISCUSSION 3.1 Analytical model predictions From the stress sum, the individual components of stresses can be determined by solving a 2D plane-strain solution to the classical Lame problem subjected to thermal load ΔT as explained in the work by Ryu et al. [21,34] Table 1. The material parameter for TCAD simulation [33,34] Material CTE Mismatch (ppm/k) Young s Modulus (GPa) Posisson s ratio Cu SiO Si 2.3 C 11 : C 12 : 63.9 C 44 : (1) σ θ ( rz, ) D/2 2π σ z ( rz, ) σ rz ( rz, ) Eε T D ( υ) 2r Eε = T π( 1 υ) 1 2υ 3z( R 2 z 2 ) sin 2 β R 2 + zr R z ( 1 2υ)cos 2 β + zr R 3 R 2 Eε = T ( υ) 1 Eε = T ( 1 υ) 2π + 2π D/2 D/2 3z 3 ρdρdθ πR 5 ρdρdθ 3z 2 ( r ρcosθ)ρdρdθ πR 5 where R = z 2 + r 2 + ρ 2 2ρrcosθ, β = tan 1 (( ρcosθ)/ ( r ρcosθ) ) and ε T = ( α Cu α Si ) ΔT is the thermal mismatch strain. Using the analytical solution from above, the expected σ r, σ θ and the sum stress, σ r + σ θ, was evaluated for TSV sizes of 4 μm and 8 μm as shown in Fig. 2. For simplicity, isotropic elastic constants were used and the effects of other thin film materials (TiN, Ta and SiO 2 ) are ignored. Young s modulus of Cu and Si were taken to be E Cu = E Si = 13 GPa, and the Poisson s ratio of ν Cu = ν Si =.28 and the coefficient of thermal expansion mismatch of α = α Cu α Si = 14.7 ppm/ o C were used. For this calculation, T = 4 C, thermal load was imposed. [34] From Fig. 2(a) and 2(b), the radial stress, σ r is tensile and hoop stress σ θ is compressive, as expected, due to the tensile volumetric change in Cu that imposes pulling force on surrounding Si in the radial direction. The radial and hoop stress matches in magnitude to results in near zero sum stress, σ r + σ θ, shown in Fig. 2(c), except near the Cu/Si interface where the σ θ becomes greater than σ r to result in negative sum stress. For the two cases of 4 μm and 8 μm Cu via, the larger sized via is expected to cause higher σ r, σ θ and therefore higher sum stress, σ r + σ θ. 3.2 Micro-Raman analysis The micro-raman frequency shift as a function of TSV diameter is shown in Fig. 3(a) and Eq. (1) was used to convert the micro-raman frequency shift to the sum stress. (3) (4) (5)

5 J. H. Kim et al. 5 The compressive sum stress in nearby Si is the highest at the Cu/Si interface and decays asymptotically with increasing distance away from the TSV in the <11> directions, as expected. Additionally, one can clearly observe that the largest Cu via size of 8 μm had the highest max stress sum in Si of 88.7 MPa in compression and the smallest via of 4 μm had significantly lower max stress sum of 21 MPa in compression. The trend of increase in the stress sum for Cu TSV with larger diameter is in agreement with previous micro-raman studies of larger sized Cu vias (5-4 μm in depth of 6 μm).[13,16,2,21] The cause for higher stresses in larger sized TSVs as shown in the micro-raman data in Fig. 3(b) can be explained with respect grain growth. The maximum stress sum, σr + σθ, in Si determined from micro-raman is plotted together with the average grain size of Cu in Fig. 3(d) that clearly indicates that larger grain sizes due more removal of excess volume associated with grain boundaries during thermal annealing step causes more tensile volumetric strain in the Cu TSV to result in higher sum stresses in in adjacent Si. Since the as-deposited Cu via is taken from room temperature to 4 C then back to 4 C, no thermal stresses are expected; however, the Cu does result in significant grain growth as discussed above that in turn causes larger tensile radial stress and compressive hoop stress to develop in nearby Si. Other than the grain growth effect, larger sized Cu via with less contribution from the Cu/ Si interface is expected to be more effective in straining the nearby Si than smaller sized Cu via thus leading to higher stresses in Si near larger sized Cu vias. These factors therefore both contribute to the size dependency in the measured stress sum in Si nearby different sized Cu TSVs. Fig. 2. The model calculation of the stress sum that is measured in micro-raman spectroscopy and the resolved, individual component stress (a), (b) and stress sum (c), radial (σr) + circumferential stresses (σθ) for a 4 µm and 8 µm Cu vias by semianalytical calculation. 3.3 Finite element modeling for size dependency in Si stresses In order to confirm the experimentally determined trend of increasing Si stresses with increase in the TSV diameter, finite element simulations using TCAD were performed for the open, isolated Cu TSVs (without SiO2/TiN overlayers) with diameters of 4 μm and 8 μm. Since the Cu via is expected to be relaxed at elevated temperatures and develop tensile stress when cooled to room temperature, thermomechanical modeling of the stress development in Si was analyzed for the case of cooling from 4 C to 25 C, ie T = 4 C and compared with the experimental trend in stresses for TSVs in the range of 4-8 μm. The top view of the in-plane stress mapping (σxx, σyy) is shown in Fig. 4 that confirmed higher tensile radial stresses and compressive hoop stresses in Si for larger sized 8 μm Cu TSVs. Although the magnitude of the stresses from the simulations were higher as a result of assuming elastic only deformations, the trend in stresses with varying via sizes can be compared with that of the experimental micro-raman measurements from

6 6 J. H. Kim et al. Fig. 3. The Raman shift (a) and the corresponding local Si stresses (b) as a function of measurement location for different sized Cu vias. (c) Max stress sum, σr + σθ, in Si measured from micro-raman is plotted against the average radial grain size(d). in Fig. 3(b) and 3(c). The results from FEM analysis showed a linear relationship of increasing stress sum, σr + σθ, with increasing via size of 4-8 μm, as expected (Fig. 3(b) and 3(c)). In comparing the simulation results to the microraman experimental data, a similar trend of increasing stress with via size was found as shown in Fig. 4(e), although experimental results deviated from linear relationship, which is expected since the simulation does not account for plasticity or grain growth of Cu. 3.4 Keep-Out-Zone The keep-out-zone (KOZ), which is defined by the region, where the stress-induced mobility variation of Si exceeds 5%, was determined based on the TCAD simulations as shown in Fig. 4(e). Since micro-raman measurements are for the stress sum σr + σθ and the individual stress components are not known. However, one can estimate the KOZ distance by defining the distance away from the Cu/Si interface in which the stress sum σr + σθ goes to zero. The plots for the KOZ equivalent from micro-raman results are shown together with the KOZ calculated from the TCAD simulations in Fig. 4(e). Although there is a difference in the magnitude of the KOZ, the trend is similar between the KOZ determined from TCAD simulations and the KOZ equivalent determined from the micro-raman results in that KOZ increases with increase in the via diameter. The KOZ is expected to be consistently lower for the micro-raman based estimation due to the plasticity induced relaxation in Cu that in turn lowers the stresses in adjacent Si; TCAD simulations, however, were for elastic deformation that results in higher stresses in Cu and adjacent Si. TCAD simulations are useful for simple estimation of the nearby stresses for TSVs, but the micro-raman based non-destructive characterization tool can more accurately provide the KOZ estimation that accounts for plastic relaxation of Cu to ensure device reliability. 3.5 Effect of SiN overlayer on the Si stresses Results presented thus far are for open Cu TSV structure, but typical Cu TSV integration requires deposition of overlayers consisting of SiO2 and SiN multilayers before the final metallization process as indicated in the schematic shown in Fig. 1(b). During the deposition steps, repeated RTA thermal cycles (>11 cycles) cause stresses in Cu and nearby Si. To gain insights into the effects of repetitive

7 J. H. Kim et al. 7 Fig. 5. Local Si stress distribution along the <11> direction calculated from micro-raman line scan (a) of 8 µm diameter Cu TSVs with (red open circle) and without (black open square) dielectric overlayers, schematic for opened Cu TSV wafer (b) and capped Cu TSV wafer (c). Fig D maps of normal stresses (σ xx, σ yy) TCAD simulation for a 4 µm (a) and 8 µm (c) Cu vias and the corresponding outline of KOZ for 4 µm (b) and 8 µm (d) via. (e) Comparison of KOZ based on TCAD simulations and micro-raman characterization plotted against Cu via size showing a similar trend. thermal cycling on stress evolution of Si adjacent to Cu TSV, micro-raman measurements were performed on 8 μm Cu TSV with the dielectric layers that are deposited at 4 C and cooled to room temperature. Local Si stresses calculated from the micro-raman measurements as a function of distance from the center for 8 μm Cu TSV with and without dielectric overlayers are shown in Fig. 5(a). The Si wafer with multilayered dielectric films on top of the Cu TSVs which were thermally cycled between 25 C to 4 C multiple times surprisingly showed the reversed sign of stress sum, σ r + σ θ. The stress sum was now tensile after the deposition of the nitride layer due the compressive stress buildup in the nitride layer as explained further below. The cause for the inversion of stress sum, σ r + σ θ, in Si from compressive to tensile stress after multilayered dielectric film deposition is presumably due to the development of compressive stress in the SiN layer that will impose biaxial tensile strain in the underlying Si. The cause for the compressive stress in SiN has been reported previously, where the process of using PECVD reactor at 4 C places SiN film in a compressive stress due to densification of the film during ion bombardment as reported in the work by Mackenzie et al. [27] Measurement of the global warpage after SiN film deposition showed convex bow downward with R = 28.7 m, which is consistent with development of compressive stress in the SiN overlayers. As a result, tensile stress is induced in the Si below the SiN/SiO 2 overlayers. The application of global tensile stress in Si therefore counteracts the increase in compressive hoop stress at the Cu/Si interface to result in tensile stress sum, σ r + σ θ. 3.6 Discussion TCAD simulations are useful for simple estimation of the nearby stresses for TSVs. In the simulation, the physical properties of bulk Cu and bulk Si are assumed to be substantially the same in micrometer scale structures. The effects of Cu EP chemistry, Cu grain growth, Cu grain orientation and difference in thermal cycles and thermal history along process integration on resulting stress in Si near Cu TSVs are neglected. We often learned that the TCAD simulation results are not necessarily in good agreement with experimental results because the experimental variables are much more complex than the simple and ideal assumption used in the simulation. Micro-Raman data were

8 8 J. H. Kim et al. measured from the actual Si wafers with Cu TSVs. We do not need to assume the physical properties of micrometer scale structures. We simply analyze the experimental results as a function of TSV diameter, thermal cycles during various steps of thin film deposition. Thus the micro-raman based non-destructive characterization tool can more accurately provide the KOZ estimation that accounts for plastic relaxation of Cu to ensure device reliability. It is useful to understand the trends of KOZ as a function of TSV diameter using the TCAD simulation under very simple assumptions. However, it is even more important to experimentally measure the true influence of TSV diameters and process variables on Si stress and KOZ. By comparing the TCAD simulation results and micro-raman measurement results, we can gain additional insights into requirements towards successful design of Cu TSV structures, Cu EP chemistry and thermal cycles along the Cu process integration. The results of this study not only provides scientific knowledge of the mechanisms responsible for size dependency in Si stresses as well as inversion of Si stress with the deposition of the nitride overlayers, but the suggested keep off zones are expected to serve as a useful design guidelines for the industry. 4. CONCLUSIONS In this study, the effects of varying the diameter of Cu TSVs on the stress distribution in the surrounding Si, with and without repetitive thermal cycling, were studied using micro-raman spectroscopy. Experimental results were compared with elastic FEM analysis using TCAD simulation and obtained good agreement in trend. The local Si stresses were the highest for largest Cu via and the compressive stress sum, σ r + σ θ, was shown to decay with distance away from the via, as expected. The KOZ was determined based on micro-raman that indicated KOZ 2.5 to 6. μm for via sizes of 4 μm, 8 μm, respectively that was comparable but smaller than the KOZ based on elastic TCAD simulations. The results from this study are expected to serve as a guideline in designing and characterizing the future Cu TSVs in 3D integrated architecturing; currently 4-8 μm diameter Cu TSV arrays are being developed for HBM devices utilizing < 2 nm technology. As demonstrated in this study, smaller Cu TSVs have advantages in terms of smaller stress variations in Si as well as making use of smaller volume of the Cu via although one should also engineer the processing carefully to avoid void inclusions and adhesion issues between small Cu vias. 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