Logic Synthesis. Late Policies. Wire Gauge. Schematics & Wiring

Transcription

1 Late Policies Logic Synthesis Primitive logic gates, universal gates Truth tables and sum-of-products Logic simplification Karnaugh Maps, Quine-Mcluskey General implementation techniques: muxes and look-up tables (LUTs) Lab check-offs sign-up on checkoff queue in lab FIFO during staffed lab hours. Please don t assume that you can wait until the last minute! No check-offs on Friday or Saturday Lab grade heckoff + Verilog grade (equal weighting) On-time check-off: 2%/day late penalty (no penalty for Friday or Saturday) Max penalty 8% reduction. ll labs must be checked off before you can start your final project. We ve learned that if you re struggling with the labs, the final project won t go very well. Lpset must be submitted on time. Reminder: Lab # due this Thursday! 6. Fall 26 Lecture 2 6. Fall 26 Lecture 2 2 Schematics & Wiring I power supply connections generally not drawn. ll integrated circuits need power! Use standard color coded wires to avoid confusion. red: positive black: ground or common reference point Other colors: signals ircuit flow, signal flow left to right Higher voltage on top, ground negative voltage on bottom Neat wiring helps in debugging! Wire Gauge Wire gauge: diameter is inversely proportional to the wire gauge number. Diameter increases as the wire gauge decreases. 2,,,, (3/) up to 7/. Resistance 22 gauge.254 in 6 ohm/ feet 2 gauge.8 in.5 ohm/ feet High voltage used to reduce loss cm cube of copper has a resistance of.68 micro ohm (resistance of copper wire scales linearly : length/area) 6. Fall Fall 26 4

2 MOS Forever? * * Intel 6. Fall 26 Lecture Fall 26 Lecture 2 6 Timing Specifications Propagation delay (t PD ):n upper bound on the delay from valid inputs to valid outputs (aka t PD,MX ) V IN ontamination Delay an optional, additional timing spec ontamination delay(t D ): lower bound on the delay from invalid inputs to invalid outputs (aka t PD,MIN ) V IH V IN V IH Do we really need t D? V IL V OUT V OH < t PD < tpd Design goal: minimize propagation delay V IL V OUT V OH > t D > t D Usually not it ll be important when we design circuits with registers (coming soon!) V OL V OL If t D is not specified, safe to assume it s. 6. Fall 26 Lecture Fall 26 Lecture 2 8

3 The ombinational ontract Functional Specifications t PD propagation delay t D contamination delay Must be > t D input input input Output if at least 2 out of 3 of my inputs are a. Otherwise, output. I will generate a valid output in no more than 2 minutes after seeing valid inputs output Y Y 3 binary inputs so rows in our truth table Note: Must be < t PD. No Promises during 2. Default (conservative) spec: t D n concise, unambiguous technique for giving the functional specification of a combinational device is to use a truth table to specify the output value for each possible combination of input values (N binary inputs -> 2 N possible combinations of input values). 6. Fall 26 Lecture Fall 26 Lecture 2 Here s a Design pproach S-O-P uilding locks Y -it s systematic! -it works! -it s easy! -are we done yet???. Write out our functional spec as a truth table 2. Write down a oolean expression with terms covering each in the output: Y This approach creates equations of a particular form called SUM-OF-PRODUTS Sum (+): ORs Products ( ): NDs INVERTER: ND: OR: ubble indicates inversion Z Z Z 6. Fall 26 Lecture 2 6. Fall 26 Lecture 2 2

4 Straightforward Synthesis Y We can use SUM-OF-PRODUTS to implement any logic function. Only need 3 gate types: INVERTER, ND, OR Propagation delay: 3 levels of logic No more than 3 gate delays assuming gates with an arbitrary number of inputs. ut, in general, we ll only be able to use gates with a bounded number of inputs (bound is ~4 for most logic families). 6. Fall 26 Lecture 2 3 NDs and ORs with > 2 inputs hain: Propagation delay increases linearly with number of inputs D D Which one should I use? Tree: Propagation delay increases logarithmically with number of inputs 6. Fall 26 Lecture 2 4 SOP w/ 2-input gates Previous example restricted to 2-input gates: Y More uilding locks Z NND (not ND) NOR (not OR) Z MOS gates are naturally inverting so we want to use NNDs and NORs in MOS designs INV ND2 OR2 t PD 8ps 5ps 8ps ps 3ps 3ps t D Using the timing specs given to the left, what are t PD and t D for this combinational circuit? Hint: to find overall t PD we need to find max t PD considering all paths from inputs to outputs. XOR (exclusive OR) Z XOR is very useful when implementing parity and arithmetic logic. lso used as a programmable inverter : if, Z; if, Z~ Wide fan-in XORs can be created with chains or trees of 2-input XORs. 6. Fall 26 Lecture Fall 26 Lecture 2 6

5 NND NOR Internals Y Y Universal uilding locks NNDs and NORs are universal: ny logic function can be implemented using only NNDs (or, equivalently, NORs). Note that chaining/treeing technique doesn t work directly for creating wide fan-in NND or NOR gates. ut wide fan-in gates can be created with trees involving both NNDs, NORs and inverters. 6. Fall 26 Lecture Fall 26 Lecture 2 8 SOP with NND/NOR When designing with NNDs and NORs one often makes use of De Morgan s laws: NND form: NOR form: So the following SOP circuits are all equivalent (note the use of De Morgan-ized symbols to make the inversions less confusing): De Morgan-ized NND symbol De Morgan-ized NOR symbol De Morgan-ized Inverter Logic Simplification an we implement the same function with fewer gates? efore trying we ll add a few more tricks in our bag. OOLEN LGER: OR rules: ND rules: ommutative: ssociative: Distributive: omplements: bsorption: De Morgan s Law: Reduction: a a a a a a a a a a a a a b b a a b b a (a b) c a (b c) (a b) c a (b c) a (b c) a b a c a b c (a b) (a c) a a a a a a b a a a b a b a (a b) a a (a b) a b a b a b a b a b a b a b b (a b) (a b) b ND/OR form NND/NND form NOR/NOR form This will be handy in Lab since you ll be able to use just 74 s to implement your circuit! ll these extra inverters may seem less than ideal but often the buffering they provide will reduce the capacitive load on the inputs and increase the output drive. 6. Fall 26 Lecture 2 9 Key to simplification: equations that match the pattern of the LHS (where b might be any expression) tell us that when b is true, the value of a doesn t matter. So a can be eliminated from the equation, getting rid of two 2-input NDs and one 2-input OR. 6. Fall 26 Lecture 2 2

6 oolean Minimization: n lgebraic pproach Lets simplify the equation from slide #3: Y Using the identity For any expression α and variable : Y Y The tricky part: some terms participate in more than one reduction so can t do the algebraic steps one at a time! 6. Fall 26 Lecture 2 2 Karnaugh Maps: Geometric pproach K-Map: a truth table arranged so that terms which differ by exactly one variable are adjacent to one another so we can see potential reductions easily. Y Here s the layout of a 3-variable K-map filled in with the values from our truth table: Y It s cyclic. The left edge is adjacent to the right edge. It s really just a flattened out cube. Why did he shade that row Gray? 6. Fall 26 Lecture 2 22 Here s a 4-variable K-map: D On to Hyperspace Z gain it s cyclic. The left edge is adjacent to the right edge, and the top is adjacent to the bottom. We run out of steam at 4 variables K-maps are hard to draw and use in three dimensions (5 or 6 variables) and we re not equipped to use higher dimensions (> 6 variables)! 6. Fall 26 Lecture 2 23 Finding Subcubes We can identify clusters of irrelevent variables by circling adjacent subcubes of s. subcube is just a lower dimensional cube. Z Y D Three 2x subcubes Three 2x2 subcubes The best strategy is generally a greedy one. - ircle the largest N-dimensional subcube (2 N adjacent s) 4x4, 4x2, 4x, 2x2, 2x, x - ontinue circling the largest remaining subcubes (even if they overlap previous ones) - ircle smaller and smaller subcubes until no s are left. 6. Fall 26 Lecture 2 24

7 Write Down Equations Write down a product term for the portion of each cluster/subcube that is invariant. You only need to include enough terms so that all the s are covered. Result: a minimal sum of products expression for the truth table. D Z Y Z D We re done! 6. Fall 26 Lecture 2 25 Two-Level oolean Minimization Two-level oolean minimization is used to find a sum-of-products representation for a multiple-output oolean function that is optimum according to a given cost function. The typical cost functions used are the number of product terms in a two-level realization, the number of literals, or a combination of both. The two steps in two-level oolean minimization are: Generation of the set of prime product-terms for a given function. Selection of a minimum set of prime terms to implement the function. We will briefly describe the Quine-Mcluskey method which was the first algorithmic method proposed for two-level minimization and which follows the two steps outlined above. State-of-the-art logic minimization algorithms are all based on the Quine-Mcluskey method and also follow the two steps above. 6. Fall 26 Lecture 2 26 Prime Term Generation Start by expressing your oolean function using - terms (product terms with no don t care care entries). For compactness the table for example 4-input, - output function F(w,x,y,z) shown to the right includes only entries where the output of the function is and we ve labeled each entry with it s decimal equivalent. F f(w,x,y,z) W X Y Z label Look for pairs of -terms that differ in only one bit position and merge them in a -term (i.e., a term that has exactly one entry). Next -terms are examined in pairs to see if the can be merged into 2-terms, etc. Mark k-terms that get merged into (k+) terms so we can discard them later. -terms:, 8 - [] 2-terms: 8, 9,, --[D] 5, 7 - [],,4,5 --[E] 7,5 - [] 8, 9-8, - 3-terms: none! 9, - Example due to, - Label unmerged terms: Srini Devadas,4 - these terms are prime!,5-4,5-6. Fall 26 Lecture 2 27 Prime Term Table n X in the prime term table in row R and column K signifies that the - term corresponding to row R is contained by the prime corresponding to column K. Goal: select the minimum set of primes (columns) such that there is at least one X in every row. This is the classical minimum covering problem. D E X..... X.... X X.. X.. X.... X.... X X... X X.... X.. X. X is essential - is essential - D is essential -- E is essential -- Each row with a single X signifies an essential prime term since any prime implementation will have to include that prime term because the corresponding -term is not contained in any other prime. In this example the essential primes cover all the -terms. F f(w,x,y,z) XYZ + WXZ + WX + WY 6. Fall 26 Lecture 2 28

8 Logic that defies SOP simplification Logic Synthesis Using MUXes i S o o Full dder F S The sum S doesn t have a simple sum-of-products implementation even though it can be implemented using only two 2-input XOR gates. i S / O / S i O schematic If is then copy to Y, otherwise copy to Y 2-input Multiplexer Y Y Gate symbol Truth Table Y 4-input Mux implemented as a tree S Y S I I I 2 I 3 S S S 6. Fall 26 Lecture Fall 26 Lecture 2 3 Systematic Implementation of ombinational Logic Systematic Implementation of ombinational Logic onsider implementation of some arbitrary oolean function, F(,)... using a MULTIPLEXER as the only circuit element: Y,, in Full-dder arry Out Logic out Same function as on previous slide, but this time let s use a 4-input mux Y in in, Full-dder arry Out Logic 2 3 out 6. Fall 26 Lecture Fall 26 Lecture 2 32

9 Xilinx Virtex II FPG Virtex II L X2V6: 957 pins, 684 IOs L array: 88 cols x 96/col 8448 Ls 8Kbit RMs 6 cols x 24/col 44 RMs 2.5Mbits 8x8 multipliers 6 cols x 24/col 44 multipliers 6. Fall 26 Lecture 2 Figures from Xilinx Virtex II datasheet 33 6 bits of RM which can be configured as a 6x single- or dual-port RM, a 6-bit shift register, or a 6-location lookup table Figures from Xilinx Virtex II datasheet 6. Fall 26 Lecture 2 34 Virtex II Slice Schematic Virtex II Sum-of-products Figures from Xilinx Virtex II datasheet Figures from Xilinx Virtex II datasheet 6. Fall 26 Lecture Fall 26 Lecture 2 36

10 Spartan 6 FPG Spartan 6 SliceM Schematic Figures from Xilinx Spartan 6 L datasheet 6. Fall 26 Lecture Fall 26 Lecture 2 38 Oscilloscope Oscilloscope ontrols ursor controls Menu driven soft key/buttons uto Set, soft menu keys Trigger channel, slope, Level Input, D coupling, x probe, khz calibration source, probe calibration, bandwidth filter Signal measurement time, frequency, voltage cursors single sweep Image capture 6. Fall Fall 26 4