GRAPHENE, which is a monolayer of carbon atoms

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1 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY Graphene Nanoribbon FETs: Technology Exploration for Performance and Reliability Mihir R. Choudhury, Student Member, IEEE, Youngki Yoon, Member, IEEE, JingGuo, Member, IEEE, and Kartik Mohanram, Member, IEEE Abstract Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-cmos nanoelectronics due to their excellent carrier-transport properties and potential for largescale processing and fabrication. This paper combines atomistic quantum-transport modeling with circuit simulation to perform technology exploration for GNRFET circuits. Results indicate that GNRFETs offer significant gains over scaled CMOS at the 22-, 32-, and 45-nm nodes, with over improvement in the energydelay product at comparable operating points. A quantitative study of the effects of variations and defects on the performance and reliability of GNRFET circuits is also presented. Simulation results indicate that whereas GNRFET circuits promise higher performance, lower energy consumption, and comparable reliability at similar operating points to scaled CMOS circuits, they are more susceptible to variations and defects. These results motivate significant engineering, modeling, and simulation challenges facing the device and computer-aided design (CAD) communities involved in graphene electronics research. Index Terms Circuit design, defects, energy, energy-delay product, field-effect transistor, graphene, inverter, latch, nanoribbons, performance, quantum transport, reliability, ring oscillator, variability. I. INTRODUCTION GRAPHENE, which is a monolayer of carbon atoms packed into a 2-D honeycomb lattice, has emerged as a promising candidate material for beyond-cmos nanoelectronics. Graphene-based devices offer high mobility for ballistic transport, high carrier velocity for fast switching, monolayer thin body for optimum electrostatic scaling, and excellent thermal conductivity [1] [6]. The potential to produce wafer-scale graphene films with full planar processing for devices promises high integration potential with conventional CMOS fabrication processes, which is a significant advantage over carbon nanotubes (CNTs) [6]. Manuscript received October 18, 2009; revised June 2, 2010; accepted July 19, Date of publication September 9, 2010; date of current version July 8, This work was supported in part by the National Science Foundation under Grant CCF and Grant CCF , and in part by the Office of Naval Research. The review of this paper was arranged by Associate Editor R. Lake. M. R. Choudhury and K. Mohanram are with the Department of Electrical and Computer Engineering, Rice University, Houston, TX USA ( mihir@rice.edu; kmram@rice.edu). Y. Yoon was with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL USA. He is now with the University of California, Berkeley, CA USA ( ykyoon@ufl.edu). J. Guo is with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL USA ( guoj@ufl.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TNANO Although 2-D graphene is a zero band-gap semi-metal, a band-gap opens when a FET channel is fabricated on a nanometer-wide graphene nanoribbon (GNR) [6] [9]. In general, the band-gap of a GNR is inversely proportional to its width, and width confinement down to the sub-10-nm scale is essential to open a band-gap that is sufficient for room temperature transistor operation. Unlike CNTs, which are mixtures of metallic and semiconducting materials, recent samples of chemically derived sub-10-nm GNRs have exhibited all semiconducting behavior [9], generating considerable excitement for transistor applications. The two main types of GNRs, with the edges of the ribbons assumed passivated by hydrogen atoms, are armchairedge and zigzag-edge GNRs (AGNRs and ZGNRs). ZGNRs are predicted to be metallic by a simple tight-binding model, but a band-gap exists in more advanced, spin-unrestricted simulations [10]. For digital circuits applications, the focus has been on using AGNRs as the channel material. AGNRs have an electronic structure that is closely related to that of zigzag CNTs. The band-gap in AGNRs originates from quantum confinement, and edge effects play a critical role [10]. This paper first provides an overview of Schottky barrier (SB) GNRFETs with intrinsic AGNR channels (GNRFETs henceforth, unless specified otherwise). Unlike traditional MOSFETs, SBFETs use metal or metal silicide contacts at the source and drain ends, leading to the formation of SBs at these contacts. In SBFETs, the gate modulates the quantum tunneling current through the SB [11]. Recently fabricated GNRFETs with channel lengths of the order of 200 nm delivered about 21% of the ballistic current at V D = 1 V, and about 4.5% of the ballistic current at low V D < 0.1 V [12]. Clearly, these are preliminary devices, and it would be natural to expect further advances such as the integration of ultrathin high-κ dielectrics [13] and aggressive channel length scaling to move the performance of these devices closer to the ballistic limit, with switching speeds, I ON /I OFF, and sub-threshold slope that is competitive with scaled CMOS. Although most discussions in this paper focus on SB-type GNRFETs [14], [15], simulation studies of MOSFET-type GNRFETs with doped reservoirs have also been reported in [16] [18]. In [19] and [20], SB-type GNRFETs were also compared to MOSFET-type GNRFETs. There is consensus that in ideal devices, MOSFET-type GNRFETs show better device characteristics over SB-type GNRFETs: larger maximum achievable I ON /I OFF, larger I ON, larger transconductance, and better saturation behavior. Further, this paper presents extensive results on technology exploration for GNRFET circuits. It couples atomistic quantum X/$ IEEE

2 728 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011 transport modeling in intrinsic GNRFETs with a circuit simulator that includes parasitics and nonidealities that are necessary to capture extrinsic effects in fabricated GNRFETs. At the device level, GNRFETs are simulated by self-consistently solving an atomistic quantum transport equation based on the nonequilibrium Green s function (NEGF) formalism with the 3-D Poisson s equation. These rigorous simulations provide I V and Q V data for intrinsic GNRFETs, which are integrated into a circuit-level simulation framework based on lookup tables for technology exploration of GNRFET circuits. The simulator is used to study the delay, power, energy, and noise margins of representative GNRFET circuits including inverters, ring oscillators, and latches. Results indicate that GNRFETs offer significant gains over scaled CMOS at the 22-, 32-, and 45-nm nodes, with over improvement in the energy-delay product (EDP) at comparable operating points. Significant technical challenges, however, remain to be met. Due to the atomically thin and nanometer-wide geometries of GNRs, variability and defects are projected to have a larger impact on circuit performance and reliability in comparison to conventional silicon devices. The framework is extended to perform a quantitative study of the effects of variations and defects in intrinsic GNRFETs on the performance and reliability of GNRFET circuits. Independent variations in GNR width, which is the most common source of variation, and independent charge impurities in the gate oxide, which is the most common source of defects, are considered in this paper. Variation in GNR width affects GNRFET I ON /I OFF nonlinearly, which in turn impacts circuit performance, power, and noise margins. Simulation results indicate that variation in GNR width can increase the delay, static power, and dynamic power of inverters by 6% 77%, 313% 643%, and 37% 215%, respectively, while reducing the noise margin by 27% 80%. Charge impurities affect intrinsic GNRFET characteristics nonlinearly and in an asymmetric manner, depending upon the polarity of the charge. Simulation results indicate that charge impurities can increase the delay, static power, and dynamic power of inverters by 8% 92%, 11% 37%, and 5% 19%, respectively, while reducing the noise margin by 14% 40%. When simultaneous variations in width and charge impurities are considered, variations in width dominate, though the effects are exacerbated by the presence of charge impurities. Latch noise margins and static power also exhibit significant sensitivity to variations and defects, with near-zero noise margins and over 5 increase in static power in the worst case. Low noise margins may result in higher error rates than scaled CMOS, though the redundancy required for error detection and correction as well as the high static power may be offset by the advantages of high density and low power that GNRFETs offer over scaled CMOS. In summary, results show that graphene-based electronics has the potential for smaller, faster, and lower energy switches than scaled CMOS. The results also motivate significant engineering, modeling, and simulation challenges facing the device and computer-aided design (CAD) communities to make the performance and reliability of GNRFETs suitable for large-scale integration. Fig. 1. NEGF formalism for a generic transistor. This paper is an extended version of [21] and is organized as follows. Section II provides a background in quantum simulation of intrinsic GNRFETs. Section III describes technology exploration for GNRFET circuits based on a large-signal circuit model for extrinsic GNRFETs. Sections IV and V discuss how variations and defects impact the performance and reliability of GNRFET circuits. Section VI is a conclusion. II. SIMULATION OF INTRINSIC GNRFETS As devices scale with technology, a powerful quantum transport simulation framework based on the NEGF formalism provides an ideal approach for bottom-up device modeling and simulation [22] for the following reasons: 1) atomistic descriptions of devices can be readily implemented; 2) open boundaries can be rigorously treated; and 3) multiphenomena (e.g., inelastic scattering and light emission) can be modeled. Fig. 1 summarizes the procedure to apply the NEGF approach to a generic transistor. The transistor channel, which can be a piece of silicon, a GNR, a nanowire, or a single molecule, is connected to the source and drain contacts. The gate modulates the conductance of the channel. One first identifies a suitable basis set and derives the Hamiltonian matrix H for the isolated channel. Then, the self-energy matrices Σ 1, Σ 2, and Σ S, which describe how the channel couples to the source contact, the drain contact, and the dissipative processes, respectively, are computed. Then, the retarded Green s function, including selfconsistent electrostatic potential U, is computed as G r (E) =[(E + i0 + )I H U Σ 1 Σ 2 Σ S ] 1. (1) Finally, the physical quantities of interest, such as the charge density and current, are computed from the Green s function. In this paper, the DC characteristics of ballistic GNRFETs are simulated by solving the open-boundary Schrödinger equation using the NEGF formalism in the atomistic p z orbital basis set self-consistently with Poisson s equation. Ballistic transport (no scattering) is assumed, which sets Σ S =0in (1). The superior carrier transport properties of graphene [23] promises ballistic transport for a nanoscale channel. The simulation results establish the device performance at the ballistic limit. Whereas further work is needed to compare theory with experiment as more data for GNRFETs becomes available, it has been demonstrated previously that a CNTFET with a 50-nm-long channel delivers a near ballistic DC current [24]. An ab initio treatment of the metal contacts is not practical for efficient device simulation; therefore, a phenomenological treatment of the metal-semiconductor contacts has been used in this study. The model, which has been used to simulate the metal-

3 CHOUDHURY et al.: GRAPHENE NANORIBBON FETs: TECHNOLOGY EXPLORATION FOR PERFORMANCE AND RELIABILITY 729 Fig. 2. (a) I V characteristics and (b) V T extraction at low V D for ideal N =12GNRFETs. CNT [25] and the metal-gnr contacts [26] earlier, describes the metal-semiconductor contacts by two input parameters. The first parameter is the SB height, which determines the band discontinuity at the metal-semiconductor interface. The second parameter is the density of the metal-induced gap states, which determines the surface Green s function of the metal contact. The model treats the contact at the level of the Tersoff theory for metal-semiconductor contacts [27], [28], and has been validated by experiments for metal-cnt contacts [24]. For a detailed derivation, see [29]. Since the electric field varies in all dimensions for the simulated device structure, the 3-D Poisson s equation is used and numerically solved using the finite-element method (FEM). The FEM is efficient to treat a device with multiple gates because it can easily handle an arbitrary grid for complex geometry. A p z orbital coupling parameter of 2.7 ev is used and the tight-binding model [10] is used for band-gap calculations. The simulations in this paper consider a 15-nm-long AGNR as the channel material, and the GNR width is varied from N =9to N =18, where N denotes GNR index [30]. Double gate geometry is implemented through a 1.5-nm-thick SiO 2 gate insulator (ɛ r = 3.9). The source and drain contacts are metals, and the SB height is equal to half the band-gap of the channel GNR (Φ Bn = Φ Bp = E g /2). The gate modulates the quantum tunneling current through the SB at the source end of the channel, and the device operates as a SBFET [11]. The I V device characteristics for the ideal N = 12 GNRFET for different drain voltages is shown in Fig. 2(a). Ambipolar characteristics due to both electron and hole conduction are clearly seen, and the drain voltage exponentially increases the minimum leakage current. If I ON is divided by the channel width, it is 6300 μa/μm forthen =12GNRFET when V D is 0.5 V. As drain voltage increases, SBFETs show linear behavior in the overall range of gate bias. For example, the drain current and the channel charge for V D = 0.75 V are linearly proportional to V G, whereas those for V D = 0.25 V show exponential behavior in the sub-threshold region. As shown in Fig. 2(a), the I V characteristics exhibit electron conduction at high gate voltages and hole conduction at low gate voltages, with minimum leakage current at V G V D /2. The ambipolar conduction is explained by observing that the device operates as a SBFET. The threshold voltage V T of the GNRFET is obtained using traditional V T extraction methods for MOS devices from the I V data [31]. When a low drain voltage V DS is applied to an n-type GNRFET, the slope of the I V curve at a high gate voltage is said to intersect the V G axis at the threshold voltage V T. This is illustrated for the I V curve in Fig. 2(b), where the V T is approximately 0.3 V. The leakage current at V G =0is large, but the threshold voltage of the FET can be tuned by engineering the gate metal material to shift the I V curves along the x-axis, thereby moving the point with minimum leakage current to V G =0[32]. Note that when the offset is applied to achieve minimum leakage, V T changes by an amount equal to the offset, illustrated by the I V curve for an offset of 0.2 V and a V T of approximately 0.1 V in the same figure. Finally, both n-type and p-type FETs can be achieved on the same GNRFET due to the ambipolar I V characteristics. This has already been experimentally demonstrated in the context of CNTFETs [32], which exhibit ambipolar I V characteristics qualitatively similar to GNRFETs. III. SIMULATION OF GNRFET CIRCUITS A simulator based on table lookup techniques was implemented to simulate circuits built with GNRFETs. The simulator uses the drain current I D (V G,V D ) and channel charge Q(V G,V D ) computed for the intrinsic GNRFET using the quantum-transport simulations described in Section II. These values were used to populate a lookup table at discrete voltage steps of V GS and V DS ranging from 0 to 0.75 V. The intrinsic gate and drain capacitances C GD,i and C GS,i vary with the gate and drain voltages. These values can be computed and stored in the lookup table by differentiating the channel charge w.r.t. V GS and V DS, respectively. Thus, C GD,i = Q/ V DS and C G,i = C GS,i + C GD,i = Q/ V GS, which yields C GS,i = Q/ V GS Q/ V DS. The extrinsic n-type and p-type GNRFETs were modeled by adding the parasitic capacitances and contact resistances around the intrinsic GNR, as shown in Fig. 3(a). Two strategies fabricating very narrow contacts to an individual GNR or fabricating multiple GNRs in an array for a wide contact are currently under investigation in the device community. The

4 730 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011 Fig. 3. (a) Circuit model for GNRFET simulation. (b) EDP, frequency, and SNM contours for a 15-stage ring oscillator. GNRFET considered in this paper is comprised of four equidistant GNRs that form the channel. The pitch refers to the spacing between the neighboring GNRs in the GNRFET channel, and usually ranges from the GNR width to 1 μm as annotated in the figure. In this paper, we assume that an individual GNR channel has a contact width of 10 nm, and that this equals the pitch in the GNR array. Thus, a GNRFET with four GNRs has a total contact width of 40 nm. The current in the GNRFET is four times the current in the individual GNR channel, and the parasitics are also four times that for an individual GNR. Thus, the parasitic junction capacitances C GD,e and C GS,e are given by af/nm times the total GNRFET contact width of 40 nm. It is assumed that the substrate is thick enough and that the extrinsic parasitic capacitances C DB,e and C SB,e are negligible. The contact capacitance at the device terminals and interconnect capacitance are assumed negligible and are not considered in this paper. The contact resistances were assumed to range from 1 to 100 kω, with a nominal value of 10 kω. The SB contact between the metal source/drain electrodes and the GNR channel, which is modulated by the gate voltage, is modeled in the NEGF quantum-transport calculation. The approach to modeling the SB contact in this study is standard, as used by many groups, e.g., [19], [33]. The parasitic resistance component in Fig. 3(a) accounts for additional parasitic resistance, such as the diffusion resistance of the thin metal films. The parasitic capacitances were also determined using a 2-D capacitance model. The values used in this paper for the resistive and capacitive parasitics are in the ballpark as characterized by earlier experiments. The simulation model has been calibrated to experimental data with very good agreement in the context of CNTFETs [24]. A. Technology Exploration The tradeoff between delay, energy, and noise robustness can be explored for different values of V DD and V T for GNRFET circuits. We choose a 15-stage ring oscillator, where each inverter drives a fanout-of-4 load as the representative circuit for this study. The EDP has been widely used to explore the tradeoffs between delay and power in CMOS circuits. The EDP captures how delay can be reduced by increasing V DD and reducing V T, dynamic power can be reduced by lowering V DD, and static power can be reduced by increasing V T. The EDP attains a minimum at an intermediate value of V T and V DD, and can be used for technology exploration of GNRFET circuits. Fig. 3(b) presents the EDP contours (solid curves) for the ring oscillator. The optimum value of the EDP is achieved at V DD = 0.15 V and V T = 0.08 V, and is conventionally the preferred operating point for the circuit. However, this optimum corresponds to a low frequency of operation. By plotting the frequency of operation that can be achieved for a 15-stage ring oscillator for each V DD V T combination, it is possible to explore performance-energy tradeoffs further using the following observation. For a given desired frequency of operation, the optimum EDP curve is tangential to the frequency curve. For example, for a desired frequency of 3 GHz for the 15-stage ring oscillator, point A in Fig. 3(b) suggests that the minimum EDP is attained at V DD = 0.3 V and V T = 0.06 V. Reliability can be introduced as an additional figure-of-merit to determine optimum EDP for a desired frequency of operation by drawing the static noise margin (SNM) contours for an inverter. These contours represent points of equal SNM for each V DD V T combination. Point A in the figure lies on the 0.1-V SNM contour, which is unacceptable for most applications.

5 CHOUDHURY et al.: GRAPHENE NANORIBBON FETs: TECHNOLOGY EXPLORATION FOR PERFORMANCE AND RELIABILITY 731 TABLE I DELAY,EDP,AND SNMS FORGNRFETS AND CMOS TABLE II FREQUENCY AND EDP VERSUS PITCH AND NUMBER OF GNRS When a desired SNM is identified, the intersection of the desired frequency and SNM contours identifies a region for reliable operation that achieves desired performance. The intersection of the two curves determines the point of minimum EDP. For example, for a SNM of 0.15 V at 3 GHz, the optimum V DD V T combination is given by point B with V DD =0.4 V and V T = 0.13 V in Fig. 3(b). This operating point offers a good tradeoff between EDP, performance, and noise. Note that unlike CMOS, increasing V T does not necessarily help tradeoff performance for higher noise robustness in GNRFET circuits. For example, the operating point C with V DD = 0.4 V and V T = 0.23 V has the same EDP and noise margins as point B in the figure. However, the frequency of the ring oscillator for operating point B is 40% greater than that for operating point C, as seen in the figure. Higher V T at C is achieved by decreasing the offset as shown in Fig. 2, which corresponds to operating the ring oscillator at a point other than that of minimum leakage, as explained in Section II. As a result, the resulting potential divider effect within the GNRFET inverter limits noise margins and decreases performance as observed in the figure. Comparison to Scaled CMOS: Table I compares the performance, EDP, and SNM of the 15-stage ring oscillator for GNRFETs and scaled CMOS nodes (simulated using the predictive technology model (PTM) [34]). For all scaled CMOS nodes, V DD = 0.8 V provides the best performance, V DD = 0.4 V consumes the least power, and V DD = 0.6 V provides the best tradeoff between performance and power. For CMOS technology based on the PTM, the intrinsic capacitance of a fanout-of-4 inverter is about one-third of the total capacitance. Hence, the intrinsic capacitance contributes to about 33% of the dynamic power component of EDP. In contrast, for GNRFETs, the values of the intrinsic gate-source and gate-drain capacitances depend on the operating point and range from 6% 8% of the fanout load capacitance for a fanout-of-4 inverter. The contribution of the intrinsic and fanout load capacitances to the EDP also depends on technology-dependent factors, such as source and drain contact resistances. When the contact resistance is small (1 kω), the circuit switches faster and the intrinsic capacitances account for 8% 10% of the dynamic power component of EDP. Similarly, for contact resistance of 10 kω and 100 kω, the intrinsic capacitances account for roughly 15% 18% and 22% 25% of EDP. For CMOS technology based on the PTM, at V DD = 0.6 V, the leakage power dissipated when gate-source voltage is zero is a negligible fraction of the total power dissipation, and hence, a negligible fraction of the EDP (about 0.004%). For GNRFET technology, since our framework does not consider tunneling currents, no leakage power is dissipated when the gate-source voltage is zero. A striking difference between the scaled CMOS nodes and GNRFETs is that the optimum EDP for scaled CMOS is higher than the EDP for GNRFETs at operating point B. GNRFETs have lower noise margins in comparison to scaled CMOS and are also more susceptible to variability and defects as discussed in the remainder of this paper. However, the significant difference in EDPs leaves enough headroom for robust design with GNRFETs to overcome these challenges. Design Parameters (Pitch and Number of GNRs): Table II shows the performance and EDP of a 15-stage ring oscillator for different values of pitch and for different number of GNRs in the array of a GNRFET device. Table II shows that increasing the pitch decreases the frequency of the ring oscillator and increases the EDP. This trend is observed because increasing the pitch increases the extrinsic parasitic capacitance within the GNRFET. However, an interesting observation is that for the same pitch, the frequency of the ring oscillator decreases and the EDP increases, as we increase the number of GNRs in the array. This is because the extrinsic capacitance is proportional to the contact width, which is given by the product of the number of GNRs and the pitch. Hence, as the number of GNRs in the array increases, the extrinsic capacitance increases. The drive current of the channel also increases as we increase the number of GNRs in the array. However, the effect of increase in extrinsic capacitance is more dominant, and thus the frequency of the ring oscillator decreases. The screening effect of the GNRs has been neglected in this paper. This is a reasonable assumption for values of pitch used in this paper. However, it has been shown in [35] that screening effect in CNTFETs cannot be neglected for smaller values of pitch. A similar study of screening effect in GNRFETs is necessary and is a potential area of future research. IV. INTRINSIC GNRFETS: VARIATIONS AND DEFECTS Variability and defects are expected to play an important role in graphene electronics in practice. Variability, for example, can come from the difficulty in control of the GNR width or oxide thickness in fabrication. The charge impurity in the gate insulator, lattice vacancy, or edge roughness [36] of GNR may be a defect that results in a large performance variation. Our atomistic NEGF simulation of a wide variety of variability and defect mechanisms have identified the important role of the GNR width variation and the effect of Coulomb charge impurities in graphene, which are the subject of this study. Other defect and variability mechanisms exist and should be explored in future

6 732 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011 Fig. 4. I V characteristics for different GNR widths, where the GNR width is about 1.23 Å times its index, as labeled in the figure. studies, but we expect the effects are qualitatively similar and can be explored by readily extending the bottom-up simulation framework presented here. The occurrence of variation and defect events in the GNR array channel of a GNRFET is modeled and analyzed in two ways. In the first case, it is assumed that only one GNR in the array is subject to a variation, defect, or combination thereof. The total current is given by the sum of the currents in the GNRs, nominal or otherwise. Since the pitch is larger than the gate oxide thickness, an impurity near one GNR has a negligible effect on other GNRs because the impurity charge electric field is screened by the gate. In practice, multiple defects and variability of all GNRs in the array may exist, and this is handled in the second case by assuming that each GNR in the channel experiences the same variation, defect, or combination thereof. The results in this study, therefore, establish lower and upper limits for the effects of variations and defects on GNRFET circuits. Future studies are necessary to address multiple variability and defect effects, but we expect the broader conclusions to remain the same. A. GNR Width Variations The band-gap in AGNRs originates from quantum confinement, and edge effects play a critical role [10]. The band-gap of the semiconducting GNR is, in general, inversely proportional to the GNR width. Since device characteristics are very sensitive to the band-gap of channel material, the width effect is critical to GNRFET performance. GNR width is proportional to the GNR index. GNRs with index values of 9, 12, 15, and 18 are used to study the effect of variations in width. Starting with the minimum GNR index of N = 9, which has a width of 1.1 nm, the index is increased in steps of 3, or equivalently, by an incremental width of 3.7 Å. Fig. 4 illustrates how variability in GNR width affects device I D V G characteristics. The band-gap of the N = 18 GNR is too small to achieve a small leakage current, whereas that of the N = 9 GNR is sufficiently large so that I ON /I OFF is as high as However, the capacitance of a wider GNRFET is large due to the larger surface of the GNR channel. The N = 18 GNRFET has 50% larger intrinsic channel capacitance than the N = 9 GNRFET in the ON state, which can affect performance as discussed in the following section. B. Charge Impurities For SBFETs, the charge impurity may affect device characteristics most severely when it is located close to the source, since the SB between source and GNR is affected. In our simulations, the charge impurity is considered as a fixed external charge in the gate-oxide region, and it plays an important role for self-consistent electrostatic potential. To exaggerate the effects of an impurity, the impurity is placed near the source and at a distance of 0.4 nm from the GNR surface. Both polarities of charges are considered, and the charge magnitude is also varied. Fig. 5(a) shows the severely affected SB due to the charge impurity. The inset in the figure shows the position of the charge impurity in the cross section of the simulated device. A negative charge impurity increases the barrier height and thickness, whereas a positive charge impurity decreases the barrier height and thickness at the source contact. This affects the source drain current and the charge in the channel. With the negative charge impurity of 2q, the electron flow is significantly reduced by the large barrier, and the ON current is a factor of 6 smaller than that in the ideal device. For the device with the +2q positive charge impurity, both OFF and ON currents show a relatively smaller variation from the ideal device compared to that with the 2q negative charge impurity in the n-type operation branch (V G > 0.25 V), as illustrated in Fig. 5(b). V. GNRFET CIRCUITS:VARIATIONS AND DEFECTS In this section, we study the sensitivity of inverter delay, power, and noise robustness to variations in GNR width and charge impurities. The combined effect of variations in GNR width and charge impurities is also studied to identify the worst case combination of width variation and charge impurity on delay, power, and noise margins. As explained in the earlier section, two scenarios are considered: one where the anomaly affects one out of four GNRs in the array, and the second where all four GNRs in the array are similarly affected. The simulations were performed for an inverter with a fanout-of-4 load. The operating point (V DD = 0.4 V and V T = 0.13 V) derived in Section III-A as a good tradeoff point among delay, energy, and noise robustness for the nominal device is used to simulate all the GNRFET circuits in this section. In Tables III and IV, the nominal value of delay is reported in picoseconds, nominal static and dynamic power in microwatt, and nominal noise margin in Volt. All other entries in the table are reported as percentage deviation with respect to the nominal case. A. Width Variations Table III shows the delay, power, and noise margin due to independent variations in GNR width in both the n-type and p-type GNRFETs of an inverter. The nominal inverter has both n-type and p-type GNRFETs composed of four N = 12 GNRs in the array. The delay of an inverter driving a fanout-of-4 load, with nominal n-type and p-type GNRFETs composed of four N = 12 GNRs in the array, is 7.54 ps. The delay increases as

7 CHOUDHURY et al.: GRAPHENE NANORIBBON FETs: TECHNOLOGY EXPLORATION FOR PERFORMANCE AND RELIABILITY 733 Fig. 5. (a) Conduction-band profile of N = 12 GNRs with and without charge impurity. The inset shows the position of the charge impurity in the cross section of the simulated device. (b) I V characteristics for N = 12 GNRs with charge impurities. TABLE III EFFECT OF INDEPENDENT VARIATIONS IN GNR WIDTH IN N-/P-GNRFET CHANNELS ON INVERTER DELAY,POWER, AND SNM TABLE IV EFFECT OF INDEPENDENT CHARGE IMPURITIES IN N-/P-GNRFET CHANNELS ON INVERTER DELAY,POWER, AND SNM the width of the GNR decreases to N = 9 and decreases as the width increases to N = 18. In each entry in the table, the comma separates the first scenario when only one GNR is affected from the second scenario when all four GNRs in the GNRFET array are affected. In the worst case, when one to four GNRs in both the p-type and n-type GNRFETs are N = 9 GNRs, the delay increases by 6% 77%. On the other hand, there is a 12% 30% decrease in the delay of an inverter when one to four GNRs in both the p-type and n-type GNRFETs are N = 18 GNRs. Variations in GNR width significantly impact both static and dynamic power. When one to four GNRs in both the p-type and n-type GNRFETs are N = 9 GNRs, static and dynamic power are reduced by 13% 47% and 8% 38%, respectively. In the worst case, however, static and dynamic power increase by 313% 643% and 27% 217%, respectively. The impact of variations in width on leakage power stands out in this table, since even single GNR variations in the two GNRFETs can increase static power consumption by 3. Finally, it is observed that GNR width variations affect the SNMs of a GNRFET inverter significantly. When the n-type and p-type GNRFETs of an inverter have the same width, the SNM increases with decrease in width due to the increase in inertial delay in the inverter. The noise margin decreases from 0.17 to 0.09 V as the width (of both n-type and p-type GNRFETs) increases from N = 9toN = 18. However, the noise margins degrade further when n-type and p-type GNRFETs have different widths, and reach their worst case deviations when there is maximum mismatch of N = 9 and N = 18 between the n-type and p-type GNRFETs. In this case, the SNM is off by 27% 80% from its nominal value of 0.15 V. B. Charge Impurities Table IV shows the delay, power, and noise margin due to independent charge impurities that affect one to four of the GNRs in both the n-type and p-type GNRFETs of an inverter. Note that a +q charge has the same effect on a p-type GNRFET device as a q charge has on an n-type GNRFET device, and vice versa. The nominal inverter has both n-type and p-type GNRFETs composed of no charge defects on all four GNRs

8 734 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011 TABLE V EFFECT OF INDEPENDENT VARIATIONS AND CHARGE IMPURITIES IN N-/P-GNRFET CHANNELS ON INVERTER DELAY,POWER, AND SNM in the array. The effect of charge impurities is highly asymmetric, with large degradation in delay, power, and noise margin, but only small improvements. Inverter delay is degraded by 8% 92% in the presence of simultaneous 2q and +2q charge impurities in one to four n-type GNRFETs and p-type GNRFETs, respectively. However, the maximum improvement in delay observed due to the presence of simultaneous +q and q charge impurities in one to four n-type GNRFETs and p- type GNRFETs, respectively is 1% 9%. Charge impurities affect static power more than dynamic power in a trend similar to that observed for variations, but to a smaller extent. When one to four GNRs in both the p-type and n-type GNRFETs are subject to +q and q charge impurities, respectively, static and dynamic power increase by 11% 37% and 5% 19%, respectively. Charge impurity defects have a smaller effect on the noise margin of an inverter in comparison to variations in GNR width. The presence of simultaneous +q and q charge impurities affecting one to four n-type and p-type GNRs, respectively, degrades the noise margin by 14% 40%, with a 7% improvement in the best case. C. Simultaneous Defects and Variations In this section, we study the impact of simultaneous variations in width and charge impurities on an inverter, ring oscillator, and latch. Table V shows the impact of simultaneous variations in width and charge impurities on the delay, power, and noise margins of an inverter. The nominal inverter has both n-type and p-type GNRFETs composed of four N = 12 GNRs and no charge defects. In the worst case when all GNRs in the array are affected, delay increases by over 2, static power increases by over 7, dynamic power increases by over 2, and the noise margin reduces to zero. These effects are less pronounced on delay and noise margin when only one GNR in the array is affected. However, static power still increases by nearly 4 and dynamic power by 1.5. To summarize, the delay, power, and noise margins for simultaneous defects and variations in the GNRFET inverter are dominated by variations in GNR width and exacerbated by charge impurities. The lower and upper bounds on the effects of width variations and charge defects were obtained by assuming that a nonideal GNRFET has a nonideality in exactly one out of four GNRs, or the same nonideality in all the GNRs. However, postfabrication GNRFETs may have different nonidealities on all four GNRs. Designing circuits that account for lower bound effects of variations and defects may lead to unreliable designs. On the other hand, designing circuits that account for upper bound effects is pessimistic and may lead to sub-optimal designs. Hence, it is necessary to study the average-case behavior of GNRFETs in the presence of nonidealities through Monte Carlo techniques. A randomly selected nonideality is injected in each GNR of the n-type GNRFET and p-type GN- RFET in an inverter. The inverter is simulated using tablelookup to compute its delay, static power, and dynamic power. The average delay, static power, and dynamic power over a large number of runs give the average-case behavior of the device. We performed Monte Carlo simulations using the aforementioned technique to study the average-case delay, static power, and dynamic power dissipation of an inverter. Independent variations in width (N = 9/12/15) and charge impurities ( q/0/+q) was assumed for the GNRs. The width and charge impurities for the GNRFETs were drawn from a normal distribution, with mean width N = 12 and mean charge equal to zero. The widths N = 9/15 and charge +q/ q were set to σ for the two distributions, which were discretized to reflect the nature of occurrence of variations and defects in GNRFETs. 1) Inverter: The delay of a nominal inverter is 18.2 ps. Variations and defects yield inverters with delay ranging from 13.5 to 41.9 ps. The mean delay of a GNRFET inverter in the presence of simultaneous variations and defects is 20.2 ps and the standard deviation is 4.2 ps. The static (dynamic) power dissipation of a nominal inverter is 0.11 μw (0.71 μw). Variations and defects yield inverters with static (dynamic) ranging from 0.07 μw (0.39 μw) to 0.4 μw(1.25 μw). The mean static (dynamic) power of a GNRFET inverter in the presence of simultaneous variations and defects is 0.14 μw (0.73 μw) and the standard deviation is 0.08 μw (0.13 μw). The mean delay for an inverter in the presence of defects and variations is 10% higher than the delay of the nominal inverter. Similarly, the mean static (dynamic) power dissipation of an inverter is 27% (3%) higher than the nominal value. Thus, the delay and static power of an inverter are most affected by variations and defects. 2) Ring Oscillator: A 15-stage ring oscillator consists of 15 inverters that could potentially have different delays, static power, and dynamic power dissipation depending on the variation-defect combination of the GNRs in its n-type GNRFET and p-type GNRFET. In each run of the Monte Carlo simulation, a variation-defect combination is injected separately in each GNR of every inverter in the ring oscillator. The propagation delay (Δ), static power (P stat ), and dynamic power (P dyn ) for each inverter is computed for a rising and a falling transition using the aforementioned technique. The frequency, static power, and dynamic power of the 15-stage ring oscillator is then computed using the propagation delay, static power, and

9 CHOUDHURY et al.: GRAPHENE NANORIBBON FETs: TECHNOLOGY EXPLORATION FOR PERFORMANCE AND RELIABILITY 735 worst case for inverters), a source of concern for most memory applications. However, both the redundancy required for error detection and correction as well as the high static power may be offset by the advantages of high density and low power that GNRFETs offer over scaled CMOS. Fig. 6. Fig. 7. Monte Carlo simulations for 15-stage ring oscillator. SNM for latch with variations and defects. dynamic power of each inverter as follows: 1 f = all inverters (Δ rise +Δ fall ) P stat = 0.5(P stat,rise + P stat,fall ) P dyn = all inverters all inverters 0.5(P dyn,rise + P dyn,fall ). Fig. 6 presents the distributions for delay, dynamic power, and static power for the oscillator. Although the mean value of dynamic power remains unchanged, the mean value of frequency decreases by 15% from the nominal value, and the mean value of static power increases by 20% from the nominal value. This is expected because variations and defects cause more degradation than improvement in delay and static power (see Table V). These results illustrate that even after careful engineering of V T, variations and defects have a significant impact on circuit performance and static power in GNRFET circuits. 3) Latches: There is a lot of interest in using low-power nanoelectronics to realize dense memory arrays. The tradeoffs involved are increased susceptibility to variations and defects, both of which impact the noise margins of memory cells and require error detection and correction support. Fig. 7 shows the butterfly curves for a latch built with two inverters for three cases: nominal, single GNR affected, and all GNRs affected. Both inverters in the latch are assumed to have the same widths and impurities. The worst case combination of defects and variations occurs when the n-type GNRFET has N = 9 and a +q charge impurity, and the p-type GNRFET has N = 18 and a q charge impurity (or vice versa, see Table V). Due to the asymmetry in the n-type and p-type GNRFETs of the inverters in the latches, one eye of the butterfly curve collapses to reduce the noise margin to near-zero, as shown in the figure. A second important observation is that the static power consumption of latches can increase by over 5 in the worst case ( the VI. CONCLUSION GNRFETs have been intensively explored both experimentally and theoretically as potential candidates for nanoelectronics applications. Quantum effects and atomistic scale features inevitably play an important role in such nanoscale electronic devices and circuits. We have developed a bottom-up multiscale simulation framework that treats atomistic scale features in circuit simulations. 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Circuits Conf., pp [35] P.-Y. Chen, Y.-L. Shaob, K.-W. Cheng, K.-H. Hsu, and J.-S. Wu, Threedimensional simulation studies on electrostatic predictions for carbon nanotube field effect transistors, Compute Phys. Commun., vol. 177, pp , [36] Y. Yoon and J. Guo, Effect of edge roughness in graphene nanoribbon transistors, Appl. Phys. Lett., vol. 91, pp , Mihir R. Choudhury (S 06) received the B.Tech. degree in computer science and engineering from the Indian Institute of Technology, Mumbai, India, in 2005, and the M.S. degree in electrical and computer engineering, in 2008 from Rice University, Houston TX, where he is currently working toward the Ph.D. degree in computer engineering. His research interests include advanced logic synthesis, circuit simulation, and design for reliability in scaled electronic technologies. Youngki Yoon (S 08 M 09) received the B.E. degree in material science and engineering from Korea University, Seoul, Korea, in 1999, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Florida, Gainesville, in 2005 and 2008, respectively. Since 2009, he has been with the University of California, Berkeley, where he is currently a Postdoctoral Researcher involved in the research on low-power electronics. He has authored or coauthored 17 papers in refereed journals in nanoelectronics and quantum device simulations. His research interests include the modeling and simulation of emerging and exploratory devices. Jing Guo (M 04) received the B.S. and the M.S. degrees from Shanghai Jiao Tong University, China, in 1998 and 2000, respectively, and the Ph.D. degree in electrical engineering from Purdue University, West Lafayette, IN, in He is currently an Associate Professor of electrical and computer engineering at the University of Florida, Gainesville. He was involved in the research on modeling and simulation of silicon nanotransistors, superconductor devices, and single-electron transistors. His current research focuses on modeling and simulation of electronic, optoelectronic, and sensing devices based on nanostructures, including nanotubes, nanowires, and graphene. He has authored or coauthored more than 60 journal papers in these research areas. He has coauthored a book, Nanoscale Transistors: Device Physics, Modeling, and Simulation (Springer, 2006). Dr. Guo is a recipient of the National Science Foundation (NSF) faculty early CAREER award. He was engaged in technical program committees of International Electron Devices Meeting (IEDM) and Device Research Conference (DRC). Kartik Mohanram (S 00 M 04) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Mumbai, India, in 1998, and the M.S. and Ph.D. degrees in computer engineering from the University of Texas, Austin, in 2000 and 2003, respectively. He is currently in the Department of Electrical and Computer Engineering, Rice University, Houston, TX. His research interests include computer engineering and systems, nanoelectronics, and computational biology. Dr. Mohanram is a recipient of the National Science Foundation (NSF) CAREER Award, the Association for Computing Machinery/Special Interest Group on Design Automation (ACM/SIGDA) Technical Leadership Award, and the A. Richard Newton Graduate Scholarship.