Void Induced Thermal Impedance in Power Semiconductor Modules: Some Transient Temperature Effects

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1 Void nduced Thermal mpedance in Power Semiconductor Modules: Some Transient Effects.. Katsis and.. van Wyk enter for Power Electronics Systems The radley epartment of Electrical and omputer Engineering Virginia Polytechnic nstitute and State University lacksburg, VA 261 USA Abstract The operation of power semiconductor modules creates thermal stresses that grow voids in the solder die-attach layer. These voids reduce the ability of the die-attach solder layer to conduct heat from the silicon junction to the heat spreader. This results in increased thermal impedance. The effect of accelerated aging on solder bond voiding and on thermal transient behavior is investigated. ommercially packaged TO-247 style MOSETs are power cycled, imaged, and thermally analyzed to generate a correlation between void percentage and thermal impedance.. NTROUTON Power semiconductor modules are subject to repetitive power and thermal stresses in normal operation. Over time, these stresses create voids that accumulate in the die-attach solder layer.[1][2] This solder layer is only several mils thick but it is critical to removal of heat from within the power semiconductor module.[3] As power cycles accumulate over the life of the module, the voids grow larger. Large, coalesced voids have a more significant effect on heat flow than small distributed voids.[5] These large voids increase thermal impedance and result in greater temperature fluctuations within the semiconductor module as indicated schematically in fig. 1.[6] This excess heat accelerates damage to the entire device. eat low ncreasing Void Size ncreasing Thermal Resistance igure 1: Effect of Voiding on the eat low in the Semiconductor Package This work was supported primarily by the ER Program of the National Science oundation under Award Number EE A technique for measuring thermal impedance in power semiconductors is developed to measure semiconductor junction temperature as a function of time. This technique samples junction temperature using the on-state resistance of the device while it is being heated. Other techniques for measuring thermal impedance sample device temperature on cool-down using the temperature sensitive characteristics of a diode mounted in the vicinity of the semiconductor or on the same device. [7][10] Our goal is to use thermal impedance measurement to demonstrate the effect of die-attach voids on thermal performance degradation during device heating. Accelerated aging is used to initiate and promote void growth in solder die-attach on a sample batch of commercially packaged MOSETs. These MOSETs are used as a vehicle to investigate some effects also applicable in power semiconductor modules employing several semiconductor devices. We monitor the progress of the void growth in these discrete packages through the use of acoustic microscopy and measurements of thermal impedance. Then we correlate the effect of the voids of the packaging on the thermal performance changes.. ROWT O E ATTA VOS Thermal stress and sustained high temperature helps to deform the solder in the die-attach layer of power semiconductors. Solder is subjected to these stresses because it is sandwiched between silicon, a brittle material, and copper, a material harder than solder. The solder formulation for the MOSET module investigated in this paper is 92.5% lead, 2.5% silver, and 5% tin. (ased on manufacturer data) Solder deformation occurs under three different strain mechanisms: elastic, plastic and creep. n a thermal cycle, all three work together to fatigue the solder layer [4]. When a thermal cycle begins, the first strain experienced by the solder is elastic. Soon, the maximum temperature is reached and the solder goes beyond its yield strength. At this point plastic deformation occurs in the solder. uring this creep stage, the solder begins to deform as high temperature exposure persists. reep ends once the stresses caused by the expansion of the silicon die relative to the copper dissipate. Eventually the device begins to cool and the process repeats itself with the next thermal cycle.[2] X/01/$10.00 () 01 EEE 1905

2 A thermal cycling profile is selected to accelerate void growth on a group of ten MOSETs. The temperature profile used in this study provides a 3-minute dwell at high temperature (100 ) followed by a steep drop to in 2 minutes. The power cycle profile shown in fig. 2 shows the case temperature measured on the outer surface of the copper heat spreader. temperature Actual Profile Temp time-minutes igure 2: Power ycle Profile and Measured evice ase The power cycle procedure uses a current to heat ten series connected MOSETs by forward biasing their integral body diodes. The temperature within the chamber cavity is maintained at. The current (10.8A) that passes through the MOSET diode heats each package to a steady state temperature of 100. ooling is accomplished by simple radiation and convection from the air circulation in the chamber s cavity. igure 3. MAN E ATTA VOS Knowing void size in the die-attach region is key to measuring the accumulated physical degradation. Scanning acoustic microscopy allows the user to see voids by sending focused ultrasonic pulses into the module. Voids are lowdensity areas compared to the surrounding metals. These low-density regions appear as spaces between cracks and delaminations in the solder/silicon or solder/copper interface. Therefore voids easily reflect ultrasonic energy back to the ultrasonic transducer. The transducer plots the reflected energy as a function of location. This plot emerges as a map of voids within the module at a specific depth. The use of this technique is non-destructive, allowing the device to be returned to service after an image is captured. The images in igure 4 are examples of void growth within the die-attach region of a power MOSET. Significant growth is seen in the first 1000 thermal cycles for the power MOSETs analyzed here. After 1000 cycles, void growth continues but at a less aggressive rate. New evice 1000 ycles 00 ycles 00 ycles 00 ycles % Voided Area Thermal ycles MOSETS hamber Shelf igure 4: Void rowth in the ie-attach Layer of a Particular MOSET Sample Software provided by the manufacturer of the scanning acoustic microscope is used to measure the void percentage in the die-attach layer. The image of the die-attach area in which the void area is to be determined, is demarcated beforehand to define the measurement region of the voids. Then the software takes the user s threshold for pixel color and compares it to the pixels in the scanned image of the voids. All pixels that correspond to bright colors are counted as voids. To maintain accuracy, a reference device of known void percentage is scanned along with the other devices and is used to calibrate the threshold color level. An error margin of about 2~3% is observed with this procedure. igure 3: Power ycling Setup for Ten MOSETs 1906

3 Pixel Measurement Tool ar ndicates Percent Voided Area ox efines Region of nterest Threshold olor Level mage of ie-attach Layer igure 5: Software Tool for Measurement of Voids. n order to illustrate the type of changes taking place, figure 6 shows an example of a single device that has been scanned at five points in its lifetime, starting from zero cycles, 1000, 00, 00, and 00 cycles respectively. The first image shows initial voiding remaining from the original soldering process. After 1000 cycles, the original voids have become larger and a new void has grown near the upper left hand corner. At 00 cycles, the middle void and the upper left hand corner void has doubled in area. At 00 cycles, the edges of the die-attach are showing evidence of numerous small voids. Edge delamination is prevalent at this stage in all but the lower right corner. These voids grow towards the center of the die-attach, as seen at the 00 cycle stage. At this stage, large voids have also combined with smaller voids. nitial Void istribution Edge racking e-adhesion of material within void ontinued rowth of Edge rack rowth of Void Area Appearance of New Voids Aggressive rowth of Void Area Well efined Edge Well efined rack Edge elamination igure 6: Void rowth within a Representative Power Semiconductor V. RET TEMPERATURE MEASUREMENT The first step to developing a thermal impedance measurement system is to define and use a temperature sensitive parameter within the power semiconductor module that is being analyzed. n the power MOSET family, the following characteristics are sensitive to temperature: [7],[8] On-state Resistance: R S(ON) Threshold Voltage: V T ntegral ody iode orward Voltage rop Reverse ias Leakage / reakdown Voltage Reverse Recovery Time The reverse bias leakage current of the body diode has the highest temperature sensitivity. owever, on-state resistance, R S(ON) is chosen for our system. This is because R S(ON) has a strong correlation to temperature and it can be easily inferred measured device current and voltage. ate drive designs already exist to measure these quantities, making it possible to integrate these measurements into power conversion systems. [11] A semiconductor curve tracer and a temperature-controlled oven were used to characterize R S(ON) vs. temperature for the power MOSET. A total of ten samples of the same type of MOSET were tested. Our measurements found negligible variations of this parameter from part to part. igure 7 illustrates that R S(ON) increases linearly from to 1. The value of this resistance creates a voltage drop that is easy to measure, from 1.9V to 4.5V, at the 10A current level. This strong correlation of R S(ON) to temperature makes it a good tool for tool for temperature measurement. t has been established that for the MOSET samples used, contact resistance, package resistance, and wire-bond resistance contribute 5% to the overall resistance. RS-Ohms igure 7: On-state Resistance as a unction of for the XYS X24N MOSET V. TERMAL MPEANE MEASUREMENT A parameter used to characterize thermal performance of electronic packages is thermal resistance, R T. This resistance is modeled as a steady state behavior by the relationship: 1907

4 Rth Tj Tref P = (1) Tj is the steady-state junction temperature, Tref is a reference temperature, and P is the steady state power dissipation. n a power semiconductor module, the layers of silicon, solder, and copper also store heat. t becomes necessary to account for the heat capacity of these structures when considering transient capability of the power semiconductor module. Therefore we investigate thermal impedance defined as, Tj( t) Tref Zth = P P is defined as a constant amplitude power step, Tj is the junction temperature, and Tref is the reference temperature as function of time. Thermal impedance gives us the advantage of predicting the expected temperature rise in a power semiconductor module under transient conditions. n order to measure this, our thermal impedance system makes a measurement of silicon junction temperature while the device is heating. t does this by alternating heating intervals and temperature measurements in rapid succession as indicated schematically in igure 8 (2) current; therefore the device under test dissipates constant power. This power is about 2W and is chosen to be close to the expected conduction losses of a similar MOSET operating at full load near maximum operating temperature. This cycle is controlled by the function generator that gates the drive voltage of the MOSET into one of two stable states at a repetition frequency of 1kz. As shown in fig. 9 the device starts in the heating mode for 9µs. Then the MOSET enters temperature measurement mode for µs. n the measurement mode, the MOSET is driven to saturation (V S = 10V) to measure the on-state voltage and current of the device. mmediately after the measurement, the MOSET returns to the previous mode to continue heating. A digital storage oscilloscope is used to measure the voltage and current across the MOSET. This data is recorded and processed offline in MATLA to retain only the data points in the voltage and current waveform corresponding to temperature measurement intervals. All other data points during heating intervals are thrown out. Power eating eating eating Measurement Measurement Time Measurement Saturation ate river 10V unction enerator 1 kz Measure Measure eat eat ate rive Level Saturation Saturation Saturation Linear Region Linear Region Linear Region Time 9µs µs igure 9: Thermal mpedance Measurement Schematic RE Setting LOW 5 A urrent Regulator UT V ata Acquisition igure 8: Operating Schematic of the Thermal mpedance Analyzer The thermal impedance analyzer has two operating modes, heating of the semiconductor module and temperature measurement. The heating cycle is accomplished by operating the MOSET in its linear region to achieve high power dissipation. A closed-loop current regulator maintains the drain current at 5A to the device under test by modulating the gate drive voltage to the MOSET. A power supply operating as a voltage source at V feeds the necessary The system therefore alternates between heating and measurement cycles to build up a collection of temperature measurements every millisecond. This process is carried out at a 1kz sampling frequency for microseconds. V. RESULTS AN SUSSON The Total of 10 devices that were subjects of this study were divided as follows: - Three devices were not cycled at all (control group) - Two devices were removed from the power cycling chamber at 00 power cycles - ive devices were power cycled 7000 times Each MOSET has been scanned to generate a map of voided area. igure 10 contains a summary of the MOSET s cycle count, voided area, and corresponding scanned image. 1908

5 A MOSET Total ycle ount Percent Voided Area A E temperature E igure 10: Void Area Summary of all the MOSETs Tested igure 12: Time/ Plot for Two MOSETS with 00 Power ycles or the following thermal impedance tests, all MOSET junction temperatures are measured for a total time of ms. s are plotted as a function of time. mages of the die-attach regions for each MOSET are included in the plots to help illustrate the void percentage and its impact on the temperature. As is evident from fig. 12 MOSETs and track different temperature curves but they do so because the void percentages are different. MOSET is actually the most voided sample of the entire group; its temperature at ms is higher than MOSET but still lower than MOSETs and. This is probably because of the 00 power-cycle difference between these devices leading to some as yet undetermined effects. A E temperature A E igure 11: Time/ Plot for ive MOSETS with 7000 Power ycles igure 11 shows the temperature vs. time curves for the 7000 power-cycle MOSETs. All of these MOSETs except for one also have the highest temperatures after ms. evices, and have the two highest temperatures and also have the highest percentage of voided interface area in this group. MOSETs A,, and E track the same temperature curve and as expected, their void percentages are similar. temperature igure 13: Time/ Plot for Three MOSETS with Zero Power ycles igure 13 is the control MOSET group. These devices have the lowest temperatures of all the MOSETs after ms. rom these results one can see an appreciable difference in heating transient response between these samples, although the percentage of voided area between these devices is similar, which is not clearly understood at present. 1909

6 temperature- Silicon ie ominant: Zth1 Transistion Region ominant: Zth2 eat Spreader ominant: Zth igure 14: hange in eating Slope igure 14 illustrates the differences in slope proportional to thermal impedance during the 2W heating cycle. or each of these regions, a constant slope has been estimated which later enables the calculation of constant thermal impedance for each of the time regions, i.e. Zth1, Zth2, and Zth3 respectively. n the first 5ms the transient is dominated by the thermal properties of the silicon die. Since the heat capacity of the die is small, its temperature rises quickly. The next region of interest is the sharp change in slope from 5ms to 10ms. This slope change possibly indicates the effects of a transition region from silicon to the die-attach layer. hristians et al. have also identified 10ms as the time it takes for heat to start propagating from the silicon die to the dieattach layer.[3] The thermal decreases as the influence of the heat spreader begins to dominate. inally the heat spreader dominates the last slope from 10 to ms. opper thermal impedance is naturally very low but the die-attach layer governs the rate of heat flow into this layer, greatly affecting its performance. igure 15 shows the initial thermal impedance of the silicon and beginnings of the die attach layer. t is expected that since the silicon volume is the same for all devices, the effect of the die-attach layer should be minimal up to 5ms. Therefore, the relationship between thermal impedance and voided area is weak this point, with essentially the same thermal impedance for all the modules. igure 16 shows the thermal impedance of the transition between the silicon and heat spreader layer. A stronger relationship between voided area and thermal impedance is seen in this area as the defects in the solder layer begin to appear. The relationship between thermal impedance and voided area shows a 33% difference from the control devices to devices with 7000 power cycles. igure 17 shows the thermal impedance dominated by the heat spreader layer. A very strong correlation appears between voided area and thermal impedance at this point. A 46% change is visible in thermal impedance from the control devices to devices with 7000 power cycles. Norm. Thermal mpedance-('*s/w). Norm. Thermal mpedance-('*s/w) Percent Voided Area igure 15: Thermal mpedance (Zth1) vs. Voided Area from 0ms to 5ms (Tref=) A Percent Voided Area igure 16: Thermal mpedance (Zth2) vs. Voided Area from 5ms to 10ms (Tref=) Norm. Thermal mpedance-('*s/w) A A Percent Voided Area igure 17: Thermal mpedance (Zth3) vs. Voided Area from 10ms to ms (Tref=) 1910

7 V. ONLUSONS The results of thermal impedance vs. voided area suggest at least 46% increase in thermal impedance of the die-attach region for aged devices at ms. This performance degradation also seems to correspond closely to the difference in the level of voiding between the group of highly power cycled and control devices, which is in the range of ~%. This correlation is significant because the die attach layer degradation will severely reduce the transient thermal capability of a power semiconductor module. t appears that the domination of the thermal transient during the first ms by the silicon die, the transition region between the die and heat spreader, and by the heat spreader can be deduced from the time-temperature curves. or each of these regions, characteristic thermal impedance is calculated. These thermal impedances can be used to calculate thermal transients under conditions of different excitation than used in this experiment. mpedance Measurement Practice and Experiment 00 ntersociety onference on Thermal Phenomena, pp [11] Yong-Seok Kim; Seung-Ki Sul, On-line estimation of T junction temperature using on-state voltage drop EEE ndustry Applications onference, 1998, Page(s): vol.2 [12] Win Software Release ver. 2.5, Sonix, nc. AKNOWLEMENTS This work was supported in part by the ER Program of the National Science oundation under Award Number EE The authors also acknowledge the support from Ralph Locher at XYS in providing the MOSETs used in this reliability study. REERENES [1] rown, E.R., Shaw, M.., Thermomechatronics of Power Electronic Packages EEE TERM, onference Proceedings, 5/00 Las Vegas [2] Srinivasan, P. Reliability of Solder ie Attaches for a igh Power Application, Masters Thesis, University of Maryland, ollege Park, 00 [3]. hristiaens,. Vandevelde, E. eyne, and. Roggen, Evaluation of Structural egradation in Packaged Semiconductor omponents Using a Transient Thermal haracterization Technique Microelectron. Rel., vol. 36, pp , [4] Sarihan, V. Energy ased Methodology for amage and Life Prediction of Solder oints Under Thermal ycling, EEE Transactions on omponents, Packaging, and Manufacturing Technology-Part, Vol 17, No 4, 1994 [5] Zhu, N. Thermal mpact of Solder Voids in the Electronic Packaging of Power evices. 15 th annual EEE SEM-TERM symposium, Proceedings San iego, A. pp [6] e,.,shaw, M..,Mather,..,Addison, R.., irect Measurement and Analysis of the Time ependent Evolution of Stress in Silicon evices and Solder nterconnections in Power Assemblies ndustry Applications onference, Thirty-Third AS Annual Meeting. The 1998 EEE, Volume: 2, 1998 Page(s): vol.2 [7]. W. Sofia, "Analysis of Thermal Transient ata with Synthesized ynamic Models for Semiconductor evices," EEE omp., ybrids, Manufact. Tech., vol. 18, no. 1, pp , March [8] ntersil A New PSPE Subcircuit for the Power MOSET eaturing lobal Options Application Note: AN9210.1, ntersil orp., October 1999 [9] Qi Quan, Reliability Studies of Two lip hip A Packages Using Power ycling Test Microelectronics Reliability. April 01 Vol. 41 No. 4 pp [10] Ludwig, M., oedke, A., Slattery. O., lannery,., O Mathuna, S., haracterisation of ie Attach for Power evices using Thermal 1911