Improved Bridgeless Interleaved Boost PFC Rectifier with Optimized Magnetic Utilization and Reduced Sensing Noise

Transcription

1 Jurnal f Pwer Electrncs, Vl. 14, N. 5, pp , September JPE ISSN(Prnt): / ISSN(Onlne): Imprved Brdgeless Interleaved Bst PFC Rectfer wth Optmzed Magnetc Utlzatn and Reduced Sensng Nse Guen Ca * and Hee-Jun Km * Department f Electrnc Systems Engneerng, Hanyang Unversty, Ansan, Krea Abstract An mprved brdgeless nterleaved bst pwer factr crrectn (PFC) rectfer t mprve pwer effcency and cmpnent utlzatn s prpsed n ths study. Wth cmbned cnventnal brdgeless PFC crcut and nterleaved technlgy, the prpsed rectfer cnssts f tw nterleaved and magnetc nter-cuplng bst brdgeless cnverter cells. Each cell perates alternatvely n the crtcal cnductn mde, whch can acheve the sft-swtchng characterstcs f the swtches and ncrease pwer capacty. Auxlary blckng ddes are emplyed t elmnate undesred crculatng lps and reduce current-sensng nse, whch are amng the serus drawbacks f a dual-bst PFC rectfer. Magnetc cmpnent utlzatn s mprved by symmetrcally cuplng tw nductrs n a unque cre, whch can acheve ndependence frm each ther based n the auxlary ddes. Thrugh the nterleaved apprach, each swtch can perate n the whle lne cycle. A smple cntrl scheme s emplyed n the crcut by usng a cnventnal nterleaved cntrller. The peratn prncple and theretcal analyss f the cnverter are presented. A 600 W expermental prttype s bult t verfy the theretcal analyss and feasblty f the prpsed rectfer. System effcency reaches 97.3% wth lw ttal harmnc dstrtn at full lad. Key wrds: Brdgeless, Crculatng current, Cupled nductr, Interleaved bst, Magnetc ntegratn, Pwer factr crrectn (PFC), Sft swtchng I. INTRODUCTION Actve pwer factr (PF) crrectn (APFC) technques are cmmnly emplyed n many types f electrnc equpment t ncrease the PF and decrease the ttal harmnc dstrtn (THD) factr. The cnventnal APFC regulatr generally cmprses a brdge rectfer and a hgh-frequency sngle-ended DC DC cnverter such as a bst crcut [1], as shwn n Fg. 1. Hwever, fr the bst PF crrectn (PFC) crcut, current flws thrugh tw rectfer ddes and ne swtchng semcnductr (MOSFET r fast-recvery dde) durng ne peratn cycle []-[5]. Fr lw lne nput and hgh utput-pwer applcatns, the hgh cnductn lss caused by the frward vltage drp f brdge ddes dramatcally degrades verall system effcency [6]-[9]. The heat generated Manuscrpt receved Apr. 16, 014; accepted Jul. 17, 014 Recmmended fr publcatn by Asscate Edtr Tae-Wn Chun. Crrespndng Authr: hjkm@hanyang.ac.kr Tel: , Fax: , Hanyang Unversty * Dept. f Electrnc Systems Engneerng, Hanyang Unversty, Krea wthn the brdge dde caused by hgh cnductn lsses can als destry pwer devces [10]. T maxmze system effcency and ptmze thermal perfrmance, sgnfcant research effrts have been devted t develpng brdgeless PFC tplges [11]-[14]. In a brdgeless PFC crcut, the frnt-end dde brdge s remved t decrease the number f semcnductr swtches n the current flwng path. Therefre, cnductn lsses are sgnfcantly reduced, whch results n hgh system effcency. A number f tplges t prduce brdgeless PFC crcuts have been develped [15]-[18]. One f the representatve mplementatns s the dual-bst PFC rectfer based n the tplgy shwn n Fg. [19], [0]. In ths crcut, the bst cnverter s cmbned wth the nput brdge dde and perates smlarly t the cnventnal bst PFC cnverter. Fr the dual-bst PFC crcut shwn n Fg., tw bst cnverters are emplyed fr each half lne cycle. The peratn f ths crcut s symmetrcal n tw half lne cycles f the nput vltage [1]. Cnsequently, the lne current smultaneusly flws thrugh nly tw semcnductrs, whch reduces 014 KIPE

2 816 Jurnal f Pwer Electrncs, Vl. 14, N. 5, September 014 D 1 Undesred Crculatng Lp D 1 D V AC S 1 C R L V AC C R L L D L D N S 1 S R s Fg. 1. Cnventnal bst PFC rectfer. Fg. 3. Undesred crculatng current lp n the dual-bst PFC rectfer. V AC C R L L D 1 D D 1 D V AC C R L L S 1 D L S D N D L D N S 1 S Fg.. Basc dual-bst brdgeless PFC rectfer. cnductn lsses. The tw nductrs n ths tplgy als lead t better thermal perfrmance and mprved space utlzatn cmpared wth a sngle nductr n cnventnal bst tplgy []. Therefre, ths cnverter ncreases system effcency, partcularly n hgh-pwer applcatns. Hwever, the dual-bst brdgeless PFC rectfer has several essental practcal drawbacks [3]. As shwn n Fg. 3, the undesred crculatng lp marked by thcker lnes can cause a large crculatng current that leads t measurement errrs thrugh current-sensng resstr R s. Ths prblem can als cause a large electrmagnetc nse and pr system cntrl perfrmance, partcularly n average current mde cntrl. These drawbacks make the dual-bst crcut unsutable fr practcal applcatns. Anther majr drawback f ths tplgy s the lw utlzatn f swtches and magnetc cmpnents [4]. Fg. 4 ndcates that fr the tw bst cells, namely, S 1 D 1 and L S D, each cell perates fr a half lne cycle, wth ne cell peratng whle the ther ne remans dle. As a result, the utlzatn f swtches and magnetc cmpnents s nly 50% that f the cnventnal bst PFC cnverter, whch always utlzes all the cmpnents durng the whle lne cycle. Lw cmpnent utlzatn can be a serus lmtatn n terms f system weght and pwer densty. T vercme these drawbacks f the dual-bst PFC, an mprved nterleaved bst brdgeless PFC rectfer was prpsed n ur prevus reprt [5]. The prpsed rectfer, whch cnssts f tw nterleaved bst brdgeless PFC cells, s develped by cmbnng the cnventnal dual-bst PFC rectfer wth nterleaved technlgy. In ths study, a detaled analyss f the prncple f mprved cmpnent utlzatn, desgn cnsderatn, cmparsn study f cnventnal PFC (a) V AC C R L L D 1 D D L D N S 1 S (b) Fg. 4. Operatng stages f the dual-bst brdgeless PFC rectfer durng. (a) Pstve half lne perd. (b) Negatve half lne perd. crcuts, and cntrl strategy s dscussed. Auxlary blckng ddes are used t elmnate the undesred crculatng current lp and mprve sensng sgnal qualty. T ncrease the utlzatn f magnetc cmpnents, the tw nductrs n the cnventnal dual-bst PFC crcut are symmetrcally cupled n a sngle ferrte cre. Hence, crcut sze and cst can be reduced. The nterleaved technque s als ntrduced t the cnventnal tplgy. Thus, the swtches can perate durng the whle lne cycle, whch ncreases MOSFET utlzatn. When peratng n crtcal cnductn mde (CrM), the swtches can acheve sft swtchng t reduce swtchng lss and enhance cnversn effcency wthut any auxlary crcut. Thrugh the nterleaved peratn, the current wavefrm can exhbt lwer rpple and smaller harmnc cntent than thse f cnventnal tplges under the same pwer cndtn. Therefre, the szes and lsses f the bst nductrs and flterng stages can be reduced and swtchng lsses can be decreased. The desgn cnsderatns n nductance value and

3 Imprved Brdgeless Interleaved Bst PFC Rectfer wth 817 cmpnent current stresses f cnventnal cntnuus cnductn mde (CCM) bst PFC, CrM dual-bst PFC, and the prpsed PFC rectfer are dscussed and cmpared n detal. A smple and effectve cntrl scheme s emplyed and explaned. The rest f ths paper s rganzed as fllws. Sectn II elucdates the crcut cnfguratn and peratn prncple f the prpsed PFC rectfer. Sectn III explans the desgn cnsderatn f the pwer stage and cntrl strategy, as well as the cmparsn study f cnventnal PFC tplges. Sectn IV presents the smulatn and expermental results. Fnally, Sectn V cncludes the paper. V AC D N D L R s L L 3 L 4 D 5 D 6 S A D 7 D 8 Fg. 5. Prpsed nterleaved bst brdgeless PFC rectfer. S B Interleaved Cell A D 1 D D 3 D 4 C R L D 1 II. CIRCUIT CONFIGURATION AND OPERATION PRINCIPLE A. Crcut Cnfguratn The prpsed rectfer s frmed by cmbnng nterleaved cnverters wth a brdgeless PFC tplgy as shwn n Fg.5. S A and S B are the man swtches. D 1 D 4 are the bst ddes, whle D 5 ~ D 8, D N, and D L are slw ddes. ~ L 4 are equvalent bst nductrs. C s the utput capactr, R L s the equvalent resstve lad, and V AC s the nput. R s s the current sensng resstr used fr the system current cntrl lp. In ts cnfguratn, the crcut has the same number f MOSFETs as the dual-bst PFC rectfer. The prpsed rectfer requres fur addtnal slw ddes n seres wth the MOSFETs t blck the undesred current lp as well as tw fast ddes parallel wth the bstng ddes that are beng perated ut f phase t ncrease system pwer capacty. The equvalent crcut f the prpsed rectfer s shwn n Fg. 6. The crcut cnssts f tw nterleaved bst cnverter cells. Each cell cmprses tw parallel bst phases. The nterleaved cell A s cmpsed f D 6 S A D 1 as phase A 1 and L D 8 S B D as phase A, whle cell B s cmpsed f L 4 D 5 S A D 4 as phase B 1 and L 3 D 5 S B D 4 as phase B. Therefre, swtch S A s shared by the frst phase f each nterleaved cell A 1 and B 1, whle swtch S B s shared by each secnd phase A and B. Because f the nterleaved structure, S A and S B can perate n the entre lne cycle f the nput vltage. B. Cupled Inductrs wth Optmzed Magnetc Utlzatn In Fg. 6, cupled nductrs L A and L B are represented by fur decupled nductrs L 4. and L 4 are cupled clsely n the same ferrte cre t cmprse cupled nductr L A, whereas L and L 3 are cupled as L B. Althugh tw addtnal nductrs are ndcated, the magnetc cre sze can be smaller, wth cmpettve cmpnent cst, thrugh the nterleaved peratn cmpared wth cnventnal PFC tplges n the same pwer level applcatns. In addtn, cre utlzatn can be mprved sgnfcantly and thermal V AC D N D L Interleaved Cell B R s L L 3 L 4 D 5 D 6 S A Cupled Inductr L A D 7 D 8 S B D D 3 D 4 C Cupled Inductr L B Fg. 6. Equvalent crcut f the prpsed PFC rectfer. L 4 L1 L sen1 sen1 Φ 1 Φ Φ 4 L sen4 sen Fg. 7. Structure f the cupled nductr and current-sensng wndng. perfrmance can be enhanced. Fg. 7 shws the mplementatn structure f the cupled nductrs and L 4 wth reference plarty and magnetc flux. The tw wndngs are wund n the tw legs f the EE-type cre n the same drectn. As can be seen frm Fg. 6 and Fg.7, current L1 generates magnetc flux Φ 1 n the cre leg durng the n-state f S A. The change f flux Φ 1 nduces the electrmtve frce n wndng L 4. Gven that the current s blcked by ddes D 5 and D N, n crculatng path exsts fr wndng L 4. Thus, current L4 s zer. Smlarly, current L1 s als zer when L4, whch causes change f Φ 4, flws thrugh wndng L 4. Gven that the wndng structure s symmetrc, that s, = L 4 = L and L = L 3 = L, the turn numbers are btaned as N 1 = N 4 = N and N = N 3 = N, respectvely. Accrdng t Fg. 7, the flux lnkages f the uter legs and the center leg can be descrbed as fllws: L4 R L

4 818 Jurnal f Pwer Electrncs, Vl. 14, N. 5, September 014 { 1 F N1 = L1 L1, durng pstve lne cycle Y1 =, (1) 0, durng negatve lne cycle { 0, durng pstve lne cycle Y 4 =, F N = L L, durng negatve lne cycle Y1 { Y 4 (), durng pstve lne cycle Y =. (3), durng negatve lne cycle Accrdng t the peratn ndcates that and L 4 wrk as cupled nductrs wth small leakage nductance. Cnsequently, nductrs and L 4 are magnetcally ndependent f each ther and can be used as tw nductrs. The same cnclusn can be drawn fr cupled nductrs L and L 3. By referrng t Fg. 7, L sen1 and L sen4 are the auxlary current-sensng wndng, whch are cupled n the same legs wth bst nductrs and L 4, respectvely. sen1 and sen4 are the sensng sgnals f each current that can be used fr peak current mde cntrl. In VAC In VAC VAC DN VAC In L1 L L3 L4 DL In L1 L L3 L4 IL4 IL1 IL1 IL IL D5 D6 SA (a) IL3 IL3 IL4 D5 D6 D1 D D3 D4 D7 D8 C RL SB D1 D D3 D4 D7 D8 C RL C. Prncple fr Elmnatng Undesred Crculatng Lp As llustrated n Fg. 5 and Fg. 6, the current f each phase s blcked by emplyng D 5 ~ D 8. Thus, n crculatng current lp exsts amng the bst phases. The current measurement errr acrss sensng resstr R s s accrdngly elmnated, and sensng nse s reduced sgnfcantly. The electrmagnetc nterference (EMI) perfrmance f the system can be mprved sgnfcantly. It shuld be nted that althugh the prpsed crcut emplys mre ddes than the dual-bst PFC rectfer, ts pwer capacty s hgher because f nterleaved peratn. Cnsderng that the frward vltage f the dde ncreases wth rsng passng current, lwer cnductn lsses can be acheved frm the prpsed crcut than frm the cnventnal sgnal phase bst PFC rectfer because f ts lwer current stresses. Mrever, gven that the nput lne frequency s suffcently lw (50 Hz r 60 Hz), slw-recvery ddes can be used fr D 5 ~ D 8. T guarantee cmmn-mde EMI perfrmance, D N cnducts n the pstve half lne cycle, whereas D L cnducts n the negatve half lne cycle t cnnect the nput t the system grund drectly. D. Crcut Operatn Prncple wth Imprved Cmpnent Utlzatn The equvalent peratng crcuts durng the pstve and negatve half lne perds are shwn n Fg. 8(a) and Fg. 8(b), respectvely. The peratns f each half lne cycle are explaned belw. Fg. 8(a) shws that durng the pstve half lne perd, bst phases D 5 S A D 1 and L D 8 S B D perate alternatvely. When S A s turned n, current flws thrugh, D 5, S A, and D N, and energy s stred n. When S A s turned ff, current flws thrugh, D 1, and D N, delverng the energy t the utput. Smlarly, L D 8 S B D perates under the same prncple wth nterleaved mde. Durng ths half lne DN DL SA (b) Fg. 8. Operatng stages f the prpsed cnverter n Fg.5: (a) durng the pstve half lne perd and (b) durng the negatve half lne perd. perd, bst phases L 4 D 6 S A D 4 and L 3 D 7 S B D 4 are n dle state. Inductrs and L 4 are cupled n ne ferrte cre, whereas L and L 3 are cupled n anther ferrte cre. Althugh L 3 and L 4 are dle, the magnetc cres are fully utlzed. Smlar results can be btaned durng the negatve half lne perd. Fg. 8(b) shws that when S B s turned n, energy s stred n L 3 thrugh D 7, S B, and D L. When S B s turned ff, energy s released thrugh L 3, D 3, and D L. Because f the nterleaved peratn, L 4 D 6 S A D 4 perates ut f phase n the same mde. The peratn analyss reveals that the swtch S A perates n phase A 1, D 5 S A D 1 durng the pstve half lne cycle and n phase B 1, L 4 D 6 S A D 4 durng the negatve half lne cycle. Swtch S B perates n phase A, L D 8 S B D durng the pstve half lne cycle and n phase B, L 3 D 7 S B D 4, durng the negatve half lne cycle. Cnsequently, S A and S B can perate n the whle lne cycle f the nput vltage, and cmpnent utlzatn s mprved. E. Operatn Analyss f the Prpsed Crcut Frm the peratn prncple llustrated n Fg. 8(a) and Fg. 8(b), t can be bserved that each bst phase has tw slw ddes, that s, ne MOSFET n the current flwng path durng the n-state f the swtch, as well as ne slw dde and ne fast dde n the current path durng the ff-state f the swtch. Ths peratn prncple can reduce the number f cnductn devces when cmpared wth cnventnal bst PFC rectfers. Hence, the cnductn lsses and the thermal stresses n the SB

5 Imprved Brdgeless Interleaved Bst PFC Rectfer wth 819 Item Inductance RMS current TABLE I COMPARISON BETWEEN THE CONVENTIONAL AND PROPOSED PFC RECTIFIER IN CRM Cnventnal CCM bst PFC P V CrM dual-bst PFC P 6V Prpsed PFC P 6V Inductance value V ( V - V ) * rv P f s _ mn V V V ( - ) V V - V V P f s _ mn ( ) V P f s _ mn Bst dde RMS current 6P 4 V V pv P 3V 4 V pv P 3V 4 V pv Slw dde cnductn lss 4 PV pv F zer 6PV 8 V F 1-1V 3pV MOSFET RMS current P V 8 V 1-3pV P 8 V 1-3V 3pV P 8 V 1-3V 3pV Output capactr hgh-frequency RMS current 8 P 3pV V - I 4 8 P - I 3 3pV V 8 P - I 3 3pV V Ratng utput pwer capacty Hgh Medum Hgh Current path (swtch n-state) slw ddes, 1 MOSFET 1 slw dde, 1 MOSFET slw ddes, 1 MOSFET Current path (swtch ff-state) slw ddes, 1 fast dde 1 slw dde, 1 fast dde 1 slw dde, 1 fast dde Reverse recvery ssue f the bst dde Serus Slght Slght Swtch and magnetc cre peratn perd Whle lne cycle Half lne cycle Whle lne cycle * ρ s the requred utput current rpple n CCM. semcnductr devces can be reduced. In addtn, hgh ntegratn and utlzatn f magnetc cres mprve pwer densty and reduce the verall weght f the PFC crcut. The tw pwer swtches S A and S B are drven by ut-phase cntrl sgnals and fllw the same peratn prncple as cnventnal nterleaved bst tplges. Ths peratn sgnfcantly smplfes the cntrl scheme and can be easly mplemented by usng several ndustry standard nterleaved cntrller ICs n the market. Accrdng t the crcut analyss, there s n lmtatn n the system peratn mde. Hwever, several advantages can be btaned when the crcut s perated n CrM. Under CrM, the prpsed rectfer can acheve zer current swtchng (ZCS) durng the turn-n transtn f the man swtches and the reverse recvery perd f the bst ddes. Cmpared wth ther peratn mdes, sft-swtchng and lw current rpples ncrease system effcency and reduce cnducted EMI nse. Anther advantage f the prpsed cnverter s current stress reductn fr the pwer swtch cmpared wth cnventnal bst and dual-bst PFC rectfers because f the nterleaved peratn. III. DESIGN CONSIDERATION OF THE PROPOSED CIRCUIT A. Pwer Stage Desgn and Cmparsn Study Ths sectn dscusses the desgn cnsderatn f the prpsed rectfer. T desgn practcal crcuts f the prpsed PFC, the key parameters f the pwer stage must be calculated, and the current and vltage stresses f the man pwer cmpnents must be carred ut. Durng analyss and evaluatn, all calculatns are based n the assumptns that unty PF s realzed n the prpsed crcut. The reverse recvery ssue f blckng ddes s neglected. Cnsderng that the parallel-perated bst phases are dentcal, the bst nductr s determned based n the nductance rpple current under lw lne-nput cndtns n CrM. Therefre, the nductr can be selected by where V _mn P V f s_mn V ( V - V ) L =, V P f s _ mn nput lw lne rt mean square (RMS) vltage, ratng nput pwer, utput vltage, mnmum swtchng frequency at lw lne nput. When peratng n CrM, the average nductr current s 50% that f the peak value. Therefre, the RMS nductr current wth ne nterleaved phase can be btaned as fllws: (4)

6 80 Jurnal f Pwer Electrncs, Vl. 14, N. 5, September 014 L1 L D 1 D V AC L L3 L 3 D 3 + L 4 D 4 L4 D 5 D 6 D 7 D 8 C V R L D N D L R s g S A A g S B B - s Gate Drver L1 L4 s Zer Current Detectn + - ZCDA Current Amplfer & Cmparatr Interleaved PFC Cntrller S R Q Interleaved Phase Management Vltage Multpler Q V AC V Cmp ZCDB S R Zer Current Detectn Cmpensatr Z F - + Errr Amplfer L L3 V ref Fg. 9. Cntrl part blck dagram f the prpsed crcut. I P 1 L _ rms = = V P V Semcnductr devces shuld be determned manly based n the pwer capacty requrements. Fr the prpsed rectfer, the swtches are selected accrdng t the peak vltage stresses and RMS currents flwng thrugh them. The RMS current f the bst ddes can be expressed as fllws: I D _ rms P = 6V 4 V pv Gven that the rectfer perates n CrM, n reverse recvery ssue exsts fr the bst ddes. Therefre, nly cnductn lsses shuld be cnsdered. The RMS current flwng thrugh the MOSFET f each phase s gven by I P S_ rms = V 3pV 8 V Cnsderng that each bst phase perates nly fr the half lne cycle, the RMS currents f blckng slw ddes are calculated n the same manner as the nductr current as fllws: I 6P 8 V SD _ rms = V 3pV.. (5) (6) (7) (8) Wth a frward vltage drp V F acrss the slw dde, the pwer lss f the dde can be calculated by P 6P 8 V SD = 1 - VF. 1V 3pV Assumng a resstve lad, the rpple current n the utput capactr s the cmbnatn f the twce-lne-frequency rpple current and hgh-swtchng-frequency rpple current, whch are typcally used t select hgh-vltage electrlytc utput capactrs. The RMS current that flws thrugh the utput capactr s gven by, Crms Crms _ LF Crms _ HF (9) I = I + I (10) I I Crms _ HF Crms _ LF = P V 16 P = - I, 9pV V, (11) (1) where P s the ratng utput pwer and I s the ratng utput current. The cmparsn study amng the cnventnal CCM PFC, dual-bst PFC n CrM, and the prpsed PFC rectfer are summarzed n Table. I. Snce the prpsed cnverter s cnstructed by cnnectng tw cnverters, n whch each cnverter perates as an nterleaved bst crcut n CrM, the

7 Imprved Brdgeless Interleaved Bst PFC Rectfer wth 81 current stresses f each nductance wndng and semcnductr devces are reduced sgnfcantly cmpared wth thse f the cnventnal sngle-phase bst PFC and brdgeless dual-bst PFC rectfers. The swtchng perfrmance f the prpsed crcut remans as the advantages f brdgeless tplges and nterleaved cnverters, whch results n lw swtchng and cndtn lsses. The nput current n the prpsed PFC crcut flws thrugh fewer pwer devces cmpared wth that n cnventnal bst cnverters. Mrever, the peak nductr current s reduced t 50% f that f cnventnal brdgeless cnverters. Althugh mre pwer cmpnents are needed n the prpsed crcut than n the ther tplges, the pwer capacty requrements fr these cmpnents are lwer than thse fr the ther tw tplges under the same utput pwer level. Cnsequently, the quanttes and csts f the cmpnents n the prpsed crcut are cmpettve amng the cmpared tplges. B. Cntrl Strategy Cnsderatn Current mde cntrl has been wdely used and prvdes many advantages such as mprved lad regulatn and fast current prtectn. T cntrl the prpsed rectfer, a cntrl scheme based n peak current mde cntrl s emplyed. The smplfed scheme f the pwer stage and cntrller s shwn n Fg. 9. The cntrl blck ncludes the current cntrl lp, vltage cntrl lp, pulse-wdth mdulatn (PWM) cntrl, and nterleaved phase management. Smlar t the cnventnal peak current mde cntrl, the cntrller exhbts the functn f regulatng utput vltage n CrM, and peratn frequency vares cnstantly wth tme. As shwn n Fg. 9, wth a current lp nsde the vltage cntrl lp, the cntrller enables actve crrectn f the nput current wavefrms by wrkng prperly n hgh frequences, whch causes the nductr current t fllw the shape f the nput vltage wavefrm. The current-cntrl lp and vltage-cntrl lp perate tgether t sample system ttal current S and utput vltage V, respectvely. The multpler perates as a gan mdulatr. One nput f the mdulatr s the current sgnal that s prprtnal t the nput full-wave-rectfed vltage V AC. Anther nput cmes frm the vltage errr amplfer, whch takes n V and cmpares t wth reference vltage V ref. These tw sgnals are cnsdered and cmpared t determne the gan that s appled t the nput f the current cntrl. The current amplfer and cmparatr use nfrmatn frm the multpler and cmpares t wth a sample f utput current S t adjust the duty cycle f the PWM cntrl. Output current S s used as a fast feed-frward f the nsde lp and functns as the ramp t the current PWM cmparatr. The zer current detectn (ZCD) blcks (ZCDA and L sen1 L sen4 R S1 R S3 D S D S4 D S1 D S3 C S1 C S ZCDA R S R S4 Fg. 10. Smplfed ZCD crcut f the prpsed crcut. ZCDB) sense the multphase nductr currents L1 t L4 and use the nfrmatn as the reset sgnal t the PWM utputs. Fr CrM peratn, the MOSFET s turned n when the valley f the nductr current s detected. Fr each nterleaved cell, tw bst phases perate ndependently n an nteractve phase apprach, wth each phase prperly peratng n CrM. Snce tw nterleaved cells perate fr each half lne cycle, alng wth the nductrs f ne cell crss cuplng wth that f anther cell, the ZCD f the multphase nductrs s sgnfcant. An effectve and smple crcut s prpsed t mplement ZCD f the tw phases frm dfferent nterleaved cells. Fg. 10 shws the prpsed ZCD crcut. In ths crcut, tw current-sensng crcuts f tw legs frm ne cupled nductr are cnnected n parallel. Durng the pstve half lne perd, L sen1 senses the nductr current f. Lsen1 s taken t the ZCDA prt f the cntrller thrugh D S1. As the current f L 4 s blcked, Lsen4 becmes zer and s segregated frm ZCDA by D S3. Smlarly, durng the negatve half lne perd, Lsen4 s taken t the ZCDA prt thrugh D S3, whereas Lsen1 s segregated by D S1. Thus, we can btan the vltage f ZCDA prt v ZCDA as fllws: RS, pstve lne cycle v = ZCDA. R, negatve lne cycle (13) Lsen1 { Lsen4 S4 The same results are btaned frm the ZCDB crcut f anther cell. Therefre, althugh fur nductr channels exst n the pwer stage wth tw ZCD prts n the nterleaved cntrller, the prpsed crcut can effectvely detect the nductr current valley f each channel. Thus, the nterleaved bst brdgeless PFC crcut can be cntrlled by usng the cmmercal nterleaved PFC cntrller. IV. SIMULATION AND EXPERIMENTAL RESULTS A. Smulatn Results A PSpce smulatn mdel s develped t verfy the analyss f the prpsed PFC rectfer. The nterleavng CrM PFC cntrller frm Texas Instruments, Inc. (Texas, USA), UCC8063, s used as the system cntrller n the smulatn. The smulatn mdel s desgned wth the specfcatns shwn n Table II.

8 8 Jurnal f Pwer Electrncs, Vl. 14, N. 5, September 014 TABLE II PARAMETERS OF THE SIMULATED POWER STAGE Parameters Symbl Value Input vltage V ac 85 V ~ 65 V Lne frequency f L 60 Hz Output vltage V 388 Vdc Output pwer P 600 W Bst nductance t L 4 10 uh Output capactr C ut 500 uf Fg. 11 llustrates the smulated swtchng wavefrms f swtches S A and S B. S A and S B are turned n under ZCS, whereas bst ddes D 1 t D 4 are turned ff. Hence, mnmal reverse recvery nse and sgnfcantly lw swtchng lsses can be acheved frm the CrM prncple. The smulated nterleaved nductr and utput currents are shwn n Fg. 1. The fgure ndcates that CrM peratn s an effcent and cst-effectve technque that des nt requre lw reverse-recvery tme ddes. Gven that the tw stages are perated ut f phase, the current rpple s als sgnfcantly reduced. In partcular, the RMS current wthn the bulk capactr s dramatcally reduced. Fg. 13 presents the current wavefrms f and L f the cnventnal dual-bst brdgeless PFC rectfer shwn n Fg.. The vltage wavefrms acrss current-sensng resstr R s are als measured. Based n nductr current wavefrms, the undesred crculatng current s sgnfcantly large, whch causes cnsderable nse. Dstrtn f the current-sensng wavefrm s als serus n the cnventnal crcut. Furthermre, ne f the magnetc cres becmes dle after a half lne perd, whch leads t lw cmpnent utlzatn. Fr cmparsn, the current wavefrms f swtches S A and S B, as well as the current-sensng sgnal acrss R s f the prpsed crcut, under full-lad cndtns at 0 V lne vltage are shwn n Fg. 14. The nput and utput currents are als shwn n ths fgure. As llustrated, S A and S B perate n the whle lne cycle. Cmpared wth Fg. 13, Fg. 14 shws n measurement errr n the current-sensng sgnal, and the sensng nse s als reduced sgnfcantly. The nductr current wavefrms f the prpsed crcut n whle lne cycles are shwn n Fg. 15. After a half lne peratn perd, the nductr current becmes zer wthut a crculatng lp. The smulated wavefrms f the nput vltage, nput current, and utput vltage are shwn n Fg. 16. The nput current s n phase wth the nput vltage. The utput vltage remans cnstant durng the whle lne perd. B. Expermental Results A 600 W expermental prttype crcut as shwn n Fg.17, s bult and tested t verfy the peratn f the prpsed crcut. The desgn specfcatns are the same as thse fr the smulatn descrbed n Table. II. The cmmercal nterleaved Fg. 11. Wavefrms f drver sgnal V GS, dran-t-surce vltage V DS, and dran-t-surce current I DS f S A and S B. Fg. 1. Smulatn results fr the current wavefrms f and L wth the drver sgnals f S A and S B. Fg. 13. Smulatn wavefrms f the dual-bst PFC crcut. I L1, I L : nductr current f and L, respectvely; V Rs : current sensng sgnal. PFC cntrller, UCC8063, frm Texas Instruments, Inc. (Texas, USA) s emplyed. The expermental results f the prpsed crcut are shwn and analyzed as fllws. The dran-t-surce vltage wavefrms f S A and S B are shwn n Fg. 18. The swtches perate n the whle lne cycle, thereby mprvng cmpnent utlzatn. The vltage wavefrms thrugh D 5 and D 6 t the grund are shwn n Fg. 19. The vltage wavefrms f D 6 and D 8, whch are n tw phases f ne

9 Imprved Brdgeless Interleaved Bst PFC Rectfer wth 83 V DSA 00V 00V V DSB 5ms Fg. 18. Dran-t-surce vltage wavefrms f the swtches. Fg. 14. Smulatn wavefrms f the nput and utput currents, swtch current, and ttal current sensng sgnal f the prpsed crcut. V D5 00V V D6 00V 5ms Fg. 19. Vltage wavefrms acrss ddes D 5 and D 6. Fg. 15. Smulatn nductr current wavefrms f t L 4 n the prpsed crcut V D8 00V V D6 00V 5ms Fg. 0. Vltage wavefrms acrss ddes D 6 and D 8. L4 V n 350V Fg. 16. Smulatn wavefrms f nput vltage, nput current, and utput vltage L1 V Rs 5ms 0.5V Fg. 1. Inductr current wavefrms f and L 4 and the current-sensng sgnal. Fg. 17. Phtgraph f the prttype rectfer. nterleaved cell, are shwn n Fg. 0. Each dde perates n a half lne perd and blcks the current frm ther phases. Cnsequently, n undesred lp ccurs durng dle perd. In addtn, when peratng n a half lne perd, the RMS current stresses f the ddes D 5 ~ D 8 are lw, and thus, less deal devces can be used.

10 84 Jurnal f Pwer Electrncs, Vl. 14, N. 5, September 014 L1 V 00V L V n 00V n 0.5V V Rs Fg.. Inductr current wavefrms f and L and the current-sensng sgnal. 5ms 10ms Fg. 4. Expermental results fr the nput vltage, nput current, and utput vltage at full lad wth 0 V nput vltage. I L1 L 5µs Fg. 3. Expermental current wavefrms f and L. The current wavefrms f and L 4 under full lad and 0 V nput vltage cndtns are shwn n Fg. 1. Althugh tw nductrs are cupled n a sngle magnetc cre, the nductrs are magnetcally ndependent f each ther, wth wrkng n a pstve half lne cycle and L 4 peratng n a negatve half lne cycle. The sensng sgnal f system ttal current V Rs s als shwn n the fgure. Gven the auxlary blckng ddes, n undesred crculatng current ccurs n the nductr current lp. Therefre, the current-sensng sgnal can be mre exact and stable than n the cnventnal crcut. Fg. shws the current wavefrms f and L. The tw nductrs perate n the same half lne perd n CrM. Durng the half lne cycle, the tw swtches perate n nterleaved mde, whch s the same peratn when usng the cnventnal nterleaved tplgy. Hwever, the number f cmpnents n the current path s reduced by the brdgeless tplgy. The sum nductr current and ndvdual currents f and L are shwn n Fg. 3. Effectve rpple frequency s ncreased twce, and peak-t-peak value nput rpple current s sgnfcantly reduced cmpared wth the tw nductr current rpples because f the nterleaved peratn. Cnsequently, nput flter sze can be decreased. The bst phases als perate n CrM wthut reverse-recvery prblems. Fg. 4 shws the nput current versus the nput vltage at full lad, as well as the utput vltage. The nput current s n phase wth the nput vltage and practcally snusdal wth Fg. 5. Measured system pwer factr under dfferent nput vltages. Fg. 6. Measured system THD under 0 V nput vltage and full lad cndtns. lw THD and hgh PF. The utput vltage s cnstant wth lw rpple. The measured PFs f the prpsed crcut under 85 V and 65 V nput vltages are shwn n Fg. 5. The prpsed rectfer acheves hgh PF under 85 V, whch s always hgher than 99% frm a 10% lad t the full lad. Under 65 V nput vltage, the PF s hgher than 99.6% under the rated lad. The measured THD f the prpsed PFC under 0 V nput vltage and full lad s shwn n Fg. 6. The prpsed

11 Imprved Brdgeless Interleaved Bst PFC Rectfer wth 85 REFERENCES Fg. 7. Measured system effcency under dfferent nput vltages. rectfer acheves lw THD, whch can satsfy the IEC Class D specfcatns. Fg. 7 shws the measured effcency curves f the prpsed PFC cnverter. The effcency at full lad under 85 V s ver 93%, and the maxmum effcency s 97.3%, whch s acheved at full lad and 65 Vac. Effcency s mprved at heavy lad because the cmpnent number n the current flwng path s reduced. V. CONCLUSIONS A nvel brdgeless nterleaved bst tplgy t vercme the serus drawbacks f cnventnal brdgeless PFC rectfers s prpsed n ths study. The prpsed crcut s cmpared wth the cnventnal nterleaved bst cnverter and brdgeless PFC tplgy that perate n CrM wth sft swtchng. The prpsed cnverter prvdes hgher utput pwer and lwer current rpple than the ther tplges. T verfy the feasblty f the prpsed cnverter, a 600 W prttype s desgned and tested. The perfrmance f the cnverter s als demnstrated by the smulatn and expermental results. Nearly unty PF and lw THD are acheved. Pwer effcences f 94.% and 97.3% are btaned under 85 V and 65 V nput vltages, respectvely. Therefre, ths mplementatn s a cmpettve canddate fr hgh-pwer applcatns. ACKNOWLEDGMENT Ths wrk was supprted by the Energy Effcency & Resurces Cre Technlgy Prgram f the Krea Insttute f Energy Technlgy Evaluatn and Plannng (KETEP) granted fnancal resurce frm the Mnstry f Trade, Industry & Energy, Republc f Krea (N ). [1] C. Da Cunha Duarte and I. Barb, A new famly f zvs-pwm actve-clampng dc-t-dc bst cnverters: analyss, desgn, and expermentatn, IEEE Trans. Pwer Electrn., Vl. 1, N. 5, pp , Sep [] C.-M. Wang, A nvel zer-vltage-swtchng pwm bst rectfer wth hgh pwer factr and lw cnductn lsses, IEEE Trans. Ind. Appl., Vl. 5, N., pp , Apr [3] Y.-S. Rh, Y.-J. Mn, J.-C. Gng, and C. Y, Actve pwer factr crrectn (PFC) crcut wth resstr-free zer-current detectn, IEEE Trans. Pwer Electrn., Vl. 6, N., pp , Feb [4] S. Hu, K. W. E. Cheng, and S. R. N. Prakash, A fully sft-swtched extended perd quas resnant pwerfactr-crrectn crcut, IEEE Trans. Pwer Electrn., Vl. 1, N. 5, pp , Sep [5] B. Prakash and S. Prakash, Analyss f hgh dc bus vltage stress n the desgn f sngle stage sngle swtch swtch mde rectfer, n Prc. ISIE 005, Vl., pp , 005. [6] L. Huber, Y. Jang, and M. Jvanvc, Perfrmance evaluatn f brdgeless pfc bst rectfers, IEEE Trans. Pwer Electrn., Vl. 3, N. 3, pp , May 008. [7] P.-W. Lee, Y. S. Lee, D.-W. Cheng, and X.-C. Lu, Steady-state analyss f an nterleaved bst cnverter wth cupled nductrs, IEEE Trans. Ind. Applcat., Vl. 47, N. 4, pp , Aug [8] R. Martnez and P. Enjet, A hgh-perfrmance snglephase rectfer wth nput pwer factr crrectn, IEEE Trans. Pwer Electrncs, Vl. 11, N., pp , Mar [9] B. Su and Z. Lu, An nterleaved ttem-ple bst brdgeless rectfer wth reduced reverse-recvery prblems fr pwer factr crrectn, IEEE Trans. Pwer Electrncs, Vl. 5, N. 6, pp , Jun [10] A. Sabzal, E. Ismal, M. Al-Saffar, and A. Fardun, New brdgeless dcm sepc and cuk pfc rectfers wth lw cnductn and swtchng lsses, IEEE Trans. Ind. Applcat, Vl. 47, N., pp , Mar [11] C.-M. Wang, A nvel zcs-pwm pwer-factr preregulatr wth reduced cnductn lsses, IEEE Trans. Industral Electrncs, Vl. 5, N. 3, pp , Jun [1] M. Gpnath and V. Sheela, Effcency analyss f brdgeless cuk cnverter fr pfc applcatns, n Cnf. ICICES 013, pp , 013. [13] H. Kanaan and K. Al-Haddad, A unfed apprach fr the analyss f sngle-phase pwer factr crrectn cnverters, n Cnf. IECON 011, pp , 011. [14] W. Wang, D.-C. Lu, and G. Chu, Dgtal cntrl f brdgeless buck pfc cnverter n dscntnuus nput vltage mde, n Cnf. IECON 011, pp , 011. [15] F. Musav, W. Eberle, and W. Dunfrd, A hgh perfrmance sngle-phase brdgeless nterleaved pfc cnverter fr plug-n hybrd electrc vehcle battery chargers, IEEE Trans. Ind. Appl., Vl. 47, N. 4, pp , Jul [16] C. Petrea and M. Lucanu, Brdgeless pwer factr crrectn cnverter wrkng at hgh lad varatns, n Cnf. ISSCS 007, Vl., pp. 1-4, 007. [17] J. Fguered, F. Tfl, and B. Slva, A revew f sngle-phase pfc tplges based n the bst cnverter, n Cnf. INDUSCON 010, pp. 1-6, 010.

12 86 Jurnal f Pwer Electrncs, Vl. 14, N. 5, September 014 [18] M. Mahdav and H. Farzanehfard, Brdgeless sepc pfc rectfer wth reduced cmpnents and cnductn lsses, IEEE Trans. Ind. Electrn., Vl. 58, N. 9, pp , Sep [19] W. Y. Ch, J. M. Kwn, and B. H. Kwn, Brdgeless dual-bst rectfer wth reduced dde reverse-recvery prblems fr pwer-factr crrectn, IET Pwer Electrn., Vl. 1, N., pp , Jun [0] E. Frmansyah, S. Tmka, S. Abe, M. Shyama, and T. Nnmya, A crtcal-cnductn-mde brdgeless nterleaved bst pwer factr crrectn, n Cnf. INTELEC 009, pp. 1-5, 009. [1] C. Zheng, H. Ma, B. Gu, R. Chen, E. Farac, W. Yu, J.-S. La, and H.-S. Kh, An mprved brdgeless sepc pfc rectfer wth ptmzed magnetc utlzatn, mnmzed crculatng lsses, and reduced sensng nse, n Cnf. APEC 013, pp , 013. [] D.-C. Lu and W. Wang, Brdgeless pwer factr crrectn crcuts wth vltage-dubler cnfguratn, n Cnf. PEDS 011, pp , 011. [3] B. Sngh, S. Sngh, A. Chandra, and K. Al-Haddad, Cmprehensve study f sngle-phase ac-dc pwer factr crrected cnverters wth hgh-frequency slatn, IEEE Trans. Ind. Infrmat., Vl. 7, N. 4, pp , Nv [4] Y. Jang and M. Jvanvc, A brdgeless pfc bst rectfer wth ptmzed magnetc utlzatn, IEEE Trans. Pwer Electrn., Vl. 4, N. 1, pp , Jan [5] G. Ca and H.-J. Km, An mprved brdgeless nterleaved bst pfc rectfer wth ptmzed magnetc utlzatn and reduced sensng nse, n Prc. 15th Int. Cnf. IEEE ICIT, pp , 014. Guen Ca receved hs B.S. n Electrcal Engneerng frm Shandng Unversty f Scence and Technlgy, Qngda, Chna n 009 and hs M.S. n Electrcal Engneerng frm Behang Unversty, Bejng, Chna n 01. He s currently wrkng tward hs Ph.D. n Electrcal Engneerng at Hanyang Unversty, Ansan, Krea. Hs research nterests are DC/DC cnverters and sft-swtchng technques. Hee-Jun Km receved hs B.S. and M.S.n Electrncs Engneerng frm Hanyang Unversty, Seul, Krea n 1976 and 1978, respectvely. He receved hs Ph.D. n Electrncs Engneerng frm Kyushu Unversty, Fukuka, Japan n Snce 1987, he has been wth the Department f Electrnc Systems Engneerng, Hanyang Unversty, Ansan, Krea, where he s currently a prfessr. Hs current nterests nclude swtchng pwer cnverters, electrnc ballasts, sft-swtchng technques, and analg sgnal prcessng. Dr. Km s the presdent-elect f the Krean Insttute f Electrcal Engneers and a senr member f the IEEE.