A Bidirectional Non-Isolated Multi-Input DC-DC Converter for Hybrid Energy Storage Systems in Electric Vehicles

Transcription

1 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy A Bdrectnal Nn-Islated Mult-Input D-D nverter fr Hybrd Energy Strage Systems n Electrc ehcles F. Akar, Y. Tavlasglu, E. Ugur, B. ural, I. Aksy Abstract In rder t prcess the pwer n hybrd energy systems usng reduced part cunt, reseachers have prpsed several mult-nput dc-dc pwer cnverter tplges t transfer pwer frm dfferent nput vltage surces t the utput. Ths paper prpses a nvel bdrectnal nn-slated mult-nput cnverter (MI) tplgy fr hybrd systems t be used n electrc vehcles cmpsed f energy strage systems (ESSs) wth dfferent electrcal characterstcs. The prpsed cnverter has the ablty f cntrllng the pwer f ESSs by allwng actve pwer sharng. The vltage levels f utlzed ESSs can be hgher r lwer than the utput vltage. The nductrs f the cnverter are cnnected t a sngle swtch; therefre, the cnverter requres nly ne extra actve swtch fr each nput unlke ts cunterparts, hence results n reduce element cunt. The prpsed MI tplgy s cmpared wth ts cunterparts cncernng varus parameters. It s analyzed n detal, then ths analyss s valdated by smulatn and a kw prtype based n a battery/ultra-capactr (U) hybrd ESS. Index Terms Batteres, bdrectnal, hybrd energy strage systems, ultra-capactrs, mult-nput cnverter T I. INTRODUTION here s a lt f research cnducted n hybrd electrc vehcles (HEs), electrc vehcles (Es), and plug-n hybrd electrc vehcles (PHEs) due t the envrnmental and ecnmc cncerns [] [3] n whch hybrd energy strage systems (HESSs) have been cmprehensvely studed. The am f a HESS s t make use f strng features f ESS elements whle elmnatng ther weaknesses t reach the perfrmance f an deal ESS element [3]. In rder t create a HESS havng the characterstcs f an deal energy strage unt such as hgh energy/pwer densty, lw cst/weght per unt capacty, and lng cycle lfe, researchers have hybrdzed batteres and ultracapactrs (Us) n [4] [7]. The actve hybrdzatn f the afrementned ESSs, n whch the pwer/current f the ESS can be cntrlled fully, s nly pssble by means f utlzng pwer cnverters. Manuscrpt receved July 3, 5; revsed Octber 5,5, accepted Octber 7, 5. Ths wrk was supprted n part by The Scentfc and Technlgcal Reseach uncl f Turkey (TUBITAK) under Grant 3M88. Authrs are wth Electrcal Engneerng Department, Yldz Techncal Unversty,Esenler, Istanbul, 34, Turkey. (e-mal: fakar@yldz.edu.tr, y.tavlasglu6@gmal.cm, enesugur@yldz.edu.tr, bvural@yldz.edu.tr, aksy@yldz.edu.tr ) Pwer cnverter tplges used n HESS can be classfed nt tw man categres,.e., slated and nn-slated. In [8] [], slated HEES system tplges nclude a transfrmer t ffer galvanc slatn between surces and utput. Nn-slated pwer cnverters are much smpler n terms f desgn and cntrl when cmpared t slated nes. One f the smplest way t buld a nn-slated HESS s t cnnect sme f the surces drectly whle lnkng thers t dc bus va bdrectnal dc-dc cnverters as n [], [3]; hwever, ths methd des nt allw t adjust the dc bus vltage. In addtn, studes n [4] [8] prpse ndvdual dc-dc cnverters fr each nput. Unlke the frmer tplgy, the multple cnverter tplgy structure enables managng the utput vltage; hwever, t s an expensve apprach as t requres multple cnverters. In rder t decrease the cst f multple cnverter tplges, mult nput cnverter (MI) tplges are reprted n the lterature [9] []. As mentned n [9], MIs are nt nly cst-effectve; but als relable, smple, and easy t cntrl. In [], a bdrectnal MI havng a sngle nductr shared by nput surces s prpsed; althugh ths cnverter has the advantage f beng smple, unfrtunately, t des nt allw actve pwer sharng between surces. In [], authrs ffer a mult nput dc-dc/ac bst cnverter whch cntans a bdrectnal prt fr battery strage n addtn t several undrectnal prts fr dc surces; therefre, t can be asserted that ths cnverter des nt ffer flexblty n terms f the number f EES elements. In [], authrs suggest a bdrectnal MI called multplenput pwer electrncs cnverter (MIPE) whse nput prts cnnected t dc bus va half brdges as shwn n Fg.(a); t can successfully cntrl charge/dscharge currents f nput surces whse vltages are requred t be less than the utput vltage. In [3], a mdfed bst cnverter s ntrduced; ths cnverter s cnstructed n a way that the classcal bst cnverter nductr s replaced wth a cupled nductr and a hgh valued capactr; here, the nput current rpple s amed t be elmnated va a sngle swtch drvng the nput surce energy and energy stred n the capactr. Based n ths cncept, a nn-slated undrectnal duble nput dc-dc pwer cnverter s prpsed n [4]. In ths paper, nstead f the hgh valued capactr n [3], the authr utlzed an EES element, namely a U, whch s essentally a capactr wth large capactance. The mtvatn f [4] s t create an pyrght (c) 5 IEEE. Persnal use f ths materal s permtted. Hwever, permssn t use ths materal fr any ther purpses must be btaned frm the IEEE by sendng a request t pubs-permssns@eee.rg (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

2 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T-5-8 Fg.. Bdrectnal mult nput dc/dc cnverters. a) Mutple-nput pwer electrncs cnverter (MIPE). b) Mdfed cascaded buck-bst cnverter (BB) apprach. c) Prpsed cnverter F/U hybrd system t smth F current thanks t U. As dstnct frm the cnverter n [3], the prpsed cnverter n [4] ncludes ne par f a swtch and a dde added t bth nputs hence makes pssble actve pwer sharng between surces as well as cntrl f dc bus vltage level; ths cnverter s then mdfed by replacng ts utput dde wth a swtch n [5] fr battery/u hybrdzatn fr an E applcatn. Ths mdfcatn transfrms the cnverter nt a bdrectnal cnverter that can stre regeneratve brakng energy n battery and U accrdng t ther characterstcs. The paper presented n [5] s the surce f mtvatn f ths wrk. The prpsed bdrectnal nn-slated dc-dc cnverter tplgy n ths wrk and ts cunterparts are shwn n Fg.. In summary, they all requre separate nductrs fr each nput and allw actve pwer sharng between ther nput surces. Ths paper cmpares the prpsed cnverter wth ts cunterparts and gves a detaled analyss alng wth ts verfcatn based n the smulatn and experment results. The system s examned n a battery/u HESS, whch s a wdely used cnfguratn as t can satsfy the requrements fr an E such as hgh pwer/energy densty and mprved battery lfe span [3], [6], [7]. Ths paper s rganzed as fllws. Sectn II cmpares the prpsed cnverter wth ts canddate cunterparts. Sectn III gves the analyss f cnverter peratng mdes. In Sectn I, small sgnal mdelng f the cnverter and cntrller detals are gven. Sectn valdates the analyss by llustratng the smulatn and expermental results. II. A OMPARATIE ANALYSIS In Table I, three tplges gven n Fg. are cmpared cncernng varus parameters. As can be seen frm ths table, MIPE llustrated n Fg. (a) prvdes bst and buck peratns durng prpulsn and regeneratve brakng, respectvely. The tplgy gven n Fg (b) bascally cnssts f mdfed versn f separate cascaded buck-bst cnverters (BB) [8] branches that are cnnected n parallel; when cmpared t MIPE, ths tplgy enables buck peratn as well durng prpulsn. Nte that the mdfed BB s cnsdered here fr the sake f far cmparsn n terms f actve swtch cunt. The prpsed cnverter n ths paper whch s gven n Fg. (c) has als buck/bst capablty durng prpulsn wth the advantage f fewer actve swtch requrement as stated n Table I. Table I als ncludes the swtch stress analyss f examned cnverters. Here t s assumed that each nput surce equally TABLE I OMPARISON OF BIDIRETIONAL MULTI-INPUT ONERTERS Mdfed MIPE BB apprach Prpsed Operatn mde durng prpulsn/reg. brakng Number f actve swtches (n s number f nputs) Swtch stresses durng prpulsn/ reg. brakng ( =,... n ) Overall eff. st case: =36, =36, =48. nd case: =6, =36, =48. S T and T Q and Q Bst/ buck Buck*- bst**/ buck Buck-bst/ buck n 3 n + n l. - ur. - l. ur. l. ur. Durng prp. Durng reg. brakng p. u. / p. u. p. u. / p. u. 96.% α pu.. / pu.. shares the utput pwer n bth drectns. Snce T and Q n the prpsed cnverter handle all the pwer, t seems that these tw swtches suffer frm hgh current stress thus need t be bulker than ther swtches n an applcatn. Hwever, fr a rbust HESS wth a mult-nput cnverter, every branch f that cnverter needs t be desgned cnsderng the pssblty that the asscated nput surce slely undertakes r stres all d S p. u. / p. u. n β p. u. / p. u. / ds p. u. n.. p u n α pu.. / p. u. / d pu % S n p. u. 95.8%@ d T= %@d T= %@d T= % 94.% 94.7% Average 96% 95.7% Durng prp. Durng reg. brakng N/A 95.98% Average %95.89 * α =, β=. ** α =, β= %@d T= %@d T= %@d T= %@ d T= %@d T= %@d T=.75 % % 95.45%@d T= %@d T= %@d T= (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

3 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T f the utput pwer; therefre, t can be declared that all swtches n the prpsed cnverter shuld have same r smlar current ratngs. In Table I, effcency cmparsn f the examned cnverters s gven. In ths wrk, the swtchng frequency s khz and the cnverters have tw nput surces. The prcedure gven n [4] s fllwed t calculate swtchng, cnductn and nductr lsses. Then verall effcences under the lad varatns dependng n EE-5 drvng cycle fr tw dfferent cases are determned. Fr a realstc calculatn, the parameters f cmmercal elements, namely, FDP36NA as pwer swtch, MBR46PT as pwer dde, 5 µh nductrs havng K8E6 magnetc cres and 4 mω seral resstances, are cnsdered. As can be seen frm the results, n the frst case, MIPE s the mst effcent cnverter due t less number f swtches. Durng the prpulsn, the prpsed cnverter exhbts the lwest effcency, partcularly because f ncreasng swtchng and cnductn lsses. It s nterestng that ts effcency changes dependng n the duty cycle f T snce t affects the current stress. Addtnally, durng the regeneratve brakng, the prpsed cnverter s mre effcent than the mdfed BB apprach snce t utlzes fewer actve swtches thus decreases swtchng lsses. In the secnd case, the vltage f ne nput s rased t 6 t evaluate the buck peratn. In ths setup, t s clear that MIPE s nt peratnal. Mrever, ther tw cnverters can stre the regeneratve brakng energy nt nly ne nput surce. Durng the prpulsn, the effcency f prpsed cnverter decreases n cmparsn t the frst case due t the ncreasng current stresses. In a smlar way, the effcency f prpsed cnverter n the secnd case depends n d T. Here the prpsed tplgy s agan slghtly wrse than the ther tplgy n terms f effcency. Durng the regeneratve brakng, bth cnverters have the same effcency snce they have same equvalent crcut n the secnd setup. Overall, the prpsed cnverter exhbts slghtly wrse effcency than thers n bth cases n accunt f a reductn n actve swtch cunt. Nte that n the effcency analyze abve, MIPE, mdfed BB apprach, and the prpsed cnverter have 4, 6 and 4 actve swtches, respectvely. III. THE ANALYSIS OF THE PROPOSED ONERTER The prpsed mult-nput bdrectnal dc-dc cnverter s analyzed n the case that t has tw nputs as llustrated n Fg.. As can be seen, the cnverter has fur pwer swtches wth nternal ddes, tw pwer ddes and tw nductrs. S, S, Fg.. Prpsed mult-nput cnverter wth tw nputs Fg. 3. Typcal wavefrms n the dschargng mde T, and Q are pulse wdth mdulatn (PWM) cntrlled swtches wth d S, d S, d T, and d Q duty cycles, respectvely. The prpsed cnverter has manly tw dfferent peratn mdes. The frst peratn mde s called dschargng mde. In ths mde, the utput s fed by nput surces accrdng t states f S, S and T. Pwer ddes D and D perate n cmplementary manner wth S and S, respectvely. The secnd peratn mde s called chargng mde. In the chargng mde, by cntrllng Q, regeneratve brakng energy charges ESSs dependng n ther vltage levels. Nte that, f there s need fr an ptn whether r nt t charge ne f the ESSs, a sld-state swtch (e.g. a reverse cnnected MOSFET) can be added t the asscated cnverter nput. In the chargng mde, D and D are always OFF whle the bdy dde f T carres the nductr currents when Q s OFF. In analyss, t s assumed that nductrs, bdy ddes f swtches, and pwer ddes are deal whle the swtch turn-on resstances (R dsn) and utput capactr equvalent seral resstance (R ) are taken nt accunt; n addtn, the cnverter perates n cntnuus cnductn mde (M). A. Dschargng Mde In the dschargng mde, ne swtchng cycle cnssts f fur subntervals. Typcal wavefrms n the dschargng mde are llustrated n Fg. 3. In ths fgure, t s bvus that d T<d S<d S accrdng t the assumptn that < <, where s the frst nput vltage, s the secnd nput (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

4 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T Fg. 4. Equvalent crcuts n the dschargng mde. (a) Swtchng subnterval : <t<(-d T)T s. (b) Swtchng subnterval : (-d T)T s<t<d ST s. (c) Swtchng subnterval 3: d ST s<t<d ST s. (d) Swtchng subnterval 4: d ST s<t<t s. vltage, and s the utput vltage. The relatnshp between the vltage levels and duty cycles wll be explaned n detal later n. Steady state equvalent crcuts n fur subntervals are demnstrated n Fg. 4. Swtchng subnterval [<t<(-d T)T s]: S and S are turned ON whle S s turned OFF. D and D are OFF as shwn n Fg. 4(a). Due t the negatve vltages acrss nductrs, ther currents decrease. In addtn, the current thrugh the bdy dde f Q s equal t the sum f nductr currents, and t charges the utput capactr. Swtchng subnterval [(-d T)T s<t<d ST s]: Accrdng t Fg. 4(b), at t=(-d T)T s, T s turned ON whle S and S are stll cnductng, and ddes D and D are stll OFF. In ths subnterval, nductrs start t be charged due t pstve vltage whle the utput capactr dscharges t feed the lad. Swtchng subnterval 3 [d ST s<t<d ST s]: At t= d ST s, S s turned OFF whereas S and T are stll ON. In ths subnterval, D starts t cnduct as shwn n Fg. 4(c). As can be seen, L current starts t decrease slwly due t the turn-n resstance f T. Besdes, L cntnues t be charged, D s stll OFF, and utput capactr stll dscharges. Swtchng subnterval 4 [d ST s<t<t s]: Last swtchng subnterval s ntated by turnng OFF S at t=d ST s as demnstrated n Fg. 4(d). Bth D and D becme cnductng and bth nductr currents are decreasng because f the turnn resstance f S. Mrever, the utput capactr current s stll negatve. Fnally, equatns that shw vltage varatns f L and L n the dschargng mde can be wrtten as gven n () and (), respectvely. v ( t) v ( t) RdsnL ( t), < t < ( dt ) Ts () vl ( t) = v ( t) Rdsn ( L ( t) + L ( t) ), ( dt ) Ts < t < dsts Rdsn ( L ( t) + L ( t) ), dsts < t < Ts ( ) ( ) ( ), ( ) ( ) ( ( ) ( )), ( ) dsn ( L ( ) L ( )), S s s v t v t RdsnL t < t < dt Ts v ( t) = v t R t + t d T < t < d T R t + t d T < t < T L dsn L L T s S s The utput capactr current and utput vltage varatns dependng n the state f the S can be derved as gven n (3) and (4). () ( ( ) ( )) R L t + L t v ( t), < t < ( dt ) Ts R + Rc R + R (3) c ( t) = v ( t), ( dt ) Ts < t < T s R + Rc RRc R ( L ( t) + L ( t) ) + v ( t), < t < ( dt ) Ts R + Rc R + R (4) c v ( t) = R v ( t), ( dt ) Ts < t < Ts R + Rc Based n small rpple apprxmatn and nductr vltsecnd-balance [9], by utlzng () and (), the relatnshp between the utput vltage and surce vltages at steady state can be btaned as gven n (5) by neglectng R dsn. d d = S S = (5) dt dt Accrdng t (5), the cnverter perates at an equlbrum pnt where duty cycles have fllwng relatnshp: d d S = (6) S B. hargng Mde In the chargng mde, Q s cntrlled and T s kept OFF n rder t stre regeneratve brakng energy nt the energy strage unts whle regulatng the utput vltage. As expressed, chargng nly ne ESS can be realzed by addng a sld-state swtch t the cnverter nput. Therefre, n ths Fg. 5. Typcal wavefrms n the chargng mde (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

5 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T Fg. 6. Equvalent crcuts n chargng mde. (a) Swtchng subnterval : <t<d QT s. (b) Swtchng subnterval : d QT s<t<t s. analyss, t s assumed that the regeneratve brakng energy charges nly the frst nput. Furthermre, snce the prpsed cnverter perates n buck mde n the chargng mde, the utput vltage s assumed t be hgher than. Fg. 5 llustrates the steady state wavefrms n the chargng mde. Accrdng t ths fgure, ne swtchng cycle s cmpsed f tw subntervals. Asscated equvalent crcuts are shwn n Fg.6 where reg(t) s the current surce that represents the regeneratve brakng energy. In ths mde, the nductr current s negatve snce the surce s charged. Swtchng subnterval [<t<d QT s]: Frm Fg. 6(a) ne can see that, when Q s turned ON, the bdy dde f S becmes OFF. Because f negatve vltage acrss L, ts current ncreases (negatvely). Mrever, the current f the utput capactr s negatve snce t dscharges. Swtchng subnterval [d QT s<t<t s]: At t=d QT s, Q s turned OFF. Therefre, the current f L nw flws thrugh T bdy dde as llustrated n Fg. 6(b). In ths subnterval, the nductr current decreases due t the surce vltage acrss t. Addtnally, the current f utput capactr changes ts drectn and becmes pstve. Based n the analyss abve, the equatns fr the L vltage, utput capactr current, and utput vltage n tw swtchng subntervals can be gven as gven n (7), (8), and (9), respectvely. v L ( t) ( ) ( ) ( ) ( ), v t v t RdsnL t, < t < dqts = v t d T < t < T Q s s (7) I. SMALL SIGNAL MODELING AND ONTROLLER ONSIDERATIONS A. Small Sgnal Mdelng In [3], authrs prpse the unfed cntrller cncept. Accrdng t ths cncept, a sngle cntrller can be used fr buck mde (chargng) and bst mde (dschargng) f a bdrectnal cnverter; and that cntrller can be desgned accrdng t ne f the transfer functns f these tw peratng mdes. Therefre, n ths paper, a classcal bst cnverter s analyzed fr the chargng mde. Smlarly, swtch turn-on resstance f ths bst cnverter and the equvalent seral resstance f the utput capactr are taken nt accunt, whle nductr resstance and vltage drps n ddes are gnred. Snce related equatns t ths nn-deal bst cnverter can be derved easly n a smlar way f dervng ()-(4) and (7)-(9), they are nt gven here. A small sgnal ac mdel n matrx frm can be gven n () where A, B, and are matrces cmprsed f cnstants. ( ) dˆ ( ) ˆ ( ) Axˆ s = B s + v s () In (), x(s), d(s), and v(s) dente the state varables, duty cycles, and nput vltages, respectvely, whch cnsst f dc cmpnents (X, D, and ) and small perturbatns ( xˆ( s ), d ˆ( s ), and vˆ( s ) ) as shwn n (). x = X + xˆ ; d = D + d ˆ ; v = + v ˆ. () In rder t btan A, B, and matrces n (), frst () s appled t ()-(4) and t the derved equatns fr nn-deal bst cnverter. By applyng Laplace transfrm t these equatns, they are averaged ver ne swtchng cycle and secnd rder ac terms are neglected [9]. Fnally, the small sgnal ac mdels n matrx frm f the cnverter n the dschargng mde and chargng mde are derved as n (3) and (4), respectvely. ( t) ( ) ( ) ( ), ( ( ) ( )) c ( ) ( ) ( ), L t + reg t, < t < dqts = t d T < t < T reg Q s s L t + reg t R + v t, < t < dqts v ( t) = reg t Rc + v t dqts < t < Ts (8) (9) Applyng t small rpple apprxmatn and nductr vltsecnd-balance t (7), ne can fnd the relatnshp between the utput vltage ( ) and surce vltage ( ) at steady state as n () by neglectng R dsn. = () dq Fg. 7. Overall cntrl strategy (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

6 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T ( T S ) dsn dsn ( T ) R sl + ( D + D ) R ( D ) sl + D + D R R D R R A = ( DT ) ( DT ) s + R + R R + R R R + RR RR R ( DT ) ( DT ) R + R R + R R + R DS D S = dsn T S dsn T, xˆ ˆ ˆ vˆ vˆ, ˆ ( ) c L L = dˆ T d s = dˆ S s dˆ S sl + D R D R A = ( DQ ) s + R + R R R + RR R ( DQ ) R + R R + R ( ), vˆ ( ) Q dsn Q vˆ vˆ =, B =IL R + R I L, B ( I + I ) I R I R L dsn L dsn I R I R L dsn L dsn = L L R + R ( I L + I L ) R RR R + R. (3) R RR R + R, = ˆ L x s =vˆ c s vˆ, ˆ( ) ( ), dˆ = dˆ Q ; vˆ = vˆ.(4), B. ntrl Strategy A battery/u HESS s cnsdered here n rder t test the prpsed cnverter, and the cntrl strategy whch s demnstrated n Fg. 7 s appled t system. In ths fgure, the pwer sde represents the prpsed pwer cnverter where T dentes current transducers. In addtn, the cntrl sde s the platfrm where currents and vltages are sensed and develped cntrl strategy s carred ut. In the cntrl sde, frst f all, the peratn mde s determned by checkng the utput vltage (v ): the dschargng mde s actvated when v s lwer than v * - and the chargng mde s actvated when v s greater than v * +, where v * s the utput vltage reference and s a defned vltage level. In the dschargng mde, t s amed t realze actve pwer sharng between battery and U. In rder t acheve ths, a PI cntrller adjusts the duty cycle f S t cntrl the battery pwer whle anther PI cntrller adjusts the duty cycle f S fr dc bus regulatn. In ths way, U pwer s cntrlled ultmately snce battery and U share the utput pwer demand. The battery current reference s calculated t assure that battery prvdes all f the pwer demand by lad prvdng that t des nt exceed A. In the case that battery pwer s nt enugh t regulate dc bus, U undertakes the necessary extra pwer. Frm (5), ne can see that ncreasng d T expands the ESS vltage range. Hwever, t may result n reductn n the effcency as hghlghted n the effcency analyss. Therefre, n the dschargng mde, d T s kept cnstant at a reasnable value,.5, and uncntrlled fr the sake f cntrl smplcty. In the chargng mde, Q duty cycle s regulated by a PI cntrller t keep the utput vltage at ts reference whle keepng T always OFF. It s hghlghted that the vltage errr n the chargng mde s calculated by v -v * snce the nductr current changes ts drectn.. ntrller Desgn In rder t desgn PI cntrllers shwn n Fg. 7, frst f all asscated transfer functns need t be knwn. Transfer functn matrces can be btaned by slvng small sgnal mdel n () fr each peratn mde as gven n (5). ˆx ( ) ˆ s A Bd A vˆ = + (5) If the effect f crss-cuplng transfer functns n (5) s assumed t be neglgble, decupled transfer functn can be derved as n [], [3] [33]. Therefre, by lettng ther perturbatns be zer n (5), cntrl-t-nductr current transfer functn and cntrl-t-utput transfer functn fr the dschargng mde and cntrl-t-utput transfer functn fr the chargng can be fund. After ths step, cntrl-t-battery current transfer functn can be derved as gven n (6). ˆ ˆ bat L = D + I (6) L dˆ dˆ S S The generalzed frm f a secnd-rder transfer functn can be shwn as n (7). Usng (5), the ceffcents n (7) fr bth peratn mdes can be calculated as gven n Table II and Table III. G b + b s + b s = a + a s + a s (7) PI cntrllers are used t mprve phase margns and t have reasnable cut-ff frequences. A PI cntrller transfer functn s gven (8) (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

7 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T K G = K + PI p (8) s In ths wrk, PI cntrller gans are determned as shwn n Table I by usng PID Tunng tl n Matlab. Fg. 8 and Fg. 9 demnstrate the uncmpensated and cmpensated system bde plts fr the dschargng and chargng mdes, respectvely. Frm these fgures t can be seen that, all f the cmpensated systems have pstve phase margns hence they are stable [9]. Mrever, decreased cut-ff frequences result n lw gan n hgh frequences; therefre, ncrease the rbustness [7]. Nte that parameters gven n Table are utlzed t derve bde plts and desgn the cntrllers. llustrated n Fg.. As can be seen frm ths fgure, the cnverter cnssts f a pwer bard and a cntrl bard. The pwer bard ncludes the pwer elements such as, swtches, gate drvers, ddes, wth specfcatns gven n Table I. In Table I, d T s lmted between.4 and.6 t assure that the cnverter can wrk n bth drectns accrdng t the nput and utput vltage ranges determned cncernng the ratng f pwer elements. The cntrl bard ncludes Texas Instrument TMS3F8335 DSP as a cntrller and an nterface t prgram t drectly va a USB prt f a cmputer.. SIMULATION AND EXPERIMENTAL RESULTS In rder t verfy the analyss and evaluate the dynamc perfrmance f the cnverter, a kw prttype s bult as TABLE II DISHARGING MODE TRANSFER FUNTION OEFFIIENTS ˆ dˆ ( s ) vˆ dˆ ( s) bat S ' a + ( + ) D R D D R T T S dsn ' a + ( + ), ( + T S)( + dsn T ) L R R D D R D R R a ( + ), D I R I a b ( ) + S bat L dsn L b ( ) S bat L dsn L R R L D ( I R ) R + R + I a S ( ) D I R ' T U L dsn R R + R + R R + R ( )( ) D I R R R ' T U L dsn b L I a TABLE III HARGING MODE TRANSFER FUNTION OEFFIIENTS vˆ dˆ ( s ) ' a D Q R + DQ Rdsn a L + ( R + R ) DQ ( R + D dsn Q ) Q Fg. 8. Bde plts f dschargng mde: (a) ˆ ˆ ( s ) d S S ( s ), (b). vˆ dˆ ( s ). S ( R + R ) L a b D Q ' R I R R L dsndq ' b D R R I R Q L ( L + D R R Q dsn ) I R R L b L TABLE I ONTROLLER PARAMETERS Dschargng mde hargng mde G ( s ) G ( s ) G ( s ) PI PI PI 3 K p K Fg. 9. Bde plt f chargng mde: vˆ dˆ ( s ) Q (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

8 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T TABLE BODE PLOT PARAMETERS 48 bat = U 36 L = L 5µH R 4.6 Ω R 3.8 mω dsn R S 3 mω D.5 D.67 S D.5 Q TABLE I PROTOTYPE POWER BOARD SPEIFIATIONS d T range.4-.6 Output vltage range 36-6 Input vltage range -4 Peak pwer kw Swtchng frequency khz Output capactr µf, and 3 mω ESR Pwer Swtches FDP36NA Swtch ratngs / 8 A Pwer ddes MBR46PT Ddes ratngs 6 /8 A Gate drvers FAN73933 and FAN737 Gate vltages 5 Inductrs Kl-Mu re, 5 µh, 4 mω ESR Fg.. kw prttype f the cnverter. The prpsed cnverter s tested fr a battery/u hybrd system as shwn n Fg.. In ths fgure, the battery bank cnssts f three separate batteres n seres thus t has 36 nmnal vltage whle U has 48 rated vltage and 65F rated capacty. A mtr-generatr set (fr regeneratve brakng energy) and a dc lad bank are cnnected t the utput f the cnverter s as t attan the desred lad prfle. In ths setup, a rectfer and an auttransfrmer are utlzed t energze dc generatr feld wndng. Furthermre, an scllscpe and a pwer analyzer are used t retreve expermental results. Fgs. -4 demnstrate the measured steady state wavefrms fr the dschargng mde when the utput pwer s set t 4 W. In ths test, the battery current s cntrlled n a way that ts pwer s W whle U s cntrlled t keep the dc bus vltage at 48. It can be seen that these fgures valdate the theretcal analyss shwn n Fg.3. Fg.. Expermental setup Gate sgnals and related dran-surce sgnals f each swtch are gven n Fg.. In Fg., ne can see that the duty cycle f T s.5 accrdng t the cntrl strategy. Mrever, gate sgnals f S (ν GS-S) and S (ν GS-S) verfy the analyss: ν GS-S duty cycle (~.73) becmes hgher than ν GS-S duty cycle (~.66) due t the dfference between battery and U vltages. Fg.3 llustrates L and L vltage and current varatns. Inductr vltages and nductr currents vary accrdng t states f swtches. Mrever, bth nductr currents are pstve snce bth energy strage elements dscharge. The vltage and current f Q bdy dde are llustrated n Fg.4. Frm Fg.4 and Fg., ne can see that when T s OFF, the dde starts t cnduct as can be understd frm ts pstve current. nversely, when S s ON, the dde becmes OFF thus ts current ges t zer. Fgs. 5-6 llustrate the measured steady state wavefrms when the cnverter perates n the chargng mde. In ths test, by cntrllng Q swtch, the utput vltage s agan kept at 48 whle U s charged under 4W cnstant pwer. Based n these fgures, t can be asserted that the expermental results match the theretcal wavefrms gven n Fg. 4. Fg. 5 shws the expermental results f Q termnal vltages at steady state. In Fg.5, the duty cycle f Q s abut.8 as expected accrdng t () whch explans the relatnshp between the duty cycle f Q, U vltage (~4), and the utput vltage. Fgs. 5-6 llustrate the measured steady state wavefrms when the cnverter perates n the chargng mde. In ths test, by cntrllng Q swtch, the utput vltage s agan kept at 48 whle U s charged under 4W cnstant pwer. Based n these fgures, t can be asserted that the expermental results match the theretcal wavefrms gven n Fg. 4. Fg. 5 shws the expermental results f Q termnal vltages at steady state. In Fg.5, the duty cycle f Q s abut.8 as expected accrdng t () whch explans the relatnshp between the duty cycle f Q, U vltage (~4), and the utput vltage In Fg. 6, the vltage and current varatns f L are demnstrated. It can be ntced that the nductr current s (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

9 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T negatve snce U s charged. Mrever, when Q s turned ON, the vltage f the nductr becmes negatve thus ts current ncreases (negatvely); cnversely, turnng t OFF makes the vltage f the nductr equal t U vltage and decreases ts current (negatvely). Fg. 7 llustrates the prpsed cnverter effcency curves fr the dschargng and chargng mdes whch are btaned by pwer analyzer. In the dschargng mde, the pwer f ne surce s set t W whle ther surce s utlzed t cmpensate the lad demand. Besdes, n the chargng mde, dc bus s regulated when adjustng the chargng pwer f the nput surce. Fg. 7 clearly ndcates that n bth mdes cnverter effcency s hgher than 93% under the whle pwer range. Furthermre, by cmparng effcency curves, ne can see that the chargng mde effcency s hgher than the dschargng mde effcency due t the dfference between the number f cntrlled swtches n these tw mdes. Fg. 3. Expermental wavefrms f nductr vltages and currents n the dschargng mde: L: ν L [h: 4 /dv], L [h3: 5 A/dv], L: ν L [h: 4 /dv], L [h4: 5 A/dv]. Tme base: µs/dv (a) (b) Fg. 4. Expermental wavefrms f Q swtch bdy dde vltage and current n the dschargng mde: ν Q-D [h: /dv], Q-D [h3:a/dv]. Tme base: µs/dv (c) Fg.. Expermental wavefrms f swtches gate-surce and dran-surce vltages n dschargng mde: (a) S : ν GS-T [h: 5/dv], ν DS-T [h: 3/dv). (b) S : ν GS-S [h: 5/dv], ν DS-S [h: /dv]. (c) S : ν GS-S [h: 5/dv], ν DS-S [h: /dv]. Tme base: µs/dv. Fg. 5. Expermental wavefrms f swtch Q gate-surce and dran-surce vltages n the dschargng mde: (a) ν GS-Q [h: 5/dv], ν DS-Q [h: /dv). Tme base: µs/dv (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

10 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T-5-8 Fg.6. Expermental wavefrms f nductr vltage and current n the chargng mde: ν L [h: /dv], L [h3: 3A/dv]. Tme base: µs/dv. Fg.8. Nrmalzed EE-5 drvng cycle and ts analyzed sectn cmpensatng the lad demand. Addtnally, U current becmes negatve when t stres regeneratve brakng energy. Fg. hghlghts the nput surce vltages. Ths fgure ndcates that battery vltage as well as U vltage n the experment and n the smulatn change n a smlar way. Because f ts equvalent seral resstance, battery vltage decreases substantally when t gves pwer. In addtn t that, U vltage decreases when t cmpensates lad demand and ncreases when t s charged. Fg.7. Effcency curves In rder t test the dynamc perfrmance f the system, a lad prfle s chsen accrdng t nrmalzed EE-5 drvng cycle [5]; the analyzed sectn f ths drvng cycle s demnstrated n Fg. 8. Ths perd s chsen t examne the system under maxmum pwer demand and n the presence f regeneratve brakng energy. The lad prfle s created by utlzng dc lad bank and dc generatr whch are shwn n Fg.. Mrever, smulatns are carred ut va develped PSIM swtchng mdel ncludng swtch turn-on resstances and utput capactr equvalent seral resstance; n the smulatn, battery and U are mdeled as n [5]. Nte that n bth cases battery and U ntal vltages are set t 38 and 33.6 (7% state-f-charge), respectvely. Fgs. 9- cmpare the expermental and smulatn results. In Fg. 9, the utput vltage and utput current are shwn. Here, t s clear that the utput vltage s successfully regulated at 48 n bth cases. Mrever, the fact that utput current n the experment and smulatn match well ndcates that the utput pwer s adjusted as ntended by lad bank and generatr Fg. shws the battery and U average current. Frm Fg., t can be ntced that the battery current varatns n the experment and n the smulatn appear smlar. In bth cases maxmum battery current s lmted t A due t the cntrl strategy; at ths nstant, U current s ncreased fr Fg.9. Dynamc test results: a) utput vltage, b) utput current. Fg.. Dynamc test results: a) battery current, b) U average current (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

11 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T-5-8 Fg.. Dynamc test results: a) battery vltage, b) U vltage. I. ONLUSIONS In ths wrk, a new mult nput nn-slated bdrectnal dc/dc cnverter fr hybrd energy strage systems t be used n electrc vehcle applcatns has been prpsed. A detaled cmparsn f the prpsed cnverter and tw cnventnal cnverters has been presented. The peratn mdes f the prpsed cnverter have been analyzed thrughly and small sgnal ac mdels fr these mdes have been btaned. Fr a battery/u hybrd system, asscated transfer functns have been derved fr cntrllng battery current and regulatng the utput vltage. A kw labratry prttype f the prpsed cnverter tplgy has been desgned and develped. Utlzng derved transfer functns, PI cntrllers have been desgned n rder t acheve prper phase margns and cut-ff frequences. Expermental fndngs have revealed that the prttype cnverter effcency s greater than 93% n bth peratn mdes. The analyss has been valdated thrugh ths prttype, and by cmparng the expermental and smulatns results, dynamc perfrmance f the cnverter has been examned under a lad prfle btaned frm a well knwn drvng cycle, namely EE-5. Fr a future wrk, t s amed t buld a full scale battery/u hybrd system based n the prpsed cnverter and test t n a cncept electrc vehcle. REFERENES [] S. M. Lukc, R.. Bansal, F. Rdrguez, and A. Emad, Energy Strage Systems fr Autmtve Applcatns, IEEE Trans. Ind. Electrn., vl. 55, n. 6, pp , Jun. 8. [] O.. Onar, J. Kbayash, and A. Khalgh, A Fully Drectnal Unversal Pwer Electrnc Interface fr E, HE, and PHE Applcatns, IEEE Trans. Pwer Electrn., vl. 8, n., pp , Dec. 3. [3] A. Khalgh, Battery, Ultracapactr, Fuel ell, and Hybrd Energy Strage Systems fr Electrc, Hybrd Electrc, Fuel ell, and Plug-In Hybrd Electrc ehcles: State f the Art, IEEE Trans. eh. Technl., vl. 59, n. 6, pp ,. [4] S. Dusmez, A. Hasanzadeh, and A. Khalgh, mparatve Analyss f Bdrectnal Three-Level D D nverter fr Autmtve Applcatns, IEEE Trans. Ind. Electrn., vl. 6, n. 5, pp , May 5. [5] J. Shen, S. Dusmez, and A. Khalgh, Optmzatn f Szng and Battery ycle Lfe n Battery/Ultracapactr Hybrd Energy Strage Systems fr Electrc ehcle Applcatns, IEEE Trans. Ind. Infrmatcs, vl., n. 4, pp., Nv. 4. [6] S. Lu, K. A. rzne, and M. Ferdws, A New Battery/Ultracapactr Energy Strage System Desgn and Its Mtr Drve Integratn fr Hybrd Electrc ehcles, IEEE Trans. eh. Technl., vl. 56, n. 4, pp , Jul. 7. [7] S. Dusmez and A. Khalgh, A Supervsry Pwer-Splttng Apprach fr a New Ultracapactr Battery ehcle Deplyng Tw Prpulsn Machnes, IEEE Trans. Ind. Infrmatcs, vl., n. 3, pp , Aug. 4. [8] Z. Dng,. Yang, Z. Zhang,. Wang, and S. Xe, A nvel sftswtchng multprt bdrectnal dc-dc cnverter fr hybrd energy strage system, IEEE Trans. Pwer Electrn., vl. 9, n. 4, pp , 4. [9] H. Zhu, T. Bhattacharya, D. Tran, T. S. T. Sew, and A. M. Khambadkne, mpste energy strage system nvlvng battery and ultracapactr wth dynamc energy management n mcrgrd applcatns, IEEE Trans. Pwer Electrn., vl. 6, n. 3, pp ,. [] S. Dusmez, S. Member, X. L, S. Member, B. Akn, and S. Member, A New Multnput Three-Level D / D nverter, vl. 3, n., pp. 3 4, 6. [] K. lak, E. Asa, M. Bjarsk, and D. zarkwsk, Asymmetrcal Duty-ycle ntrl f a Nvel Mult- Prt LL Resnant nverter, vl. 3, n. 4, pp , 5. [] S. Lu, K. A. rzne, and M. Ferdws, A Unque Ultracapactr Drect Integratn Scheme n Multlevel Mtr Drves fr Large ehcle Prpulsn, IEEE Trans. eh. Technl., vl. 56, n. 4, pp , Jul. 7. [3] M. B. amara, H. Gualus, F. Gustn, A. Berthn, and B. Daky, D / D nverter Desgn fr Supercapactr and Battery Pwer Management n Hybrd ehcle Applcatns Plynmal ntrl Strategy, IEEE Trans. Ind. Electrn., vl. 57, n., pp ,. [4] S. K. Kllmalla, M. K. Mshra, and N. L. Narasamma, Desgn and Analyss f Nvel ntrl Strategy fr Battery and Supercapactr Strage System, IEEE Trans. Sustan. Energy, vl. 5, n. 4, pp , Oct. 4. [5] A. Tan, M. B. amara, and B. Daky, Energy management based n frequency apprach fr hybrd electrc vehcle applcatns: Fuelcell/lthum-battery and ultracapactrs, IEEE Trans. eh. Technl., vl. 6, n. 8, pp ,. [6] M. Zand, A. Payman, J. Martn, S. Perfederc, B. Davat, and F. Mebdy-Tabar, Energy Management f a Fuel ell / Supercapactr / Battery Pwer Surce fr Electrc ehcular Applcatns, IEEE Trans. eh. Technl., vl. 6, n., pp ,. [7] A. Payman, S. Perfederc, F. Mebdy-Tabar, and B. Davat, An Adapted ntrl Strategy t Mnmze D-Bus apactrs f a Parallel Fuel ell/ultracapactr Hybrd System, IEEE Trans. Pwer Electrn., vl. 6, n., pp ,. [8] A. S. Samsr and A. H. M. Yatm, Implementatn f dynamc evlutn cntrl f bdrectnal D-D cnverter fr nterfacng ultracapactr energy strage t fuel-cell system, IEEE Trans. Ind. Electrn., vl. 57, n., pp ,. [9] F. Nejabatkhah, S. Danyal, S. H. Hssen, M. Sabah, and S. M. Napur, Mdelng and cntrl f a new three-nput dc-dc bst cnverter fr hybrd P/F/battery pwer system, IEEE Trans. Pwer Electrn., vl. 7, n. 5, pp , May. [] A. Khalgh, J. a, and Y.-J. Lee, A Multple-Input D D nverter Tplgy, IEEE Trans. Pwer Electrn., vl. 4, n. 3, pp , Mar. 9. [] S. Danyal, S. H. Hssen, and G. B. Gharehpetan, New Extendable Sngle-Stage Mult-nput D D/A Bst nverter, IEEE Trans. Pwer Electrn., vl. 9, n., pp , Feb. 4. [] L. Sler, A. Ldzz, and J. A. Pml, Desgn f Multple-Input Pwer nverter fr Hybrd ehcles, IEEE Trans. Pwer Electrn., vl., n. 5, pp. 7 6, Sep. 5. [3] W. G. Dunfrd and K. Mauch, Mdfed bst cnverter wth cntnuus nductr current mde and rpple free nput current, n PES Recrd. 7th Annual IEEE Pwer Electrncs Specalsts nference, 996, vl., pp [4] B. ural, F/U hybrdzatn fr dynamc lads wth a nvel duble nput D D cnverter tplgy, Int. J. Hydrgen Energy, vl. 38, n., pp. 3, Jan. 3. [5] F. Akar and B. ural, Battery/U hybrdzatn fr electrc vehcles va a nvel duble nput D/D pwer cnverter, n 3 3rd Internatnal nference n Electrc Pwer and Energy nversn (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.

12 Ths artcle has been accepted fr publcatn n a future ssue f ths jurnal, but has nt been fully edted. ntent may change prr t fnal publcatn. tatn nfrmatn: DOI.9/TT , IEEE Transactns n ehcular Technlgy T-5-8 Systems, 3, pp. 4. [6] R. arter, A. ruden, and P. J. Hall, Optmzng fr effcency r battery lfe n a battery/supercapactr electrc vehcle, IEEE Trans. eh. Technl., vl. 6, n. 4, pp ,. [7] A. Kuperman, I. Aharn, S. Malk, and A. Kara, Desgn f a semactve battery-ultracapactr hybrd energy surce, IEEE Trans. Pwer Electrn., vl. 8, n., pp , 3. [8] M. Anun, M. Ordnez, I. Galan, and G. Ogger, Bdrectnal pwer flw wth cnstant pwer lad n electrc vehcles: A nn-lnear strategy fr Buck+Bst cascade cnverters, 4 IEEE Appl. Pwer Electrn. nf. Exp. - APE 4, pp , 4. [9] R. W. Ercksn and D. Maksmvc, Fundamentals f Pwer Electrncs, nd ed. Sprnger,. [3] J. Zhang, J. S. La, and W. Yu, Bdrectnal D-D cnverter mdelng and unfed cntrller wth dgtal mplementatn, nf. Prc. - IEEE Appl. Pwer Electrn. nf. Exp. - APE, vl., pp , 8. [3] D. Smayajula and M. Ferdws, Small-sgnal mdelng and analyss f the duble-nput buckbst cnverter, nf. Prc. - IEEE Appl. Pwer Electrn. nf. Exp. - APE, pp. 5,. [3]. Mummad and K. K. Sawant, ntrl f mult-nput ntegrated buck-bst cnverter, IEEE Reg. llq. 3rd Int. nf. Ind. Inf. Syst. IIIS 8, pp. 6, 8. [33] W. Jang and B. Fahm, Actve current sharng and surce management n fuel cellbattery hybrd pwer system, IEEE Trans. Ind. Electrn., vl. 57, n., pp ,. Furkan Akar (S ) was brn n Kcael, Turkey, n 986. He receved the B.Sc. degree n electrcal and electrncs engneerng frm Mersn Unversty, Mersn, Turkey, n 9, the M.Sc. degree n electrcal engneerng frm Flrda State Unversty, Tallahassee, FL, USA, n. He s currently a Ph.D. canddate at Department f Electrcal Engneerng, Yldz Techncal Unversty, Istanbul, Turkey. Hs feld f research ncludes cntrl f the swtched reluctance machne, renewable energy surces, dc-dc cnverters, electrc vehcles, and hybrd energy strage systems. Yakup Tavlasglu was brn n Erzurum, Turkey, n 987. He receved the B.Sc. degree n electrncs engneerng frm Gebze Insttute f Technlgy, Kcael, Turkey, n. He s currently a M.Sc. student at Department f Electrcal Engneerng, Yldz Techncal Unversty, Istanbul, Turkey. Hs research nterests are phtvltac systems, dc-dc cnverters, electrc vehcles, and hybrd systems. Enes UGUR (S ) receved the B.Sc. degree n electrcal engneerng frm Istanbul Techncal Unversty n 8 and the M.Sc. degree frm Yldz Techncal Unversty, Istanbul, Turkey, n. He s currently a Ph.D. student at Department f Electrcal Engneerng, Yldz Techncal Unversty. Hs research nterests nclude fuel-cells, electrc vehcles, dc-dc cnverters, energy management strateges fr renewable energy systems, and fault dagnss f wde-bandgap devces. Bulent URAL receved the B.Sc., M.Sc. and Ph.D. degrees frm Yldz Techncal Unversty, Istanbul, Turkey, n 4, 7, and, respectvely, all n electrcal engneerng. He s an Asscate Prfessr and drectr f Electrc ehcle Technlges Labratry at Yldz Techncal Unversty. Hs research nterests are; embedded cntrl systems, pwer electrncs applcatns n alternatve/renewable energy systems and electrc vehcles, smart grd, pwer hardware-nthe-lp smulatns. He s authr and cauthr f mre than 35 jurnal and cnference papers. Ismal AKSOY was brn n lgne, Germany, n 977. He receved the B.Sc., M.Sc., and Ph.D. degrees n electrcal engneerng frm Yldz Techncal Unversty, Yldz, Turkey, n 999,, and 7, respectvely. He was a Research Assstant frm 999 t 8 n the Department f Electrcal Engneerng, Yldz Techncal Unversty. Snce 4 he has been wrkng as an Asscate Prfessr n the Department f Electrcal Engneerng at Yldz Techncal Unversty. He has publshed ver jurnal and cnference papers n the area f pwer electrncs. He was als emplyed n three research prjects cncernng pwer electrncs. Hs research subjects are pwer factr crrectn, swtchng pwer supples, hgh frequency pwer cnversn, and actve and passve snubber cells n pwer electrncs (c) 5 IEEE. Persnal use s permtted, but republcatn/redstrbutn requres IEEE permssn. See fr mre nfrmatn.