Experimental verification of the Chua s circuit designed with UGCs

Transcription

1 Experimental verification of the Chua s circuit designed with UGCs C. Sánchez-López a), A. Castro-Hernández, and A. Pérez-Trejo Autonomous University of Tlaxcala Calzada Apizaquito S/N, Apizaco, Tlaxcala, 90300, Mexico. a) cslopez@ingenieria.uatx.mx Abstract: In this letter, experimental results of the Chua s circuit designed with unity-gain cells (UGCs) are reported. The UGCs have been implemented with the commercially available integrated circuit (IC) AD844AN from Analog Devices. Parasitic elements of the UGCs are taken in account to design suitable the grounded inductor and the nonlinear resistor (NR) into Chua s circuit. Experimental results are given, showing close agreement with theoretical conclusions. Keywords: Chua s circuit, unity-gain cells, double-scroll Classification: Integrated circuits References [1] T. Matsumoto, L. O. Chua, and M. Komuro, The Double Scroll, IEEE Trans. Circuits Syst. I, vol. 32, no. 8, pp , [2] J. M. Cruz and L. O. Chua, A CMOS IC Nonlinear resistor for Chua s Circuit, IEEE Trans. Circuits Syst. I, vol. 39, no. 1, pp , [3] R. Michel and P. Kennedy, Robust Opamp Realization of Chua s Circuit, Frenquez, vol. 46, no. 3-4, pp , [4] A. S. Elwakil and M. P. Kennedy, Improved Implementation of Chua s Chaotic Oscillator Using Current Feedback Op Amp, IEEE Trans. Circuits Syst. I, vol. 47, no. 1, pp , Jan [5] A. S. Elwakil and M. P. Kennedy, Chua s Circuit Decomposition: A Systematic Design Approach for Chaotic Oscillators, J. Franklin Inst., vol. 337, no. 1, pp , [6] Gaurav Gandhi, An Improved Chua s Circuit and its use in Hyperchaotic Circuit, Analog Integrated Circuits and Signal Processing, vol. 46, no. 2, pp , [7] Peter Stavroulakis, Chaos Applications in Telecommunications, CRC Press, [8] C. Sánchez-López, R. Trejo-Guerra, and E. Tlelo-Cuautle, Simulation of Chua s Chaotic Oscillator Using Unity-Gain Cells, Proc. 7th ICCDCS, Cancun, Mexico, ID-33, April [9] [online] 657

2 1 Introduction Chua s circuit has been widely used for chaotic and nonlinear research [1, 2, 3, 4, 5, 6, 7, 8], since chaotic oscillators can be used in commercial applications such as medicine, biology and secure communications [7]. In the past design of chaos circuits, active devices such as: Current Feedback Operational Amplifier (CFOA) [4, 5], Operational Amplifier (OPAMP) [3], Operational Transconductance Amplifier (OTA) [2] and Second Generation Current Conveyor (CCII) [6] have been used as their building blocks. Recently, a new topology to design the Chua s circuit which is based in UGCs, has been proposed and Hspice simulation results have been reported [8]. In this paper, we report experimental results of Chua s circuit designed with this new topology asasequelto[8]. 2 Unity-Gain Cells Design UGCs have become versatile analog building blocks in the analog signals processing, since they are recognized for its excellent performance in wider bandwidth, low bias voltage, low power consumption, simpler architecture compared with others more complex analog building blocks and high accuracy while operating in open-loop configurations, since their bandwidth is not inversely related to the closed loop gain [8]. For purposes of analysis, each UGC has been built with the IC AD844AN, since it is internally composed by two Voltage Followers (VFs) and one Positive Current Follower (CF+) [9]. Typical values of the parasitic elements connected to the terminals of the IC AD844AN are: R Y =10MΩ, R X =50Ω,R Z =3MΩ, C Y =2pF, C Z =4.5 pf [9]. According to IC AD844AN configuration, a VF can be built by connecting the X-terminal with W-terminal, as shown in Fig. 1 a. A CF+ is obtained by connecting the Y-terminal toward signal ground, as shown in Fig. 1 b. In order to obtain a CF-, two CF+ connected in cascade should be used, as shown in Fig. 1 c [8]. 3 NR Architecture With UGCs The topology of the NR with UGCs taken from [8] is shown in Fig. 2 a. Here, parasitic elements associated to the terminals of the IC AD844AN are taken in account, therefore, it can easily be shown that the node voltages V X and in Fig. 2 a can be approximated as: V Y V x V N (1+ ) Z 2 Z Z2 Z 1 (Z Z2 + Z X3 ) ) Z 4 Z Z4 V y V N (1+ Z 3 (Z Z4 + Z X5 ) The currents flowing through Z 2 and Z 4 are given as: i Z2 = 1 Z 2 (V N V X ), i Z4 = 1 Z 4 (V N V Y ) (3) (1) (2) 658

3 Fig. 1. UGCs designed with the AD844AN: (a) VF, (b) CF+ and (c) CFwhere Z 1 = R 1 +2R X1 + R X2 Z 2 = R 2 Z 3 = R 3 +2R X1 + R X4 Z 4 = R 4 Z X3 = R X3 Z X5 = R X5 Z Z2 = R Z2 //C Z2 Z Z3 = R Z3 //C Z3 Z Z4 = R Z4 //C Z4 Z Z5 = R Z5 //C Z5 Z Y 1 = R Y 1 //C Y 1 The input currents to both CF s are provided by V A /Z 1 and V A /Z 3,where V A is the output voltage associated to the VF. On the other hand, the total output current of a CF is limited by the current mirrors of the input stage, since they are saturated to a maximum output voltage. Thus, the maximum positive output voltage is constant at E +sat (positive saturation region), the maximum negative output voltage is E sat (negative saturation region) and when the input current is small in magnitude, the output varies almost linearly with the input (linear region). This way, by considering parasitic elements and following the same analysis as in [8], the new breakpoints and slopes of the NR are modified as: (4) m 0 = 1 Z Z 4 m 1 = 1 Z 4 + Z 1Z X3 +Z Z2 (Z 1 Z Z3 ) Z 1 (Z 2 +Z Z3 )(Z Z2 +Z X3 ) 1 Z 4 + m 2 = Z 1Z X3 +Z Z2 (Z 1 Z Z3 ) Z 1 Z Z3 Z 1 (Z 2 +Z Z3 ) Z 1 (Z 2 +Z Z3 )(Z Z2 +Z X3 ) + Z 3Z X5 +Z Z4 (Z 3 Z Z5 ) Z 3 (Z 4 +Z Z5 )(Z Z4 +Z X5 ) Z 1 Z Z3 Z 1 (Z 2 +Z Z3 ) + Z 3 Z Z5 Z 3 (Z 4 +Z Z5 ) (5) ±E 1 = ± ±E 2 = ± E ± sat 1+ Z 4 Z Z Z4 Z 3 (Z Z4 +Z X5 ) E ± sat Z 1+ 2 Z Z2 Z 1 (Z Z2 +Z X3 ) ± E± sat 1+ Z 4 Z 3 ± E± sat 1+ Z 2 Z 1 ±E 3 = ±E ± sat (6) 4 Active Grounded Inductor Architecture The design of the active grounded inductor by using UGCs, is depicted in Fig. 2 b. Again, by considering parasitic elements and following the analysis 659

4 Fig. 2. (a) Nonlinear resistor (b) Active grounded inductor (c) Chua s circuit designed with UGCs given in [8], the equivalent inductance value can be computed as: where I IN V IN = Z 3 Z Z4 Z 1 Z 2 (Z Z4 + Z X5 ) + 1 Z 4 Z 3 Z 1 Z 2 (7) Z 1 = R 1 + R X1 + R X4 Z 2 = R 2 + R X2 + R X3 Z 3 = R Z5 //R Y 2 //C A Z 4 = R Z3 //R Y 1 //C B Z Z4 = R Z4 //C Z4 Z X5 = R X5 C A = C + C Y 2 + C Z5 C B = C Y 1 + C Z3 If the parasitic elements are insignificant, then the Eq. (8) is reduced to [8]: (8) V IN I IN scr 1 R 2 = sl eq (9) 5 Chua s Circuit Architecture and Experimental Results The Chua s chaotic oscillator circuit implemented with UGCs, is shown in Fig. 2 c. This circuit was also implemented in the laboratory using the IC AD844AN from Analog Devices with ±5 V voltage supply. For purposes of experimentation, we have fixed the following values of the elements: R 1 =1.8kΩ, R 2 = 560 Ω, R 3 =2.2kΩ, R 4 =4.7kΩ, R 5 = 560 Ω, R 6 =18Ω, R =1.5kΩ, C 1 =22nF, C 2 =1uF and C = 470 nf. The inductor is approximated to L = mh, where the parasitic resistances and capacitances of the VFs and CFs have been considered. The inductor along with the NR, both designed with UGCs show a good behavior at low frequency. We note that the parasitic resistors associated to the input terminal of a CF 660

5 Fig. 3. (a) The double scroll attractor experimental. Horizontal axes: V C2 (0.1 V/div), Vertical axes: V C1 (20 mv/div), (b) Experimental results in the time domain. V C1(t) :1V/div,V C2(t) : 100 mv/div. and at the output terminal of a VF play an important role in the inductor behavior and of the NR, since they impose a low-limit on the values of R 1, R 3, R 5 and R 6. Furthermore, one should have care also with the parasitic capacitances, since the discrete capacitors should be large enough to minimize the effect of the parasitic capacitor at nodes Y and Z of the IC AD844AN. On the other hand, the double scroll attractor measured in the laboratory is shown in Fig. 3 a. A good agreement of the theoretical analysis [8] with the experimental results is evident. Finally, the chaotic waveforms in the time domain are shown in Fig. 3 b. 6 Conclusions We have demonstrated experimentally that the Chua s chaotic circuit can be designed with UGCs. In this case, each UGC has been implemented in the laboratory by using the IC AD844AN and a consequence, the NR and the grounded active inductor can easily be built. Likewise, the equations that model the behavior of the slopes and breakpoints associated to the NR as well as of the grounded active inductor, have been deduced. Experimental results in the time domain and in the state space have been shown for illustrating the capability of the proposed topology. Acknowledgments This work has been supported by CONACyT, Mexico with the project number J