Nanocrystalline Si Formation by Pulsed Laser Deposition/Annealing Techniques and Its Charge Storage Eect

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1 Journal of the Korean Physical Society, Vol. 51, December 2007, pp. S308S312 Nanocrystalline Si Formation by Pulsed Laser Deposition/Annealing Techniques and Its Charge Storage Eect Sol Lee, Byoung Youl Park and Kyoungwan Park Department of Nano Science and Technology, University of Seoul, Seoul Chang Hyun Bae and Seung Min Park Department of Chemistry, Kyung Hee University, Seoul Cheljong Choi IT Convergence Technology Research Division, Electronics and Telecommunications Research Institute, Daejeon Seongjae Lee Department of Physics, Hanyang University, Seoul Si nanocrystals were fabricated in a SiO 2 lm by pulsed laser deposition followed by annealing in an O 2 atmosphere. High resolution transmission electron microscopy and photoluminescence analyses demonstrate the existence of Si nanocrystals in the SiO 2 lms, whose average size is 2 4 nm. Metal-oxide-silicon structures containing a SiO 2 layer are shown to exhibit capacitance-voltage hysteresis under several gate voltage sweep conditions. A eld eect transistor with a SiO 2 layer as a gate insulator was fabricated, and this revealed a memory eect. It is shown that the charge storage memory eect is a likely consequence of charging/discharging at the Si nanocrystals. PACS numbers: Gk, Cw, Ap Keywords: Pulsed laser deposition, Si nanocrystals, Charge storage eect, Nonvolatile oating gate memory I. INTRODUCTION Since the charge storage eect and light emission were observed in Si nanocrystals (Si-NCs) embedded in SiO 2, such systems have been the subject of intensive studies in terms of electronic and optoelectronic device applications [1{4]. Si-NCs may also be used as quantum electronic devices such as single electron tunneling transistors and memory devices [5]. Recently, the charge storage eects of Si-NCs have been widely investigated and metal-oxidesilicon (MOS) memory structures containing Si-NCs as charge storage nodes in the gate oxide were reported to be promising for future applications in ultra-dense and ultra-low power ash memories [6{11]. Si-NC charge storage memory devices are expected to have characteristics that include long-term charge retention and fast switching response, due to the high tunneling barrier of the SiO 2 and small size of the Si-NC charge storage units, respectively [1, 2]. Various methods of growing Si-NCs were suggested, such as Si ion implantation [6, 12], plasma-enhanced chemical-vapor deposition [13,14], pulsed laser deposition [15], and low-pressure chemical- kwpark@uos.ac.kr; Tel: ; Fax: S308- vapor deposition [16{18]. There are limitations, however, in the fabrication of a Si-NC charge storage memory device, such as low threshold voltage shift and uctuation of electrical characteristics from one device to an other, mainly because of the low nanocrystal density and the spread of nanocrystal size. As such, the formation of Si- NCs with high density and uniform size became a critical issue in Si-NC charge storage memory technology. Pulsed laser deposition (PLD) is a versatile technique for the growth of thin lms and nanostructured materials. For example, it has been demonstrated that PLD of silicon in an inert gas atmosphere allows the synthesis of photoluminescent silicon nanoclusters with wellcontrolled size [19, 20]. Laser ablation in a reactive gas atmosphere is also known to be a powerful method to control the stoichiometry of deposited lms. The optical properties of SiO 2 thin lms deposited under oxygen pressure have recently been investigated for optoelectronic applications such as silicon-based light emitting materials and waveguides [21, 22]. Although Si-NCs in SiO 2 formed by the PLD technique are a good candidate in material systems for charge storage nonvolatile memory devices, there are few studies on such material systems. We attribute the lack of information on the nonvolatile memory properties of the PLD silicon oxide

2 Nanocrystalline Si Formation by Pulsed Laser { Sol Lee et al. -S309- layer to poor quality of the oxide matrix layer. In this work, SiO x (x < 2) lms were deposited by the PLD method and successively post-annealed in O 2 ambient, in order both to precipitate the Si-NCs and to increase the oxygen content in the as-deposited SiO x (x < 2) lms. High resolution transmission electron microscopy (HRTEM) and photoluminescence (PL) measurements were employed to verify the existence of Si- NCs. MOS structures and MOS eld eect transistors (FET) with the SiO 2 layer containing the Si-NCs were fabricated, and the charge storage eect was investigated through capacitance-voltage (C-V ) and drain currentgate voltage (I D -V G ) measurements. II. EXPERIMENT SiO x (x < 2) lms were deposited by using the PLD technique on p-type Si substrate with 3.5-cm resistivity and (100) orientation. The target material, consisting of a pure silicon disk, was irradiated with a focused laser beam in an oxygen-lled atmosphere. The base pressure and working pressure of the PLD chamber were Torr and Torr, respectively. The target was rotated in the deposition process. The post-annealing process was performed at 500 C for 10 min in an O 2 atmosphere. The detailed processes for Si-NC formation were well described elsewhere [23]. The formation of Si- NCs was investigated by HRTEM experiments. The PL was measured at room temperature. The wavelength of the pumping source for the PL measurements was 325 nm, from a He-Cd laser. We made MOS structures with the SiO x (x < 2) layer in order to investigate the charge storage eect. A 5- nm SiO 2, that is tunneling oxide, was grown by a thermal oxidation method on p-type Si substrate. The 20- nm-thick SiO x (x < 2) lms were deposited by using the PLD technique on the tunneling oxide. After that, the 20-nm-thick control oxide was deposited on the SiO x (x < 2) lm with mixed gases of SiH 4 and O 2 at 430 C for 20 min in a low pressure chemical vapor deposition system. The control oxide deposition temperature was high enough, so post-annealing the as-deposited layer in O 2 atmosphere was not carried out in the fabrication of MOS structures. The control oxide deposition simultaneously plays the role of post-annealing in O 2 atmosphere. The electrodes were fabricated by depositing a 400-nmthick Al layer onto both the top of the control oxide lm and the backsurface of the silicon substrate by a thermal evaporator. High-frequency (1 MHz) C-V measurement was performed at 300 K. MOSFET structures with the same gate oxide stack as that in the MOS structures were fabricated, and the threshold voltage shifts were measured in order to investigate the nonvolatile memory properties. Fig. 1. (a) Cross-sectional HRTEM image showing Si- NCs. (b) PL spectra of the SiO 2 layer (post-annealed and as-deposited). III. RESULTS AND DISCUSSION Images of the Si-NCs after the post-annealing process in O 2 ambient are clearly seen in the cross-sectional HRTEM results, which are shown in Figure 1(a). Otherwise, no Si-NC images were observed in the as-deposited SiO x (x < 2) lms. We reported in previous experiments that post-annealing the as-deposited SiO x (x < 2) lms in O 2 ambient played a crucial role for the formation of Si-NCs embedded in SiO 2 matrix. The clear peaks at the Si-Si binding energy and Si-O binding energy in the X-ray photoemission spectra indicated that the Si-NCs were formed in the SiO 2 matrix during the post annealing process [23]. The density of the Si-NCs is estimated to be about /cm 2. The size of the Si-NCs is quite uniform, and the average size is 2.1 nm. Figure 1(b) shows PL spectra of the post-annealed and as-deposited lms. The post-annealed lm shows strong luminescence intensity at 0.75 m and small intensity at 0.9 m in addition, while there is not detectable luminescence in the as-deposited lm. We attribute the and 0.9-m luminescences to the light emission from the major Si-NCs and larger Si-NCs, 3.9 nm in size, which appear in Figure 1(a), respectively. The luminescence energy results agree well with the previously reported PL peak energy

3 -S310- Journal of the Korean Physical Society, Vol. 51, December 2007 Fig. 2. Current vs: applied voltage. Squares and solid line denote the experimental data and the tted data, respectively. The experimental data are best tted by I V 2 exp( b=v ), which is known to be the expression for the Fowler-Nordheim tunneling process. The inset shows a schematic of the device. vs: Si-NC size [20]. We examined the correlation between the bandgap energy and the size of the Si-NC by using a quantum connement model based on the eective mass theory. The bandgap energy of three dimensionally conned Si- NCs can be expressed as E (ev) = E bulk + C=d 2, where E bulk is the bandgap energy of the bulk crystalline Si, that is 1.12 ev, C is the quantum-connement parameter, and d is the diameter of the Si-NC in nanometers [24]. The quantum-connement parameters are calculated to be 2.3 and 4.0 from the TEM and PL results for the small Si-NCs and large Si-NCs, respectively. The smaller quantum-connement parameters in this study, compared to the reported values [24], can be attributed to imperfections in the crystalline structure of Si-NCs. Localized electronic states due to the structural imperfections are believed to be less sensitive to the quantum connement than the delocalized states in perfect crystalline Si-NCs [25]. Figure 2 shows the I-V characteristics of the MOS device, and the inset is a schematic diagram of the device structure. There are many carrier transport mechanisms in the insulating layer, such as Schottky emission, Frenkel-Poole emission, and Fowler-Nordheim tunneling [26]. To identify the charge transport mechanism in the multi-oxide layers, we tted the experimental data. The squares and the line in Figure 2 denote experimental data and tted data, respectively. The experimental data are best tted by I V 2 exp( b=v ), which is known to be the expression for the Fowler-Nordheim tunneling process. Therefore, these data conrm that Fowler-Nordheim tunneling of the carriers is the dominant carrier transport mechanism, with an onset voltage of 0.8 V. The charge storage eect of Si-NCs can be easily ob- Fig. 3. C-V hysteresis curves of the MOS with the SiO 2 layer containing the Si-NCs in the gate stack. The voltage of the top electrode is swept from V to +V and back to V. served in the C-V measurements of the MOS structure containing the Si-NCs in the gate oxide stack. A hysteresis behavior in the C-V plot represents charging/discharging eects in oxide-trap sites. Figure 3 shows typical C-V hysteresis curves. No hysteresis curve is found in the small range of voltage sweep, ( 1, +1) V, which is consistent with the value of the onset tunneling voltage of 0.8 V. However, a considerable C-V hysteresis is observed when the voltage sweep range increases; the magnitude of the hysteresis reaches 4.1 V in the sweep range of ( 5, +5) V. The shift of the C-V curve with respect to the curve with no hysteresis is clearly larger for a sweep of V to +V (hole charging) than for a sweep of +V to V (electron charging). The directions of the threshold voltage shift ( V th ) in the hysteresis behavior indicate that hole and electron charging occur at negative and positive gate voltages; the hole and electron charging from the substrate make V th 2.6 V and 1.5 V, respectively. This may be caused by the larger shift of the energy level in the conduction band than that in the valence band by a quantum-connement effect [27], thus lowering the tunneling barrier for electrons in the Si-NCs, compared to that for holes [13,28]. The lower tunneling barrier for electrons than for holes implies that electrons can escape from the Si-NCs more easily than holes, resulting in a smaller C-V shift by electron charging. Moreover, no hysteresis was found in the MOS structure without the PLD-oxide layer, so that the hysteresis behavior was clearly attributed to the charging/discharging eect to/from the Si-NCs. A n-channel MOSFET with the Si-NCs as the charge storage nodes was fabricated; this is a nonvolatile Si- NC oating gate memory. Figure 4 shows the I D -V G characteristics of the memory device. We measured the I D -V G under a drain voltage (V D ) of 0.05 V without any initial gate voltage stress. The initial threshold voltage was observed to be 0.3 V. After a gate voltage stress of 5

4 Nanocrystalline Si Formation by Pulsed Laser { Sol Lee et al. -S311- REFERENCES Fig. 4. I D-V G characteristics of the nonvolatile Si-NC oating gate memory before and after electron charging. The arrows indicate the positions of threshold voltage. V was applied in a few seconds, the I D -V G was measured under V D of 1 V. The I D -V G curve shifts from the initial curve; the V th was found to be 1.1 V between the empty state and the electron-charging state of the Si-NCs. The V th of the MOSFET is less than that of the MOS as seen in Figure 3, which may be due to the weak electron retention property caused by the low tunneling barrier for electrons. IV. SUMMARY Si nanocrystals were successfully fabricated in a SiO 2 lm by pulsed laser deposition followed by annealing in an O 2 atmosphere; their average size and density are 2.1 nm and /cm 2, respectively. Through HRTEM and PL analyses, it was found that the post annealing process in O 2 atmosphere played a crucial role for the formation of Si-NCs in SiO 2 matrix with high density and uniform size. Charge storage eect was demonstrated in MOS structures containing the Si-NCs in the gate oxide stack, by measurements of the capacitance-voltage hysteresis of 4.1 V. The fabricated nonvolatile Si-NC oating gate memory device showed a memory eect, in which the threshold voltage shift was 1.1 V under program voltage bias of 5 V. The charge storage memory eect is a consequence of charging/discharging at the Si nanocrystals and points to the possibility of nonvolatile Si nanocrystal oating gate memories. ACKNOWLEDGMENTS This work was nanced by the University of Seoul as part of its 2006 research program. [1] S. Tiwari, F. Rana, H. Hana, A. Hartstein, E. F. Cabbe and K. Chan, Appl. Phys. Lett. 68, 1377 (1996). [2] S. Tiwari, F. Rana, K. Chan, L. Shi and H. Hana, Appl. Phys. Lett. 69, 1232 (1996). [3] M. L. Brongersma, A. Polman, K. S. Min, E. Boer, T. Tambo and H. A. Atwater, Appl. Phys. Lett. 72, 2577 (1998). [4] F. Iacona, G. Franzo and C. Spinella, J. Appl. Phys. 87, 1295 (2000); A. Irrera, D. Pacici, M. Miritello, G. Franzo, F. Priolo, F. Iacona, D. Sanlippo, G. Di Stefano and P. G. Fallica, Appl. Phys. Lett. 81, 1866 (2002); F. Iacona, C. Bongiorno, C. Spinella, S. Boninelli and F. Priolo, J. Appl. Phys. 95, 3723 (2004). [5] Nanomaterials: Synthesis, Properties and Applications, edited by A. S. Edelstein and R. C. Cammarata (Institute of Physics, London, 1996). [6] E. Kapetanakis, P. Normand, D. Tsoukalas, K. Beltsios, J. Stoemenos, S. Zhang and J. Berg, Appl. Phys. Lett. 77, 3450 (2000). [7] M. L. Ostraat, J. W. De Blauwe, M. L. Green, L. D. Bell, M. L. Brongersma, J. Casperson, R. C. Flagan and H. A. Atwater, Appl. Phys. Lett. 79, 433 (2001). [8] J. D. Blauwe, IEEE Transactions on Nanotechnology 1, 1 (2002). [9] M. Saitoh, E. Nagata and T. Hiramoto, Appl. Phys. Lett. 82, 1787 (2003). [10] Y. D. Kim, E. K. Kim, S. Lee and W. J. Cho, J. Korean Phys. Soc. 49, 1192 (2006). [11] S. S. Kim, W.-J. Cho, C.-G. Ahn, K. Im, J.-H. Yang, I.-B. Baek, S. Lee and K. S. Lim, Appl. Phys. Lett. 88, (2006). [12] S.-H. Choi and R. G. Elliman, Appl. Phys. Lett. 75, 968 (1999); S. Kim, H.-S. Hwang, S.-H. Choi and K. J. Kim, J. Korean Phys. Soc. 48, 108 (2006). [13] N.-M. Park, S.-H. Choi and S.-J. Park, Appl. Phys. Lett. 81, 1092 (2002). [14] C.-H. Cho, B.-H. Kim, T.-W. Kim, S.-J. Park, N.-M. Park and G.-Y. Sung, Appl. Phys. Lett. 86, (2005). [15] P. Normand, E. Kapetanakis, P. Dimitrakis, D. Tsoukalas, K. Beltsios, N. Cherkashin, C. Bonafos, G. Benassayag, H. Con, A. Claverie, V. Soncini, A. Agarwal and M. Ameen, Appl. Phys. Lett. 83, 168 (2003). [16] Y. Shi, K. Saito, H. Ishikuro and T. Hiramoto, J. Appl. Phys. 84, 2358 (1998). [17] M. Saitoh, E. Nagata and T. Hiramoto, Appl. Phys. Lett. 82, 1787 (2003). [18] F. Mazen, T. Baron, A. M. Papon, R. Truche and J. M. Hartmann, Applied Surface Science 214, 359 (2003). [19] N. Suzuki, T. Makino, Y. Yamada, T. Yoshida and S. Onari, Appl. Phys. Lett. 76, 1389 (2000); T. Makino, Y. Yamada, N. Suzuki, T. Yoshida and S. Onari, J. Appl. Phys. 90, 5075 (2001). [20] T. Orii, M. Hirasawa and T. Seto, Appl. Phys. Lett. 83, 3395 (2003). [21] D. Riabinina, C. Durand, M. Chaker and F. Rosei, Appl. Phys. Lett. 88, (2006). [22] A. P. Caricato, M. De Sario, M. Fernandez, G. Leggieri, A. Luches, M. Martino and F. Prudenzano, Appl. Surf. Sci. 197, 458 (2002).

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