Synthesis, testing and tolerance in reversible logic

Transcription

1 Universit of Lethridge Reserh Repositor OPUS Theses Arts nd Siene, Fult of 2017 Snthesis, testing nd tolerne in reversile logi Nshir, Md Asif Lethridge, Alt. : Universit of Lethridge, Dept. of Mthemtis nd Computer Sienes Downloded from Universit of Lethridge Reserh Repositor, OPUS

2 SYNTHESIS, TESTING AND TOLERANCE IN REVERSIBLE LOGIC MD ASIF NASHIRY Bhelor of Siene, Islmi Universit, 2006 Mster of Siene, Islmi Universit, 2008 A Thesis Sumitted to the Shool of Grdute Studies of the Universit of Lethridge in Prtil Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY Deprtment of Mthemtis nd Computer Siene Universit of Lethridge LETHBRIDGE, ALBERTA, CANADA Md Asif Nshir, 2017

3 SYNTHESIS, TESTING AND TOLERANCE IN REVERSIBLE LOGIC MD ASIF NASHIRY Dte of Defene: Deemer 19, 2017 Dr. J. E. Rie Supervisor Professor Ph.D. Dr. S. Wismth Committee Memer Professor Ph.D. Dr. W. Osorn Committee Memer Assoite Professor Ph.D. Dr. H. Li Internl Memer Assoite Professor Ph.D. Dr. G. W. Duek Eternl Eminer Professor Ph.D. Dr. H. Khrghni Chir, Thesis Emintion Committee Professor Ph.D.

4 Dedition To m eloved prents nd m dughter, Srh Itid. iii

5 Astrt In reent ers, reversile omputing hs estlished itself s promising reserh re nd emerging tehnolog. This is motivted widel supported predition tht onventionl omputer hrdwre tehnologies will reh their limits in the ner future. This thesis fouses on three importnt res of reversile logi, whih is n re of reversile omputing. Firstl, this thesis proposes trnsformtion sed snthesis pproh for relizing onservtive reversile funtions using SWAP nd Fredkin gtes. The proposed SWAP nd Fredkin gtes pproh is ompred with NOT, CNOT nd Toffoli gtes pproh. Eperimentl results show tht snthesizing onservtive reversile funtions using SWAP nd Fredkin gtes is more effiient thn omprle pprohes using NOT, CNOT nd Toffoli gtes. Most eisting snthesis pprohes in reversile logi result in iruits tht m not e optiml in terms of ost metris suh s the gte ount, the numer of grge lines or the quntum ost. Hene, post snthesis optimiztion pprohes re used to generte simplified iruits. This thesis proposes ten templtes for optimizing SWAP nd Fredkin gtes-sed reversile iruits. We hve pplied these templtes in SWAP nd Fredkin gtes-sed iruits, nd hieved (on verge) 16% redution in quntum ost. Seondl, this thesis proposes n pproh for the design of online testle reversile iruits. A reversile iruit omposed of NOT, CNOT nd Toffoli gtes n e mde online testle dding two sets of CNOT gtes nd single prit line. The performne of the proposed pproh for deteting single it fult, rosspoint fult nd fmil of missing gte fults hs een oserved. Disussion round the orretness of our pproh nd its overhed is lso provided. iv

6 DEDICATION Thirdl, we hve proposed n pproh to hieve fult tolerne in reversile iruits. A design of 3-it reversile mjorit voter iruit is presented. The proposed mjorit voter iruit is simpler nd of lower ost in terms of the gte ount nd the quntum ost thn eisting designs in the literture. This voter iruit n e used to design fult tolernt reversile iruits. We lso provide designs for etending the voter iruit. v

7 Aknowledgments First nd foremost, I would like to thnk the Almight for giving me the opportunit, strength, nd ptiene to undertke this reserh. This work would not hve een possile without His lessing. I m using this opportunit to epress m grtitude to everone who supported me throughout this thesis. I would like to epress m deepest grtitude nd sinere ppreition to m supervisor, Dr. Jqueline E. Rie, for her ptiene, support, effort, nd enggement throughout this thesis. She provided neessr guidne nd strtegi diretion to pursue m thesis, nd helped me to nvigte ever spet of m journe. I would like to epress m grtitude to m thesis ommittee memers, Dr. Shell Wismth, nd Dr. Wend Osorn, for their timel suggestions nd useful remrks during m reserh. I would like to thnk Dr. Mozmmel Khn for his suggestion nd guideline. I would like to etend m thnks to Dr. Hdi Khrghni, Dr. Gerhrd Duek, nd Dr. Hu Li for eing prt of m thesis ommittee. I m thnkful to the Nturl Sienes nd Engineering Reserh Counil of Cnd (NSERC), the Pifi Institute for the Mthemtil Sienes (PIMS)-Alert, nd the Shool of Grdute Studies (SGS) of the Universit of Lethridge for their finnil support. It is hrd to epress how grteful I m to m prents for their support nd srifie. I would like to thnk m wife, dughter, rothers, reltives, friends, nd l mtes for their love, support nd enourgement. Lst ut not lest, I m lso grteful to the reserhers for their ides nd ontriutions in reversile logi. vi

8 Contents Contents List of Tles List of Figures vii i 1 Introdution Ojetives Thesis Orgniztion Bkground Logi Computtion Trditionl Logi Computtion Reversile Logi Computtion Logi Gtes nd Ciruits Trditionl Logi Gtes Reversile Logi Gtes Snthesis Approhes in Reversile Logi Cost Metris in Reversile Logi Fults nd Fult Testing in Reversile Logi Fult Tolerne in Reversile Logi Snthesis nd Post-Snthesis Logi Snthesis in Reversile Logi Trnsformtion Bsed Snthesis Approh A Proposed Trnsformtion Bsed Snthesis Approh Comprison of Trnsformtion Bsed Approhes Post Snthesis Optimiztion Proposed Templtes Reversile Ciruits Optimiztion Chpter Summr Contriution Conlusion Future Diretions vii

9 CONTENTS 4 Fult Testing Fult Models nd Fult Testing: An Overview Fult Models for Reversile Logi Crosspoint Fult Model Missing Gte nd Repeted Gte Fult Model Fult Testing in Reversile Ciruits Offline Approhes Online Approhes New Online Testing Approh Design Anlsis Testing: Fult Detetion Comprison nd Limittion Chpter Summr Contriution Conlusion Future Diretions Fult Tolerne in Reversile Logi Priniple of Fult Tolerne Tehniques to Ahieve Fult Tolerne Testing vs. Tolerne Approhes to Ahieve Fult Tolerne Fult Tolerne in Reversile Ciruits Eisting Reversile Mjorit Voter Ciruits A Proposed Reversile Mjorit Voter Fult Tolernt Full Adder Design Etension of Reversile Mjorit Voter Chpter Summr Contriution Conlusion Future Diretions Conlusion Contriution nd Conlusion Future Works Biliogrph 124 A Eperiment Result 130 viii

10 List of Tles 2.1 Truth tles of trditionl logi funtions Truth tles of reversile logi funtions Prit preserving nd onservtive reversile funtions Truth tle of 3 3 Toffoli Gte Truth tle of 3 3 positive ontrolled Fredkin gte Trnsformtion of n irreversile funtion to reversile one Quntum ost of n n Toffoli gtes A 3-it reversile funtion Truth tle of (3 3) reversile funtion Trnsformtion stges of the funtion from Tle Stges of SF sed trnsformtion of the funtion in Tle Comprison etween two iruits shown in Figures 3.1 nd Performne omprison of NCT gte trnsformtion sed snthesis nd SF gte trnsformtion sed snthesis Performne omprison of the miniml iruits generted using et snthesis [67] with the iruits generted using SF gte sed snthesis Perentge of redution in GC nd QC when using SF sed trnsformtion s ompred to NCT sed trnsformtion Truth tle for Templte Results fter ppling the proposed templtes on enhmrk iruits Results fter ppling templtes on rndoml generted iruits Truth tle of the iruit shown in Figure Output vlues t the different levels of the iruit shown in Figure Output vlues t the different levels of iruit shown in Figure Output vlues t the different levels of the iruit in Figure Test vetor to detet pperne fult in the iruit shown in Figure Test vetor to identif SMGF for the iruit, s shown in Figure Logi vlues t different levels to detet MGFs for the iruit, shown in Figure Truth tles of the iruits shown in Figure Truth tle for the iruit shown in Figure 4.20() Overhed for seleted enhmrk iruits Truth tle for the reversile voter iruit Truth tle of the 4-it mjorit voter shown in Figure A.1 Results fter ppling templtes on rndoml generted iruits i

11 List of Figures 2.1 Some trditionl iruits Some reversile gtes of NCT gte fmil Some reversile logi gtes of the SF gte fmil A reversile iruit onsisting of three gtes A 3 3-Toffoli gte operting s n AND gte Two different reliztions of the sme funtion using the SF gte fmil The iruit otined from the funtion shown in Tle Ciruit resulting from SF sed snthesis of the funtion from Tle Ciruit reliztion using NCT nd SF gte fmilies Further simplified iruits for the funtion shown in Tle Two templtes presented in [41] An emple to demonstrte the deletion rule in reversile iruit An emple to demonstrte the moving rule for iruit simplifition A SF iruit where the moving rule does not work Templte Templte Templte Templte Templte Templte Templte Templte Templte Templte Moving rules for the SF gte fmilies An emple to show the role of the moving rule in iruit optimiztion Apperne nd dispperne fults in reversile iruit SMGF in reversile iruit A RGF where gte is repled n even numer of instnes of the sme gte A RGF where gte is repled n odd numer of instnes of the sme gte An emple of the ourrene of MMGF A reversile iruit with the ourrene of PMGF An emple of single pperne rosspoint fult An emple of SMGF in reversile iruit

12 LIST OF FIGURES 4.9 DFT sed pproh for missing gte testing [20] R1 nd R2 gtes proposed in [69] Blok digrms of piring of R1 nd R2 reversile gtes An online testle iruit sed on the pproh proposed in [69] A CNOT gte nd its dedued version for online testing TRC nd TC for online testilit A (3 + 1)-it ETG gte An emple of online testle reversile iruit sed on [49] An emple of online testle reversile iruit sed on [28] Two eisting reversile online testing pprohes for PMGF Conversion of Toffoli gte into Duplite Gte Blok Trnsformtion of reversile iruit into its online testle equivlent Blok digrm of n online testle reversile iruit Testing for the ourrenes of SMGF nd PMGF Testing for the ourrenes of pperne rosspoint fult Testing for n ourrene of single it fult IG gte presented in [23] Prit Preserving Full Adder Ciruit Composed of IG gtes Prit Preserving Toffoli gte [18] Ahieving fult tolerne using the onept of redundn Three identil opies of module using TMR in trditionl omputing A minimum triplited voter iruit proposed in [72] A reversile mjorit voter s proposed in [6] A three input reversile mjorit voter Ahieving fult tolerne using TMR A fult tolernt reversile full-dder iruit design A 4-it mjorit voter A 4-it mjorit voter designed from 3-it voter A 5-it reversile mjorit voter A 6-it reversile mjorit voter i

13 Chpter 1 Introdution We re living in n ge where there is n ever growing dependen on digitl devies. The mount of informtion proessed digitl devies ontinues to inreses over time. In order to proess this inresing volume of informtion, the numer of omponents frited on integrted iruits of digitl devie is lso inresing over time. Over the pst few dedes, the size of the omponents hs een redued in order to inrese the densit of these omponents on integrted iruits. However, this pttern nnot ontinue forever euse the urrent tehnolog is pprohing the phsil limits of omputing [14]. Limittions of trditionl omputing, suh s het dissiption, n eome n ostle for the further development of urrent tehnolog [14, 15]. Logi in trditionl omputing is irreversile. In most ses, its of informtion re destroed during the logil opertions tht re performed in trditionl omputing. One of the fundmentl limittions of trditionl omputing is tht eh time informtion is lost, energ is dissipted regrdless of the underling tehnolog. In 1961 R. Lnduer showed tht KT ln2 joules re dissipted eh time n informtion it is lost during logil opertion, where K is Boltzmnn s onstnt nd T is the operting temperture in Kelvin [30]. At room temperture, the mount of dissipted het eomes joules. For instne, when two-input AND gte produes single it of output, this mount of energ is dissipted s het. The mount of generted het m not seem signifint t present. However, s Moore s lw [62], prediting douling of omponents ever few ers, hs held true over the lst severl dedes, this het dissiption is eoming mjor onern in trditionl irreversile sstems. Re- 1

14 1.1. OBJECTIVES versile omputing [15] offers solution to this potentil dedlok of further development in trditionl omputing. It ws lso shown Chrles Bennett tht theoretil zero power dissiption n onl e hieved if the iruit is logill reversile [5]. Reversile omputing is ijetive, nd definition reversile iruits re informtion-lossless [10]. Thus, using reversile omputtion, the power dissiption whih results ording to Lnduer s priniple n e deresed or even eliminted. For this reson, in reent ers reversile omputtion hs estlished itself s promising reserh re nd emerging tehnolog. Other resons for reserh into reversile sstems inlude onnetions to quntum omputing [21], nd pplitions in rptogrph [64], nno-omputing tehnologies [40] nd digitl proessing [51]. It is widel elieved tht the net genertion omputers will e quntum omputers. Quntum omputtions re reversile, nd the iruits in quntum omputing work on reversile funtions [51]. Therefore, reserh on reversile logi is inevitle from vrious points of view. 1.1 Ojetives Most logi gtes used in trditionl omputtion re not reversile. In most ses, the reltionship etween the input nd the output of trditionl gte is mn-to-one. For emple, n AND gte hs two or more inputs nd one output. However, the reltionship etween the input nd the output of reversile gte is one-to-one. Over the pst few ers, severl reversile logi gtes nd snthesis methods hve een proposed [11, 16, 37, 68]. However, nlsing the logi gtes nd the snthesis pprohes in order to optimize reversile iruits is still n tive re of reserh. We hpothesize tht one prtiulr set of reversile gtes n e more useful thn nother for relizing speifi reversile funtions. One of the ojetives of this thesis is to develop snthesis pproh for relizing onservtive reversile funtions. The numer of gtes of iruit is onsidered n importnt ompleit mesure in trdi- 2

15 1.2. THESIS ORGANIZATION tionl omputing. In ddition to this mesure, the quntum ost nd the numer of grge lines re two dditionl ftors to onsider in mesuring the ompleit of reversile iruit. Templte mthing nd rule sed simplifitions re two ommonl used postsnthesis methods for optimizing reversile iruits. This thesis introdues new templtes for simplifing reversile iruits. The testing of reversile iruits is nother importnt re. The phsil implementtion of quntum iruits will e different thn the implementtions of trditionl iruits. Therefore, fult models designed for trditionl iruits will not work for reversile iruits. Proposing ost-effetive testing pproh for reversile fult models is nother ojetive of this thesis. Sine reversile iruit mintins one-to-one reltionship etween inputs nd outputs, hieving fult tolerne in suh sstem is not n es tsk. A fult tolernt sstem n orretl perform its speified opertions even in the presene of fults. This thesis lso investigtes the eisting work on the design of fult tolernt reversile iruits nd presents n effiient pproh for hieving fult tolerne in reversile iruits. 1.2 Thesis Orgniztion The reminder of this disserttion is orgnized s follows. Chpter 2 provides detiled introdution to reversile logi nd presents the required kground knowledge neessr for this disserttion. Chpter 3 disusses trnsformtion sed snthesis in reversile logi. A proposed pproh sed on this tehnique is presented in this hpter. The performne of this proposed pproh is evluted nd ompred with n eisting pproh. This hpter lso introdues templtes nd presents post snthesis optimiztion pproh for simplifing reversile iruits. Chpter 4 desries reversile fult models nd fult testing pprohes. The eisting testing pprohes in reversile iruits re nlsed nd the limittions of these pprohes 3

16 1.2. THESIS ORGANIZATION re identified. A testing pproh for three reversile fult models is proposed lter in this hpter. Chpter 5 fouses on fult tolerne. The requirements for hieving fult tolerne in reversile iruits re disussed in this hpter. A mjorit voter iruit is presented, whih n e used to design fult tolernt reversile iruits. An etension of this voter iruit nd other res of pplition of the proposed voter re lso disussed in this hpter. Chpter 6 highlights the ontriutions, onludes with disussions nd provides diretions for possile future work. 4

17 Chpter 2 Bkground This hpter desries the fundmentl onepts of reversile logi s well s the priniples of snthesis, fult testing nd fult tolerne in reversile logi. 2.1 Logi Computtion Logi pls mjor role in modern d omputtion. Digitl logi is logi for representing nd mnipulting digitl informtion. Logi in omputer siene dels with defining prolem in terms of Boolen funtions, nd designing iruit in order to implement the funtions. Logi in tod s digitl devies follows the priniple of Boolen logi, whih is lso known s lssil or trditionl logi. As disussed in Chpter 1, there eists limits to the eisting phsil omponents of digitl sstem tht implement trditionl logi. Reversile logi offers one possile model to design digitl sstem to overome suh limittions Trditionl Logi Computtion Like n other funtion, trditionl logi funtion mps one or more inputs to one or more outputs. More speifill, trditionl logi funtion, f, tkes the form f : B n B m, where n nd m re non-negtive integers, nd B = {0,1} is Boolen domin. The vlues of n nd m m or m not e equl nd in most ses n > m. For emple, simple iruit onsisting of onl one AND gte hs two (or more) inputs, ut hs onl one output. Tht is, logi omputtions in trditionl pprohes often mp multiple inputs to fewer outputs. A onvenient w to represent the reltionship etween inputs nd outputs is 5

18 2.1. LOGIC COMPUTATION using truth tle. A truth tle shows ll possile input nd output omintions for speifi logi funtion. A truth tle for Boolen logi funtion uses (n+m) olumns nd 2 n rows to show the ehviour of funtion for ll possile input instnes of the funtion of n input nd m output. Tle 2.1: Truth tles of trditionl logi funtions. () NOT opertion. I O () AND opertion. I 1 I 2 O () Full dder opertion. I 1 I 2 in sum out One of the simplest emples of trditionl logi funtion is logil NOT opertion, whih tkes one input nd genertes one output, s shown in Tle 2.1(). Tles 2.1() nd 2.1() show funtions for whih the reltionship etween inputs nd outputs is not one-to-one. Hene, for these funtions it is not possile to determine the input sttes oserving onl the output of funtion. For emple in Tle 2.1(), the output vlues re 0 for the input sttes (0,0),(0,1), nd (1,0). B oserving this output vlue, 0, it is not possile to determine whether the input vlues re (0,0),(0,1), or (1,0). A similr oservtion n e mde from the truth tle shown in Tle 2.1() nd most other trditionl or lssil logi funtions. The reltionship etween inputs nd outputs of trditionl funtion is not ijetive (with the onl eeption eing NOT opertion). This mens tht the reltionship etween inputs nd outputs of trditionl funtion is not one-to-one nd onto. Sine ijetive reltionships etween inputs nd outputs do not eist for most trditionl funtions, it is not possile to determine n input instne from n output instne of trditionl funtion. For this reson trditionl logi is sometimes referred to s irreversile 6

19 2.1. LOGIC COMPUTATION logi Reversile Logi Computtion A reversile logi funtion hs the form f : B n B n, where n is non-negtive integer nd the domin B = {0,1}, with the ke feture eing tht the funtion is ijetive. More speifill, the numer of inputs nd the numer of outputs of reversile funtion re etl the sme. In prtiulr, there is lws distint output stte for eh of the possile input sttes. Tle 2.2: Truth tles of reversile logi funtions. () NOT opertion. I O () Contolled NOT opertion. I 1 I 2 O 1 O () Full dder opertion. g in in i 1 i 2 out sum g out1 g out

20 2.1. LOGIC COMPUTATION The work in this thesis is restrited to Boolen reversile logi funtions. For Boolen reversile funtion of n vriles, truth tle requires 2n olumns nd 2 n rows in order to represent the funtion. Tle 2.2() shows tht NOT opertion in reversile logi hs the sme funtionlit s tht of trditionl NOT opertion (Tle 2.1()). In ft, NOT opertion in trditionl logi is reversile in nture. As long s there is unique output for eh input instne of funtion, the funtion is reversile (Tle 2.2). This reltionship etween the input nd the output llows the determintion of input vlues of funtion from the output vlues. In order to trnsform n irreversile funtion into reversile one, it is often neessr to inlude one or more etr vriles on the output nd/or input sides of truth tle of the irreversile funtion. For emple, the truth tle of reversile full dder shown in Tle 2.2() onsists of etr vriles on oth the input nd output s ompred to the truth tle of its irreversile ounterprt shown in Tle 2.1(). The dditionl inputs re lled onstnt inputs, or nill inputs. The dditionl outputs re non-funtionl outputs euse these re not the output of interest of the reversile funtion. In full dder, sum nd rr re the two output its of interest. In Tle 2.2(), two outputs, sum nd out, represent the sum nd the rr its of full dder. The other two outputs, g out1 nd g out2, re used to mintin the ijetive reltionship etween the inputs nd the outputs of this reversile full dder funtion. These non-funtionl outputs re known s grge outputs, s the do not ontriute to the propert of the originl output of funtion. Two importnt properties of reversile funtions re the prit preserving propert nd the onservtion propert. A prit preserving reversile funtion, s the nme suggests, preserves the prit of the input vetors to the orresponding output vetor. For emple, in prit preserving reversile funtion, if the prit of n input vetor is even, the prit of the output vetor will lso e even. Ever output vetor of the funtion shown in Tle 2.3() preserves the prit (either odd or even) of the orresponding input vetor. Hene, the funtion shown in Tle 2.3() is n emple of prit preserving funtion. However, this funtion is not onservtive funtion. A reversile funtion is lled 8

21 2.2. LOGIC GATES AND CIRCUITS onservtive funtion if nd onl if the numer of 1s in the output vetor is the sme s tht of the orresponding input vetor, for ll inputs. The funtion shown in Tle 2.3() is n emple of onservtive reversile funtion. Chpter 4 shows the role of the prit preserving propert in the fult detetion nd testing of reversile iruits. A snthesis pproh sed on the onservtion propert is presented in Chpter 3. Tle 2.3: Prit preserving nd onservtive reversile funtions. () A prit preserving funtion. input output I 1 I 2 I 3 O 1 O 2 O () A onservtive funtion. input output I 1 I 2 I 3 O 1 O 2 O Logi Gtes nd Ciruits A logi gte performs one or more logil opertions in order to implement logil funtion. A iruit onsists of one or more logi gtes, whih re onneted some form of interonneted medi (e.g. wire). This setion desries some logi gtes s well s logi iruits in trditionl nd reversile logi omputtion Trditionl Logi Gtes Severl logi gtes eist for designing iruits in trditionl logi. The gtes AND, OR nd NOT re the primr logi gtes. Figure 2.1 shows oth NOT nd n AND logi gte. These two gtes re used to implement the trditionl NOT (Tle 2.1()) nd AND (Tle 2.1()) funtions, respetivel. A NOT gte works s n inverter, whih lws 9

22 2.2. LOGIC GATES AND CIRCUITS tkes one input nd produes one output fter inverting the input vlue. An AND gte, on the other hnd, works on more thn one input nd produes single output. A full dder iruit, whih onsists of trditionl logi gtes, is shown in Figure 2.1(), nd implements the funtion represented Tle 2.1(). A trditionl full dder iruit hs three input lines nd two outputs lines to generte sum nd rr its. () A trditionl NOT gte. () A trditionl AND gte. A B S C in C out () A trditionl full dder iruit. Figure 2.1: Some trditionl iruits Reversile Logi Gtes A reversile iruit onsists of one or more reversile gtes tht re onneted in sde. Tht is, the output(s) of prior gte is/re onneted s input(s) to the following gte. For emple, onsider reversile iruit g 2 (g 1 ( 1, 2 )) where the outputs of logi gte g 1 re onneted s the inputs of the gte g 2 in order to implement 2-it reversile funtion, f ( 1, 2 ). Like reversile logi funtion, one of the fundmentl hrteristis of reversile gte is tht the reltionship etween inputs nd outputs is one-to-one. This implies tht the output vlues of reversile gte re distint for n given input. So unlike trditionl irreversile gte, it is lws possile to restore the input vlues of reversile gte from the outputs. A trditionl NOT gte is lso reversile gte, sine it is possile 10

23 2.2. LOGIC GATES AND CIRCUITS to dedue the input of NOT gte from its output. For emple, 1 t the output of NOT gte for prtiulr instne indites tht the input of tht instne is 0. A numer of reversile gtes eist in order to implement reversile funtions. The two most widel used tegories of reversile logi gtes re [71] : the NCT (NOT-CNOT- Toffoli) gte fmil nd the SF (SWAP-Fredkin) gte fmil. NCT gte fmil The NCT gte fmil (Figure 2.2) onsists of NOT, CNOT nd Toffoli gtes. This is one of the most widel used gte fmilies in reversile omputing. The simplest possile reversile logi gte is NOT gte. A NOT gte (Figure 2.2()), like NOT gte in trditionl logi, onsists of one input nd one output, whih inverts the vlue of the input to generte the output. A CNOT gte nd Toffoli gte re vritions of NOT gte. A CNOT gte [12] is ontrolled-not gte with ontrol input nd trget input. The vlue presented t the ontrol point determines when to invert the vlue of the trget input, or simpl trnsfers the trget input vlue to the output. Figure 2.2() shows CNOT gte. The ( ) smol in the CNOT gte represents ontrol point nd the ( ) smol indites the trget of reversile gte. When the vlue of the ontrol of CNOT gte is 1, the gte inverts the vlue of the input tht is onneted to the trget line. If the vlue of the ontrol point is 0, the vlue of the trget input remins unhnged to the trget output. For emple, when the inputs of CNOT(I 1, I 2 ) gte in Figure 2.2() re (1,0), the output (O 1,O 2 ) will e (1,1 0) (1,1). Unlike NOT gte, CNOT gte n ontrol the inversion of n input vlue, hene its nme is ontrolled-not or CNOT. A CNOT gte is lso known s Fenmn gte. A vrition of Fenmn gte is doule Fenmn gte. A doule Fenmn gte onsists of one ontrol point nd two trget lines. When the vlue of the ontrol point is 1, the doule Fenmn gte inverts oth input vlues tht re onneted to the trget lines [53]. A Toffoli gte [68] is form of the CNOT gte where the numer of ontrol points is 11

24 2.2. LOGIC GATES AND CIRCUITS I 1 O 1 = I 1 I O = Ī I 2 O 2 = I 1 I 2 () A reversile NOT gte. () A CNOT gte. I 1 O 1 = I 1 I 2 O 2 = I 2 I 1 O 1 = I 1 I 3 O 3 = I 3 I 2 I 3 () A 3 3 Toffoli gte. O 2 = I 2 O 3 = I 3 I 1 I 2 I n-1 I n O n-1 = I n-1 O n = I n Ī 1 I 2 Ī 3...I n-1 (d) A n n Toffoli gte with multiple nd negtive ontrol. Figure 2.2: Some reversile gtes of NCT gte fmil. more thn 1. For emple, Figure 2.2() shows 3 3 Toffoli gte with two ontrol points nd one trget line. The two input lines, I 1 nd I 2, re onneted to the two ontrol points nd the third input I 3 is onneted to the trget line. The vlues of the inputs, whih re onneted to the ontrol lines, remin unhnged t the output. The vlues presented t the input of these ontrol lines determine when the gte will invert the vlue presented t the trget input line. The trget line in Figure 2.2() hs the funtion: O 3 = I 3 I 1 I 2. This mens the vlue of the trget line will e inverted when oth inputs tht re onneted to the ontrol points hve the vlue 1. For emple, when (I 1,I 2,I 3 ) (0,1,1), the output of the Toffoli gte will e (O 1,O 2,O 3 ) (0,1,1). In this se there is no hnge on the vlue of the trget input, sine one of the ontrol points (I 1 ) is equl to 0. However, when (I 1,I 2,I 3 ) (1,1,1) the gte output will e (O 1,O 2,O 3 ) (1,1,1 1 1) (1,1,1 1) (1,1,0). In this se oth ontrol points hve the vlue 1, whih is the required ondition for inverting the input vlues t the output. The truth tle of 3 3 Toffoli gte is shown in Tle 2.4. Bsed on the numer k of ontrol points of gte, logi gte in the NCT fmil is lso referred to s k-cnot gte. For emple, sed on the numer of ontrol lines the NOT, CNOT nd 3 3 Toffoli gtes re lso known s 0-CNOT, 1-CNOT nd 2-CNOT gtes respetivel. A Toffoli gte with multiple ontrols is referred to s multiple ontrolled Toffoli (MCT) gte. In ddition, Toffoli gte or Fenmn gte n hve one or more 12

25 2.2. LOGIC GATES AND CIRCUITS Tle 2.4: Truth tle of 3 3 Toffoli Gte. input output I 1 I 2 I 3 O 1 O 2 O negtive ontrol points. For emple, negtive ontrol Fenmn (1-CNOT) gte inverts the input vlue t the trget line if nd onl if the vlue of the ontrol point is 0. A negtive ontrol is represented ( ) smol in the NCT gte lirr. For emple, Figure 2.2(d) shows multiple ontrolled Toffoli gte where two input lines I 1 nd I 3 re onneted to the two negtive ontrol lines. A negtive ontrol, like positive ontrol of logi gte, does not ffet the vlue on the line to whih it is onneted. The output funtion of the trget of n n-toffoli gte, s shown in Figure 2.2(d), is O n = I n I 1 I 2 I 3 I n 1. This mens tht when the vlues of ll negtive ontrol points re 0, nd the vlues of ll positive ontrol points re 1, the gte will invert the vlue tht is onneted to its trget input. Another ommon w to represent the gtes of the NCT fmil is in the form of Toffoli gtes. A TOF(C;T) nottion is used to indite Toffoli gte with C ontrol points nd T trget lines. For instne, TOF(0;T), TOF(1;T) nd TOF(2;T) represent NOT, CNOT nd 3 3 Toffoli gtes, respetivel. An importnt propert of Toffoli gte is tht it n e used to implement n reversile funtion. For this reson, Toffoli gte is known s universl gte in reversile logi [52]. SF Gte Fmil Two other importnt reversile logi gtes re SWAP nd Fredkin gtes. A Fredkin gte [16] is vrition of SWAP gte with one or more ontrol points. A Fredkin gte is lso 13

26 2.2. LOGIC GATES AND CIRCUITS universl gte in reversile logi, sine it is possile to implement the three si opertions (NOT, AND nd OR) using onl Fredkin gtes [52]. As disussed ove, the logi gtes in the NCT gte fmil invert the vlue of the trget input sed on ertin onditions (in the se of CNOT, Toffoli gtes) or without n ondition (in the se of NOT gtes). Insted of inverting the input vlue on trget line, the trget lines of n SF gte interhnge their vlues. Generll, gte of the SF gte fmil hs two trget lines. When gte interhnges the vlues of the trget lines t the output without n ondition, the gte is lled SWAP gte. However, if the swp or interhnge of the trget vlues ours sed on the vlues presented on the ontrol lines, the gte is lled Fredkin gte. The truth tle of 3 3 positive ontrolled Fredkin gte is shown in Tle 2.5. Figures 2.3() nd 2.3() Tle 2.5: Truth tle of 3 3 positive ontrolled Fredkin gte. input output I 1 I 2 I 3 O 1 O 2 O show SWAP gte nd 3 3 positive ontrolled Fredkin gte respetivel. A SWAP gte lws swp the vlues whih re onneted to its trgets lines. For n input vetor (I 1,I 2 ), the output of the SWAP gte will e (O 1 = I 2,O 2 = I 1 ), s shown in Figure 2.3(). However, positive ontrolled Fredkin gte interhnges two trget input vlues (I 2,I 3 ) if the vlue of the other input, I 1, whih is onneted to ontrol line ( ), is 1. If the vlue of I 1 equls to 0, the Fredkin gte simpl trnsfers ll the input vlues to the orresponding output vlues without interhnging the trget vlues. A 3 3 positive ontrolled Fredkin gte with ontrol point onneted to I 1, nd two trget lines, I 2 nd I 3, hs the following output funtions t 14

27 2.2. LOGIC GATES AND CIRCUITS 1. ontrol point: O 1 = I 1 2. trget line: O 2 = I 1 I 2 I 1 I 3, nd 3. trget line: O 3 = I 1 I 2 I 1 I 3. I 1 1 (0) I 1 O 1 = I 2 I 2 I 3 (I 2 ) I 2 O 2 = I 1 I 3 I 2 (I 3 ) () A SWAP gte. () A (3 3) positive ontrolled Fredkin gte. I 1 0 (1) I 1 I 2 O 1 = I 1 O 2 = I 2 I 2 I 3 I 3 (I 2 ) I 2 (I 3 ) I 3 I 4 O 3 = I 4 O 4 = I 3 If I 1 = 0, nd I 2 = 1 () A (3 3) negtive ontrolled Fredkin gte. (d) A (n n) multiple ontrolled Fredkin gte. Figure 2.3: Some reversile logi gtes of the SF gte fmil. When Fredkin gte onsists of more thn one ontrol point, the Fredkin gte is lled multiple ontrolled Fredkin (MCF) gte. Like Toffoli gte, Fredkin gte n lso hve one or more negtive ontrols (Figure 2.3()). In this se the gte swps the vlues onneted to the trget lines if nd onl if 0 vlue is presented t the negtive ontrol point. Figure 2.3(d) shows n emple of multiple ontrolled Fredkin gte onsisting of oth positive nd negtive ontrol points. In this se 1 t the positive ontrol nd 0 t the negtive ontrol point tivte the gte to interhnge the vlues on the trget lines. One or more reversile gtes n e used to generte iruit in order to implement reversile funtion. For emple, onsider reversile funtion f (I 1,I 2,I 3 ) (O 1,O 2,O 3 ) where (O 1,O 2,O 3 ) re defined s (I 1,I 1 I 2,(I 1 I 1 I 2 ) I 3 ) respetivel. These three output funtions n e implemented the iruit TOF(TOF(TOF(I 1 );I 2 );I 3 ) onsisting of three reversile gtes s shown in Figure 2.4. As seen in this emple the outputs of one 15

28 2.3. SYNTHESIS APPROACHES gte g i re onneted s the inputs for the gte g i+1 whih ppers immeditel net to g i in the iruit. The output of the NOT gte, TOF(I 1 ), is I 1 whih is onneted s n input of the following CNOT gte. This then omputes TOF(TOF(I 1 );I 2 ) = TOF(I 1 ;I 2 ) = (I 1,I 1 I 2 ). Finll, the outputs of this CNOT gte re onneted s the inputs of the 3- it Toffoli gte, whih omputes TOF(TOF(TOF(I 1 );I 2 );I 3 ) = TOF(TOF( I 1 ;I 2 );I 3 ) = TOF(I 1,I 1 I 2 ;I 3 ) = (I 1,I 1 I 2,I 1 (I 1 I 2 ) I 3 ) = (I 1,I 1 I 2,I 1 I 1 I 2 I 3 ). I 1 O 1 I 2 O 2 I 3 O 3 Figure 2.4: A reversile iruit onsisting of three gtes. 2.3 Snthesis Approhes in Reversile Logi The onept of snthesis is ver importnt in designing reversile logi iruits. Snthesis refers to the trnsformtion of logi funtion into orresponding logi iruit. Aording to some snthesis pprohes, if logi funtion is irreversile, the first step of logi snthesis is to trnsform the funtion into its reversile equivlent. One or more grge lines nd/or onstnt inputs re inluded in the originl irreversile funtion in order to mke the funtion reversile. The finl step is to trnsform the reversile funtion into logi iruit onsisting of one or more reversile gtes whih re onneted in sde. The resulting iruit is reversile iruit. There n e more thn one reversile iruit for implementing single funtion. Two importnt ftors pl signifint role in trnsforming irreversile funtions into reversile iruits: (1) the numer of grge lines nd/or onstnt inputs, whih re inluded in order to trnsform the irreversile funtion to reversile one; nd (2) the use of different reversile logi gtes for relizing the reversile funtion reversile iruit. 16

29 2.4. COST METRICS IN REVERSIBLE LOGIC During the proess of trnsforming n irreversile funtion into the orresponding reversile funtion, it is neessr to oserve the output of the irreversile funtion. If the output of n irreversile funtion hs mimum numer of k identil ptterns, the minimum numer of grge lines required to mke the funtion reversile is log 2 k [35]. For instne, onsider the irreversile AND funtion in Tle 2.6(). The output of this irreversile funtion hs 3 ourrenes of logi 0. Thus the minimum numer of grge lines required in order to trnsform the funtion into its reversile ounterprt is log 2 3 = 2 s shown in Tle 2.6(). For the input line, I 3 = 0 in Tle 2.6(), the funtion performs the AND opertion of input lines, I 1 nd I 2, nd genertes the output t O 3. The other two output lines, O 1 nd O 2, do not ontriute to the finl output, nd hene these two lines re onsidered grge lines. An importnt ft to oserve is tht the ehviour of the funtion in Tle 2.6() is the sme s the ehviour of 3 3-Toffoli gte (Tle 2.2()). Thus, 2-input trditionl AND opertion n e implemented 3 3-Toffoli gte, s shown in Figure 2.5. Chpter 3 overs more regrding snthesis nd post snthesis pprohes in reversile logi. Tle 2.6: Trnsformtion of n irreversile funtion to reversile one. () Irreversile AND funtion. input output I 1 I 2 O () One possile orresponding reversile AND funtion. input output I 1 I 2 I 3 O 1 O 2 O

30 2.4. COST METRICS IN REVERSIBLE LOGIC I 1 I 2 O 1 = I 1 O 2 = I 2 grge outputs onstnt 0 input O 3 = I 1 I 2 (AND opertion) Figure 2.5: A 3 3-Toffoli gte operting s n AND gte. 2.4 Cost Metris in Reversile Logi Sine reversile funtion n e snthesized in multiple ws, it is neessr to evlute the ost of the snthesis pprohes. A numer of metris n e used to evlute the effiien of iruits for relizing the sme reversile funtion [45]. Gte ount is one of the most ommon ost metris, prtiulrl in trditionl logi design. As the nme suggests, gte ount refers to the numer of gtes required in iruit to relize funtion. For emple, one Toffoli gte is used to implement the AND opertion, s shown in Figure 2.5. In this se the gte ount is 1. However, gte ount is not useful prmeter when the iruits onsist of different tpes of gtes. Gte ount does not onsider gte ompleit; it insted simpl ounts the numer of gtes in iruit. Gte ount n e good evlutor when two iruits onsist of gtes of the sme size nd ompleit. Mohmmdi et l. [45] proposed new form of gte ount giving some weight to the gtes sed on the ompleit of the gtes of iruit. The numer of grge outputs in iruit is nother importnt ost metri. During the snthesis proess in reversile logi, one or more grge outputs m e needed for mintining reversiilit. The vlues of the grge lines re not signifint to the finl output of iruit. Therefore, it is desirle to minimize the numer of grge outputs. A iruit design with fewer grge lines is onsidered desirle design. For mn, quntum ost is the most importnt prmeter for evluting reversile iruit from design stndpoint. Quntum ost is defined s the numer of si or primitive quntum gtes whih re required to design reversile gte. The 1 1 nd 2 2 qun- 18

31 2.4. COST METRICS IN REVERSIBLE LOGIC Tle 2.7: Quntum ost of n n Toffoli gtes. Size (n) Grge Nme Quntum Cost 1 0 NOT,t CNOT,t Toffoli,t Toffoli,t t t t t t t t t t t t t t t t t t10 86 n > 10 0 tn 2 n 3 n > 10 1 tn 24n 88 n > 10 n 3 tn 12n 34 tum gtes re onsidered primitive quntum gtes. For emple, quntum NOT, CNOT, V nd V + gtes re onsidered primitive quntum gtes, nd the quntum ost of these gtes is onsidered to e 1. The quntum ost of Toffoli gte nd Fredkin gte is 5, sine five primitive gtes re required for designing these gtes. Breno et l. [4] showed reliztion of 3 3 Toffoli gte onsisting of 2 positive ontrol points using five primitive quntum gtes. Smolin nd DiVinenzo [66] presented n implementtion of 3 3 positive-ontrolled Fredkin gte using five 2-quit (quntum it) elementr quntum gtes. Quntum ompution nd quntum gtes re eond the sope of this thesis. A detiled disussion on quntum gtes n e found in [4, 43, 51]. In ddition, there hve een 19

32 2.4. COST METRICS IN REVERSIBLE LOGIC numer of works suh s [2, 4, 34, 35, 39, 33, 58] on minimizing the quntum ost for designing reversile iruit. Tle 2.7 shows the quntum ost of positive ontrol Toffoli gtes [71]. Tle 2.8: A 3-it reversile funtion. input output I 1 I 2 I 3 O 1 O 2 O Another importnt ftor to onsider when designing reversile iruits is to minimize the numer of grge outputs. However, there re some ses where the quntum ost of iruit n e redued dding grge lines [33]. For emple, s seen from Tle 2.7, the quntum ost of 6 6 Toffoli gte without inluding n etr line s grge line is 61. However, fter dding 1 nd 3 lines s grge lines the quntum ost of 6 6 Toffoli gte n e redued to 52 nd 38 respetivel. Therefore, lrge numer of grge lines does not lws ield higher quntum ost. I 1 O 1 I 1 O 1 I 2 O 2 I 2 O 2 I 3 O 3 I 3 O 3 () () Figure 2.6: Two different reliztions of the sme funtion using the SF gte fmil. Similrl higher gte ount for iruit does not neessril men higher quntum ost. Consider the 3 3 reversile funtion shown in Tle 2.8. Figure 2.6 shows 20

33 2.5. FAULTS AND FAULT TESTING IN REVERSIBLE LOGIC two different implementtions of this funtion using onl SWAP nd Fredkin gtes. Both implementtions hve gte ount of 3. The reliztion in Figure 2.6() uses two negtiveontrolled Fredkin gtes nd one positive-ontrolled Fredkin gte. The quntum ost of the first implementtion is ( ) = 15. The iruit in the seond implementtion, shown in Figure 2.6(), uses two SWAP gtes nd one 3 3 positive-ontrolled Fredkin gte. Here the quntum ost is ( ) = 11. Both iruits onsist of 3 logi gtes; however, the seond iruit offers more effiient iruit design, from the perspetive of the quntum ost, thn the first iruit. 2.5 Fults nd Fult Testing in Reversile Logi A fult leds to filure of sstem. A fult n e defined s n imperfetion within some hrdwre nd/or softwre omponents. Therefore, fult leds the sstem to produe n inorret output. This inorret output is known s n error, whih is devition from the urte outome [26]. Fults re the unwnted events for sstem nd, therefore, must e deteted nd removed. A fult model is model tht onsiders the potentil fults whih m our in sstem [59]. An idel fult detetion method n detet ll the fults of prtiulr fult model. A ommon fult model in trditionl logi is the stuk-t fult model. Sometimes wire n pss onl high or low voltge signls due to the mlfuntion of some prt of iruit. Tht is, pth of iruit is stuk t prtiulr voltge level. When line of iruit psses onl high voltge due to the ourrene of fult, the fult is onsidered to e stuk-t 1 fult. When line of iruit psses onl low voltge, the fult is onsidered to e stuk-t 0 fult. As onsequene the iruit genertes n inorret output. For emple, if line is roken, it is onsidered open nd the output of tht line will lws e 0. The fult in this sitution is refered to e stuk-t 0. However, reserh suggests tht the stuk-t fult model is not n pproprite fult model in reversile omputing [20, 73]. A numer of fult models for reversile logi hve een proposed [20, 56, 73]. 21

34 2.6. FAULT TOLERANCE IN REVERSIBLE LOGIC A method of testing is required in order to identif the ourrene of fult in iruit. Testing indites whether sstem is fult or fult-free. Fult overge is n importnt onept in testing whih reltes fult models to testing strtegies. Fult overge is rtio of the numer of fults deteted testing method to the totl numer of detetle fults for given fult model. Methods of testing in reversile omputtion re divided into two tegories: offline testing nd online testing [59]. Eh hs its own enefits nd drwks. Online testing pprohes ppl the testing opertions in rel time. Tht is, online testing methods determine whether the output of sstem is orret or inorret while the sstem is performing its norml opertions. However, this is not the se for n offline testing method. In offline testing, the sstem under onsidertion is tken out of its norml mode of opertion, nd then the method of testing is pplied. Fult models nd testing pprohes in reversile logi re desried in detil in Chpter 4 of this thesis. 2.6 Fult Tolerne in Reversile Logi The differene etween fult testing nd fult tolerne is tht fult testing is proess of error identifition wheres fult tolerne is proess of error orretion. Fult tolerne is n ttriute tht enles sstem to generte orret output even in the presene of fults in the sstem. One or more tehniques m e required in order to hieve fult tolerne. These m inlude fult detetion, fult dignosis, fult ontinment, fult reover nd fult msking. Eh of these tehniques requires dditionl logil or phsil omponents of the sstem suh s hrdwre, softwre nd/or informtion [26]. For emple, one w to hieve fult tolerne in sstem is to replite one or more phsil omponents of the sstem. The tehniques nd pprohes tht n e used to hieve fult tolerne in reversile iruits re desried in Chpter 5. 22

35 Chpter 3 Snthesis nd Post-Snthesis This hpter egins with providing the si onepts of snthesis in reversile logi. A trnsformtion-sed snthesis is proposed in this hpter. This hpter lso introdues templtes for optimizing reversile iruits. Eperimentl results tht evlute the proposed templtes re provided t the end of the hpter. 3.1 Logi Snthesis in Reversile Logi Logi snthesis is the proess of generting iruit design, desried s sde of gtes, tht n implement the desired logi funtion. The reltionship etween the inputs nd the outputs of logi funtion determines the numer of the logi gtes, tpe of logi gtes used, nd the order in whih the logi gtes pper in the iruit. If logi funtion is lred reversile, the snthesis proess n tke ple immeditel. However, if logi funtion is not reversile, the first step in most snthesis lgorithms is to trnsform the irreversile funtion into reversile one. One or more grge outputs nd/or onstnt inputs re dded to n irreversile funtion in order to trnsform the irreversile logi funtion into reversile logi funtion. Setion 2.3 in Chpter 2 shows n emple of trnsforming n irreversile AND funtion into reversile funtion. In most ses, reversile iruit design with fewer grge outputs nd/or onstnt inputs is onsidered desirle design. The minimum numer of grge outputs whih re required in order to trnsform n irreversile funtion into reversile funtion is log 2 K, where K is the mimum numer of repeted pttern in the output of n irreversile funtion [35]. 23