EXAMINATION in Hardware Description and Verification

Transcription

1 Department of VT09 Computer Science and Engineering TDA956/DIT780 Chalmers and Gothenburg University EXAMINATION in Hardware Description and Verification DAY : TIME : 14:00-18:00 ROOM : Väg och Vatten Responsible for course : Thomas Hallgren, tel Result : To be available at the latest 12/06-09 Permitted in the exam : Paper and pen. No books, PDAs etc. Minimum points for each grade : CTH: 3 : 24, 4 : 36, 5 : 48 out of 60 : GU: G : 24, VG : 48 out of 60 PLEASE NOTE THE FOLLOWING Start each new question on a new page. Write your personal number (or date of birth) and name on each page. Write on only one side of each page. Attempt all questions. Read through all the questions first. Questions that look long may need short answers! 1

2 Questions 1-4 Consider the following circuit: NOR x AND OR 1 1 z y This small circuit has one input x and one output y, and contains two d-type flip-flops that output 1 in the first clock cycle. Here is an VHDL entity declaration for the circuit: library ieee; use ieee.std_logic_1164.all; entity circuit2 is port (clk,x : in std_logic; y : out std_logic); end circuit2; Question 1 (8 points) 1. Write a behavioural architecture for circuit2. Use Gaisler s two-process method. (5 points) 2. Write a test bench that connects circuit2 to a 500MHz clock and an input signal that is high for 5 clock cycles, then goes low. Question 2 (8 points) 1. A property that holds of circuit2 is that if the input x is always high, then the output y is always high. Express this property as a PSL assertion. 2. Is the above property a safety property? If not, write a safety property in PSL that captures the same intention as closely as possible. Also explain in words what your PSL property means. 2

3 3. Another property that holds of circuit2 is that zeros in the output y always occur in pairs: whenever the output goes low, it stays low for exactly two cycles, then it goes high. Write two PSL assertions that both verify this property: one that uses SEREs (Sequential Extended Regular Expressions) and one that does not use SEREs. Question 3 (10 points) 1. Write down the state transition system of circuit2, in the following form: (x, y, z) (x, y, z ) where. In this description, x corresponds to the input, and y and z to the outputs of the two flip-flops. You should replace the dots with equations that define the correct values for x, y, and z that are enforced by the circuit. Read (x, y, z) as the current state, and (x, y, z ) as the next state. 2. Draw the state transition diagram of this system. Hint: One way to organise the diagram is shown below: Calculate the set of states for which the CTL formula EG y holds, i.e., the set of states in which it is possible for the output y to remain high forever. Show all the steps of your calculation carefully. Hint: use the following model checking formulas: H(EG f) = Gfp U. H(f) Prev(R, U) Prev(R, U) = {s ( t)srt t U} 3

4 Question 4 (11 points) 1. In Lava, define the circuit circuit2 considered in the previous questions. Use the delay element (delay) for the flip-flops, and the built in gates and2, or2 and nor2. 2. In Lava, write the code for an observer circuit check that checks the property defined in question 2.3. Show how you would use the observer (and Lava and SMV) to formally verify that circuit2 has the property. check (x,y) = ok where... (Hint: your observer will need to make use of the delay element.) 3. In Lava, define a circuit that computes the dot product of two vectors, [x 1, x 2,...,x n ] [y 1, y 2,...,y n ] = x 1 y 1 + x 2 y x n y n Numbers are represented as lists of bits, as usual, and vectors are represented as lists of numbers: type Bit = Signal Bool type Binary = [Bit] type Vector = [Binary] Your definition can start like this: dotproduct :: (Vector,Vector) -> Binary dotproduct (xs,ys) =... The following and other circuits from the Lava library and tutorial are available: adder :: (Bit,(Binary,Binary)) -> (Binary,Bit) multi :: (Binary,Binary) -> Binary bintree :: ((a,a)->a) -> ([a] -> a) The carry output form the adders can be ignored, so for example, the dot product of two vectors of 16-bit numbers will be a 32-bit number. 4

5 Question 5 (10 points) 1. It is possible to use a Boolean formula to represent a set of states. Assume that each state comprises three bits (a, b, c). Give a formula that represents the state set {(0, 1, 0), (1, 0, 0), (1, 1, 0)}. 2. Construct the Ordered Binary Decision Diagram for the formula above. Choose the variable ordering a, then b, then c. 3. A simple way to compare if two Boolean formulas are equivalent is to check if their truth tables are the same. How many entries does the truth table for a formula of n variables have? 4. Many Boolean formulas can be efficiently represented as BDDs, but how big can the BDD for a formula of n variables get in the worst case? Question 6 (7 points) 1. LTL has only two basic temporal operators, X p and p U q, and a small number of derived operators, particularly F p and G p. Explain in words what the two basic operators mean, and show how the two derived operators can be defined in terms of the basic operators. 2. Which temporal operators in PSL do the four LTL operators above correspond to? 3. Assuming a request is made by holding the Req line high for one clock cycle, and a request is acknowledged by holding the Ack line high in a subsequent clock cycle, how can the following requirement be expressed in PSL? Before a second request can be made, the first request must be acknowledged. Question 7 (6 points) 1. Four different parallel prefix networks that you may have encountered in the course are the ones by Sklansky, Brent Kung, Kogge Stone and Ladner Fischer. Pick two of them and give for each one an advantage that it has over the other. Consider properties like circuit depth, the number of operators and fanout. 2. Give a Lava definition for one of the above parallel prefix networks. 5