Acknowledgment. DLD Lab. This set of slides on VHDL are due to Brown and Vranesic.
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1 Acknowledgment DLD Lab Thi et o lide on VHDL are due to Brown and Vraneic. Introduction to VHDL (Very High Speed Integrated Circuit Hardware Decription Language) 2 3 A imple logic unction and correponding VHDL code VHDL code or a our-input unction 3 2 g : OUT STD_LOGIC ) ; WITH SELECT <= w WHEN '', w WHEN OTHERS ; 4 Logic circuit or our-input unction Figure 6.27 VHDL code or a 2-to- multipleer
2 w w (a) Graphical ymbol w w (b) Truth table ENTITY mu4to IS PORT ( w, w, w2, w3 : IN STD_LOGIC ; : IN STD_LOGIC_VECTOR( DOWNTO ) ; : OUT STD_LOGIC ) ; END mu4to ; w w (c) Sum-o-product circuit w w (d) Circuit with tranmiion gate ARCHITECTURE Behavior OF mu4to IS WITH SELECT <= w WHEN "", w WHEN "", w2 WHEN "", w3 WHEN OTHERS ; Figure 6. A 2-to- multipleer Figure 6.28 VHDL code or a 4-to- multipleer w w w 2 (a) Graphic ymbol w w w w w 2 (b) Truth table PACKAGE mu4to_package IS COMPONENT mu4to PORT ( w, w, w2, w3 : IN STD_LOGIC ; : IN STD_LOGIC_VECTOR( DOWNTO ) ; : OUT STD_LOGIC ) ; END COMPONENT ; END mu4to_package ; w 2 (c) Circuit Figure 6.2 A 4-to- multipleer Figure 6.28 Component declaration or the 4-to- multipleer w w LIBRARY work ; USE work.mu4to_package.all ; ENTITY mu6to IS PORT ( w : IN STD_LOGIC_VECTOR( TO 5) ; : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; : OUT STD_LOGIC ) ; END mu6to ; w 2 ARCHITECTURE Structure OF mu6to IS SIGNAL m : STD_LOGIC_VECTOR( TO 3) ; Mu: mu4to PORT MAP ( w(), w(), w(2), w(3), ( DOWNTO ), m() ) ; Mu2: mu4to PORT MAP ( w(4), w(5), w(6), w(7), ( DOWNTO ), m() ) ; Mu3: mu4to PORT MAP ( w(8), w(9), w(), w(), ( DOWNTO ), m(2) ) ; Mu4: mu4to PORT MAP ( w(2), w(3), w(4), w(5), ( DOWNTO ), m(3) ) ; Mu5: mu4to PORT MAP ( m(), m(), m(2), m(3), (3 DOWNTO 2), ) ; END Structure ; Figure 6.3 Uing 2-to- multipleer to build a 4-to- multipleer Figure 6.29 Hierarchical code or a 6-to- multipleer
3 w w 4 w 7 w 8 w w 2 w ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR( DOWNTO ) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR( TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO ) ; Enw <= En & w ; WITH Enw SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; Figure 6.4 A 6-to- multipleer Figure 6.3 VHDL code or a 2-to-4 binary decoder En w w y y y 2 y 3 (a) Truth table w w w y w y y 2 En y 3 (b) Graphic ymbol y y y 2 : OUT STD_LOGIC ) ; <= w WHEN = '' w ; En (c) Logic circuit y 3 Figure 6.6 A 2-to-4 decoder Figure 6.3 A 2-to- multipleer uing a conditional ignal aignment PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; y <= "" WHEN w(3) = '' "" WHEN w(2) = '' "" WHEN w() = '' "" ; z <= '' WHEN w = "" '' ; w 2 w w y y d d z Figure 6.32 VHDL code or a priority encoder Figure 6.24 Truth table or a 4-to-2 priority encoder
4 PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; WITH w SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; WITH w SELECT z <= '' WHEN "", '' WHEN OTHERS ; Figure 6.33 Le eicient code or a priority encoder USE ieee.td_logic_unigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS AeqB <= '' WHEN A = B '' ; AgtB <= '' WHEN A > B '' ; AltB <= '' WHEN A < B '' ; Figure 6.34 VHDL code or a our-bit comparator a 3 i 3 b 3 a 2 b 2 i 2 i AeqB USE ieee.td_logic_arith.all ; a b a b i AltB ENTITY compare IS PORT ( A, B : IN SIGNED(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; AgtB ARCHITECTURE Behavior OF compare IS AeqB <= '' WHEN A = B '' ; AgtB <= '' WHEN A > B '' ; AltB <= '' WHEN A < B '' ; Figure 6.26 A our-bit comparator circuit Figure 6.35 A our-bit comparator uing igned number : OUT STD_LOGIC ) ; PROCESS ( w, w, ) IF = '' THEN <= w ; <= w ; : OUT STD_LOGIC ) ; PROCESS ( w, w, ) <= w ; IF = '' THEN <= w ; Figure 6.38 A 2-to- multipleer peciied uing an i-then-ele tatement Figure 6.39 Alternative code or a 2-to- multipleer
5 PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; PROCESS ( w ) IF w(3) = '' THEN y <= "" ; ELSIF w(2) = '' THEN y <= "" ; ELSIF w() = '' THEN y <= "" ; y <= "" ; z <= '' WHEN w = "" '' ; Figure 6.4 A priority encoder peciied uing i-then-ele PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; PROCESS ( w ) y <= "" ; IF w() = '' THEN y <= "" ; IF w(2) = '' THEN y <= "" ; IF w(3) = '' THEN y <= "" ; z <= '' ; IF w = "" THEN z <= '' ; Figure 6.4 Alternative code or the priority encoder ENTITY compare IS PORT ( A, B : IN STD_LOGIC ; AeqB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS PROCESS ( A, B ) AeqB <= '' ; IF A = B THEN AeqB <= '' ; : OUT STD_LOGIC ) ; PROCESS ( w, w, ) CASE IS WHEN '' => <= w ; WHEN OTHERS => <= w ; Figure 6.42 Code or a one-bit equality comparator Figure 6.45 A CASE tatement that repreent a 2-to- multipleer ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR( DOWNTO ) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR( TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS PROCESS ( w, En ) IF En = '' THEN CASE w IS WHEN "" => y <= "" ; WHEN "" => y <= "" ; WHEN "" => y <= "" ; WHEN OTHERS => y <= "" ; y <= "" ; Figure 6.46 A 2-to-4 binary decoder ENTITY eg7 IS PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; led : OUT STD_LOGIC_VECTOR( TO 7) ) ; END eg7 ; ARCHITECTURE Behavior OF eg7 IS PROCESS ( bcd ) CASE bcd IS -- abcdeg WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN "" => led <= "" ; WHEN OTHERS => led <= " " ; Figure 6.47 A BCD-to-7-egment decoder
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