MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES

Transcription

1 CHAPTER 7 MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES 7.1 Multi-Level Gate Circuits 11/20/2014 Prof. M. Akbaba Digital Logic 1

2 Figure 7-1: Four-Level Realization of Z 11/20/2014 Prof. M. Akbaba Digital Logic 2

3 Figure 7-2: Three-Level Realization of Z 11/20/2014 Prof. M. Akbaba Digital Logic 3

4 We can change the expression for Z to three levels by partially multiplying it out. Z= (AB + C)[(D + E) + FG ] + H = AB(D + E) + C(D + E) + ABFG + CFG + H Problem: Find a circuit of AND and OR Gates to realize: f(a,b,c,d) = m(1,5,6,10,13,14) Consider solution with two levels gates and three level gates. Try to minimize the number of gates and total number of gate inputs. Assume that all variables and their complements are available as inputs. 11/20/2014 Prof. M. Akbaba Digital Logic 4

5 Figure 7-3 (7.1) 11/20/2014 Prof. M. Akbaba Digital Logic 5

6 Figure /20/2014 Prof. M. Akbaba Digital Logic 6

7 Figure /20/2014 Prof. M. Akbaba Digital Logic 7

8 f = c d + ab c + cd + a b c (7.3) f = (c + d)( a + b + c )(c +d )( a + b + c ) (7.4) Equation (7.4) leads directly to a two-levels OR-AND circuit given in Figure /20/2014 Prof. M. Akbaba Digital Logic 8

9 Figure /20/2014 Prof. M. Akbaba Digital Logic 9

10 To get a three-level circuits with an AND gate output, we partially multiply out Equation (7.4) using (X+Y)(X+Z)=X+YZ: f = [c d(a + b )][c + d (a+b)] (7.5) Equation (7.5) would require four levels of gates to realize, however, if we multiply out d (a + b ), we get f = (c + a d + bd )(c + ad +bd ) (7.6) Which leads directly to a three-level AND-OR-AND cicuit given in Figure /20/2014 Prof. M. Akbaba Digital Logic 10

11 Figure /20/2014 Prof. M. Akbaba Digital Logic 11

12 Equation (7.3) gives a three-level expression for f : f = c (d + ab ) + c( d + a b ) = c (d + a)(d + b ) + c(d + a )(d + b ) (7.7) Complementing Equation (7.7) gives Equation (7.6), which corresponds to the three-level AND-OR-AND circuit given in Figure /20/2014 Prof. M. Akbaba Digital Logic 12

13 7.2 NAND and NOR Gates Until this point we have designed logic circuits using AND gates, OR gates, and inverters. Exclusive-OR and equivalence gates have also been introduced in Unit 3. In this section we will define NAND and NOR gates. Logic designers frequently use NAND and NOR gates because they are generally faster and use fewer components than AND or OR gates. As will be shown later, any logic function can be implemented using only NAND gates or only NOR gates. 11/20/2014 Prof. M. Akbaba Digital Logic 13

14 Figure 7.8(a) shows a three-input NAND gate. The small circle (or "bubble") at the gate output indicates inversion, so the NAND gate is equivalent to an AND gate followed by an inverter, as shown in Figure 7-8(b). A more appropriate name would be an AND-NOT gate, but we will follow common usage and call it a NAND gate. The gate output is 11/20/2014 Prof. M. Akbaba Digital Logic 14

15 The output of the n-input NAND gate in Figure 7.8(c) is (7.8) The output of this gate is 1 iff one or more of its inputs are 0. 11/20/2014 Prof. M. Akbaba Digital Logic 15

16 Figure 7-8: NAND Gates 11/20/2014 Prof. M. Akbaba Digital Logic 16

17 Figure 7.9(a) shows a three-input NOR gate. The small circle at the gate output indicates inversion, so the NOR gate is equivalent to an OR gate followed by an inverter. A more appropriate name would be an OR-NOT gate, but we will follow common usage and call it a NOR gate. The gate output is 11/20/2014 Prof. M. Akbaba Digital Logic 17

18 Figure 7-9: NOR Gates 11/20/2014 Prof. M. Akbaba Digital Logic 18

19 The output of an n-input NOR gate, shown in Figure 9.9(c), is F = (X 1 +X 2 + +X n ) = X 1 X 2 X n (7.9) 11/20/2014 Prof. M. Akbaba Digital Logic 19

20 (Section 7.2) 11/20/2014 Prof. M. Akbaba Digital Logic 20

21 Figure 7-10: NAND Gate Realization of NOT, AND, and OR 11/20/2014 Prof. M. Akbaba Digital Logic 21

22 Once AND or OR has been realized, the other one can always be realized using DeMorgan's laws if no more direct procedure is apparent. For example, if OR and NOT are available, AND can be realized by XY = (X' + Y ) 11/20/2014 Prof. M. Akbaba Digital Logic 22

23 7.3 Design of Two-Level NAND and NOR Gate Circuits A two-level circuit composed of AND and OR gates is easily Converted to a circuit composed of NAND gates or NOR gates. This conversion is carried out by using F = (F)' and then applying DeMorgan's laws: (7.11) (7.12) The following example illustrates conversion of a minimum sum-of-products form to several other twolevel forms: 11/20/2014 Prof. M. Akbaba Digital Logic 23

24 F = A + BC' + B C D = [(A + C + B CD) ]' = [A' (BC )' (B CD) ] ' = [A' (B' + C) (B + C' + D ) ]' = A + (B' + C)' + (B + C' + D )' Equations (7.13), (7.14), (7.15), and (7.16) represent the AND-OR, NAND-NAND, OR-NAND, and NOR-OR forms, respectively, as shown in Figure Rewriting Equation (7.16) in the form F = {[A + (B' + C)' + (B + C' + D')' ]'}' (7.17) 11/20/2014 Prof. M. Akbaba Digital Logic 24

25 leads to a three-level NOR-NOR-INVERT circuit. However, if we want a two-level circuit containing only NOR gates, we should start with the minimum productof-sums form for F instead of the minimum sum of products. After obtaining the minimum product of sums from a Karnaugh map, F can be written in the following two-level forms: 11/20/2014 Prof. M. Akbaba Digital Logic 25

26 Figure 7-11a: Eight Basic Forms for Two-Level Circuits 11/20/2014 Prof. M. Akbaba Digital Logic 26

27 Figure 7-11b: Eight Basic Forms for Two-Level Circuits 11/20/2014 Prof. M. Akbaba Digital Logic 27

28 (Section 7.3) 11/20/2014 Prof. M. Akbaba Digital Logic 28

29 Procedure for designing a minimum two level NAND-NAND circuit : 1. Find minimum sum-of-product expression for F 2. Draw the corresponding two-level AND-OR circuit 3. Repeat al gates with NAND gates leaving the gate interconnections unchanged. If the gate has any single literals as inputs, complement this literals. Figure 7.12 illustrates the transformation of step 3. Verification that this transformation leaves the circuit output unchanged follows. In general F is a sum of literals (l 1, l 2, l 3,.) and product terms (P 1, P 2,..) F = l 1 + l P 1 + P After applying DeMorgan s law F = (l 1 l 2 P 1 P 2..) 11/20/2014 Prof. M. Akbaba Digital Logic 29

30 Figure 7-12: AND-OR to NAND-NAND Transformation 11/20/2014 Prof. M. Akbaba Digital Logic 30

31 7.4 Design of Multi-Level NAND and NOR Gate Circuits 11/20/2014 Prof. M. Akbaba Digital Logic 31

32 Example F 1 =a [b + c(d + e ) + f g ] + hi j + k Figure 7.13 shows how the AND-OR circuit for F 1 is converted to corresponding NAND circuit 11/20/2014 Prof. M. Akbaba Digital Logic 32

33 F 1 =a [b + c(d + e ) + f g ] + hi j + k Figure 7.13: Multi-Level Circuit Conversion to NAND Gates 11/20/2014 Prof. M. Akbaba Digital Logic 33

34 7.5 Circuit Conversion Using Alternative Gate Symbols 11/20/2014 Prof. M. Akbaba Digital Logic 34

35 (Section 7.5) 11/20/2014 Prof. M. Akbaba Digital Logic 35

36 Figure 7-14: Alternative Gate Symbols 11/20/2014 Prof. M. Akbaba Digital Logic 36

37 Figure 7-15: NAND Gate Circuit Conversion 11/20/2014 Prof. M. Akbaba Digital Logic 37

38 Figure 7-16: Conversion to NOR Gates 11/20/2014 Prof. M. Akbaba Digital Logic 38

39 Figure 7-17: Conversion of AND-OR Circuit to NAND Gates 11/20/2014 Prof. M. Akbaba Digital Logic 39

40 7.6 Design of Two-Level Multiple Output Circuits Designing circuit with four inputs and three outputs which realizes the functions F 1 (A,B,C,D)= m(11,12,13,14,15) F 2 (A,B,C,D)= m(3,7,11,12,13,15) (7.22) F 3 (A,B,C,D)= m(3,7,12,13,14,15) 11/20/2014 Prof. M. Akbaba Digital Logic 40

41 Figure 7-18: Karnaugh Maps for Equations (7-22) 11/20/2014 Prof. M. Akbaba Digital Logic 41

42 Figure 7-19: Realization of Equations (7-22) 11/20/2014 Prof. M. Akbaba Digital Logic 42

43 Figure 7-20: Multiple-Output Realization of Equations (7-22) 11/20/2014 Prof. M. Akbaba Digital Logic 43

44 A four-input three-output circuit is to be designed to realize f 1 = m(2,3,5,7,8,9,10,11,13,15) f 2 = m(2,3,5,6,7,10,11,14,15) f 3 = m(6,7,8,9,13,14,15) (7.23) 11/20/2014 Prof. M. Akbaba Digital Logic 44

45 Figure /20/2014 Prof. M. Akbaba Digital Logic 45

46 First, we plot maps for f 1, f 2 and f 3 (Figure 7.21). If each function is minimized separately, the result is (7.23(a)) 11/20/2014 Prof. M. Akbaba Digital Logic 46

47 By inspecting the maps, we can see that terms a' bd (from f 2 ), abd (from f 3 ), and ab' c (from f 3 ) can be used in f 1. If bd is replaced with a' bd + abd, then the gate needed to realize bd can be eliminated. Because m 10 and m 11 in f 1 are already covered by b'e, ab' c' (from f 3 ) can be used to cover m 8 and m 9 ; and the gate needed to realize ab can be eliminated. The minimal solution is therefore (7.23(b)) (Terms which are used in common between two functions are underlined.) When designing multiple-output circuits, it is sometimes best not to combine a1 with its adjacent 1's, as illustrated in the example of Figure /20/2014 Prof. M. Akbaba Digital Logic 47

48 The solution with the maximum number of common terms is not necessarily best, as illustrated in the example of Figure Determination of Essential Prime Implicants for Multiple-Output Realization As a first step in determining a minimum two-level, multiple-output realization, it is often desirable to determine essential prime implicants. However, we must be careful because some of the prime implicants essential to an individual function may not be essential to the multiple-output realization. For example, in Figure 7.21, bd is an essential prime implicant of f 1 (only prime implicant which covers m 5 ), but it is not essential to multipleoutput realization. The reason for bd is not essential is that m 5 also appears on the f 2 map and, hence might be converted by a term which is shared by f 1 and f 2. 11/20/2014 Prof. M. Akbaba Digital Logic 48

49 Determination of Essential Prime Implicants for Multiple-Output Realization f 1 = a c d+abd+ab c d f 2 = bc d +abcd+bcd F 1 = [(a + b )c + d](e + f ) F 2 = [(a + b )c + g ](e + f )h Bu iki fonksiyonu Karnaugh haritalarına taşıyıp en iyi çözümü veren gerekli temel gurupları (essential prime implicans) bulalım. Sonuç bir sonraki slaytta gösterilmiştir. 11/20/2014 Prof. M. Akbaba Digital Logic 49

50 f 1 = a c d+abd+ab c d f 2 = bc d +abcd+bcd Bu iki fonksiyonu Karnaugh haritalarına taşıyıp en iyi çözümü veren gerekli temel gurupları (essential prime implicans) bulalım. Sonuç bir sonraki slaytta gösterilmiştir. 11/20/2014 Prof. M. Akbaba Digital Logic 50

51 Figure /20/2014 Prof. M. Akbaba Digital Logic 51

52 f 1 =a b d +a bc +bcd f 2 =a b c +a bd +abd 11/20/2014 Prof. M. Akbaba Digital Logic 52

53 Figure /20/2014 Prof. M. Akbaba Digital Logic 53

54 7.7 Multiple-Output NAND and NOR Gate Circuits 11/20/2014 Prof. M. Akbaba Digital Logic 54

55 Figure 7-24: Multi-Level Circuit Conversion to NOR Gates 11/20/2014 Prof. M. Akbaba Digital Logic 55

56 Çok çıkışlı NOR ve NAND kapısı devreleri ÖRNEK 2: Aşağıda verilen iki fonksiyonu çok çıkışlı NAND devresi olarak gerçekleştirelim. f 1 =(ab+c d+n)h+(a+e )g+k f 2 =(c d+eh+g)k+(a+e )g+b İstenen NAND devresi olduğundan önce AND-OR devresini kurmamız doğru yaklaşımdır. Bu devre Şekil 7.25.a da verilmiş ve NAND devresine dönüşümü Şekil 7.25.b de verilmiştir. KBUZEM Karabük Üniversitesi Uzaktan Eğitim Uygulama ve Araştırma 56

57 Çok çıkışlı NOR ve NAND kapısı devreleri Şekil 7.25.a Çok basamaklı AND-OR devresi KBUZEM Karabük Üniversitesi Uzaktan Eğitim Uygulama ve Araştırma 57

58 Çok çıkışlı NOR ve NAND kapısı devreleri Şekil 7.25.b. Çok basamaklı NAND devresi dönüşümü KBUZEM Karabük Üniversitesi Uzaktan Eğitim Uygulama ve Araştırma 58

59 REFEENCES 1. Hüseyin EKİZ, Mantık Devreleri, Değişim Yayınları, 4. Baskı, Prof. M. Akbaba Mantık Devreleri Notları 3.Thomas L. Floyd, Digital Fundamentals, Prentice-Hall Inc. New Jersey, M. Morris Mano, Michael D. Ciletti, Digital Design, Prentice-Hall, Inc.,New Jersey, /20/2014