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CD4021BC 8-Stage Static Shift Register

8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages.

Document Title 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output. Rev. No. History Issue Date Remark

12K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Document Title 12K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Revision History

.SET-RESET CAPABILITY

DUAL D TYPE FLIP FLOP.SET-RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEEL EITHER HIGH OR LOW MEDIUM-SPEED OPERATION - 16MHz (typ.) CLOCK TOGGLE RATE AT 10 QUIESCENT

Up/down binary counter with separate up/down clocks

FEATURES Synchronous reversible 4-bit counting Asynchronous parallel load capability Asynchronous reset (clear) Cascadable without external logic DESCRIPTION The is a 4-bit synchronous up/down counter