REF0 TABLE OF CONTENTS Features... General Description... Pin Configurations... Revision History... Specifications... Electrical Specifications... Abs

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1 FEATURES V output: ±0.% maximum Temperature voltage output:.9 mv/ C Adjustment range: ±% minimum Excellent temperature stability: 8. ppm/ C maximum Low noise: µv p-p maximum Low supply current:. ma maximum Wide input voltage range: 7 V to 0 V High load-driving capability: 0 ma No external components Short-circuit proof GENERAL DESCRIPTION The REF0 precision voltage reference provides a stable V output that can be adjusted over a ±% range with minimal effect on temperature stability. Single-supply operation over an input voltage range of 7 V to 0 V, low current drain of ma, and excellent temperature stability are achieved with an improved band gap design. Low cost, low noise, and low power make the REF0 an excellent choice whenever a stable voltage reference is required. Applications include DACs and ADCs, portable instrumentation, and digital voltmeters. The versatility of the REF0 is enhanced by its use as a monolithic temperature transducer. For new designs, refer to the ADR0. V Precision Voltage Reference/Temperature Transducer REF0 PIN CONFIGURATIONS 8 7 V OUT TRIM GROUND (CASE) = NO CONNECT. DO NOT CONNECT ANYTHING ON THESE PINS. SOME OF THEM ARE RESERVED FOR FACTORY TESTING PURPOSES. Figure. 8-Lead TO-99 (J-Suffix) TEMP REF0 TOP VIEW (Not to Scale) 8 7 V OUT TRIM = NO CONNECT. DO NOT CONNECT ANYTHING ON THESE PINS. SOME OF THEM ARE RESERVED FOR FACTORY TESTING PURPOSES. Figure. 8-Lead PDIP (P-Suffix), 8-Lead CERDIP (Z-Suffix) and 8-Lead SOIC (S-Suffix) REF0 TOP VIEW TEMP 7 (Not to Scale) V OUT TRIM = NO CONNECT. DO NOT CONNECT ANYTHING ON THESE PINS. SOME OF THEM ARE RESERVED FOR FACTORY TESTING PURPOSES. Figure. 0-Terminal LCC (RC-Suffix) 007-F F F-00 OUTPUT RESISTORS REF0 OPTION R9 R R 88C PRODUCT 8kΩ kω.kω P, S, J, Z PACKAGES 8kΩ.kΩ kω R8 R7 R Q8 Q7 Q Q Q R INPUT R C R R Q Q Q9 Q Q Q0 Q7 R Q Q8 Q Q9 OUTPUT R* Q R Q Q Q0 Q.V R9* TRIM R R0 TEMP R *SEE OUTPUT RESISTORS Figure. Simplified Schematic R* GROUND 007-F-00 Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 90, Norwood, MA 00-90, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 REF0 TABLE OF CONTENTS Features... General Description... Pin Configurations... Revision History... Specifications... Electrical Specifications... Absolute Maximum Ratings... 7 Thermal Resistance... 7 Typical Performance Characteristics...8 Output Adjustment... 0 Temperature Monitoring... Reference Stack with Excellent Line Regulation... Precision Current Source... Supply Bypassing... Outline Dimensions... Ordering Guide... ESD Caution... 7 REVISION HISTORY /0 Rev. H to Rev. I Changes to Figure... 0 Changes to Ordering Guide... /0 Rev. G to Rev. H Updated Figure... Changes to Specifications... Updated Outline Dimensions... Changes to Ordering Guide... /0 Rev. F to Rev. G Changes to Specifications... Change to Outline Dimensions... 7/0 Rev. E to Rev. F Updated Format...Universal Changes to Simplified Schematic... Changes to Specifications... Changes to Specifications... Changes to Specifications... Changes to Specifications... Changes to Figure Changes to Ordering Guide... /0 Rev. D to Rev. E Changes to Features... Changes to Specifications... Changes to Ordering Guide... Replaced TPCs and... Added Temperature Monitoring section... 7 Updated Figure... 7 Deleted Table I... 7 Updated Figure /0 Rev. C to Rev. D Updated TPCs...Universal Changes to Features... Changes to Electrical Specifications... Change to Absolute Maximum Ratings... Changes to Ordering Guide... Deleted Typical Electrical Characteristics table... Deleted Wafer Test Limits... Deleted Figure... 0/0 Rev. B to Rev. C Changes to Features... Changes to General Description... Changes to Simplified Schematic... Changes to Specifications... Changes to Absolute Maximum Ratings... Changes to Package Type... Changes to Ordering Guide... Updated to Outline Dimensions... Rev. I Page of

3 SPECIFICATIONS ELECTRICAL VIN = V, TA = C, unless otherwise noted. REF0 Table. REF0A/REF0E REF0/REF0H Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Output Voltage VO IL = 0 ma V Output Adjustment Range VTRIM RP = 0 kω ± ± ± ± % Output Voltage Noise en p-p 0. Hz to 0 Hz P, Z, and S Packages µv p-p J Package 0 0 µv p-p 88 Parts 0 0 µv p-p Line Regulation VIN = 8 V to 0 V %/V Load Regulation IL = 0 ma to 0 ma %/ma Turn-On Settling Time ton To ±0.% of final value µs Quiescent Supply Current ISY No load ma Load Current IL 0 0 ma Sink Current IS ma Short-Circuit Current ISC VO = ma Temperature Voltage Output 88C Product VT 0 0 mv P, S, J, and Z Packages VT 0 0 mv Guaranteed by design. Line and load regulation specifications include the effect of self-heating. During sink current test, the device meets the output voltage specified. Limit current in or out of Pin to 0 na and capacitance on Pin to 0 pf. Rev. I Page of

4 VIN = V, C TA + C for REF0A and REF0; 0 C TA 70 C for REF0E and REF0H; IL = 0 ma, unless otherwise noted. Table. REF0A/REF0E REF0/REF0H Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Output Voltage Change VOT 0 C TA 70 C % with Temperature, C TA + C % Output Voltage Temperature Coefficient TCVO 8. 0 ppm/ C Change in VO Temperature Coefficient RP = 0 kω ppm/% with Output Adjustment Line Regulation 0 C TA 70 C %/V VIN = 8 V to 0 V C TA + C %/V Load Regulation 0 C TA 70 C %/ma IL = 0 ma to 8 ma C TA + C %/ma Temperature Voltage Output Temperature TCVT Coefficient 88C Product.0.0 mv/ C P, S, J, and Z Packages.9.9 mv/ C ΔVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as a percentage of V. VMAX VMIN VOT = 00 V VOT specification applies trimmed to,000 V or untrimmed. TCVO is defined as VOT divided by the temperature range. V OT TCVO = 70 C Line and load regulation specifications include the effect of self-heating. Limit current in or out of Pin to 0 na and capacitance on Pin to 0 pf. Rev. I Page of

5 VIN = V, TA = C, unless otherwise noted. Table. REF0C REF0D Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Output Voltage VO IL = 0 ma V Output Adjustment Range VTRIM RP = 0 kω ±.7 ±.0 ±.0 ±.0 % Output Voltage Noise en p-p 0. Hz to 0 Hz P, Z, and S Packages µv p-p J Package 0 µv p-p 88 Parts 8 0 µv p-p Line Regulation VIN = 8 V to 0 V %/V Load Regulation IL = 0 ma to 8 ma %/ma IL = 0 ma to ma %/ma Turn-On Settling Time ton To ±0.% of final value µs Quiescent Supply Current ISY No load ma Load Current IL 8 8 ma Sink Current IS ma Short-Circuit Current ISC VO = ma Temperature Voltage Output 88C Product VT 0 0 mv P, S, J, and Z Packages VT 0 0 mv Guaranteed by design. Line and load regulation specifications include the effect of self-heating. During sink current test, the device meets the output voltage specified. Limit current in or out of Pin to 0 na and capacitance on Pin to 0 pf. Rev. I Page of

6 VIN = V, IL = 0 ma, 0 C TA 70 C for REF0CJ, REF0CZ, and REF0DP; and 0 C TA +8 C for REF0CP and REF0CS, unless otherwise noted. Table. REF0C REF0D Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Output Voltage Change VOT % with Temperature, Output Voltage Temperature Coefficient TCVO ppm/ C Change in VO Temperature Coefficient RP = 0 kω ppm/% with Output Adjustment Line Regulation VIN = 8 V to 0 V %/V Load Regulation IL = 0 ma to ma %/ma Temperature Voltage Output Temperature Coefficient TCVT 88C Product.0.0 mv/ C P, S, J, and Z Packages.9.9 mv/ C ΔVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as a percentage of V. VMAX VMIN VOT = 00 V VOT specification applies trimmed to,000 V or untrimmed. TCVO is defined as ΔVOT divided by the temperature range. VOT TCVO = 70 C Line and load regulation specifications include the effect of self-heating. Limit current in or out of Pin to 0 na and capacitance on Pin to 0 pf. Rev. I Page of

7 REF0 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Input Voltage Output Short-Circuit Duration to Ground or VIN 0 V Indefinite Storage Temperature Range J, RC, and Z Packages C to +0 C P Package C to + C Operating Temperature Range REF0A, REF0J, REF0RC C to + C REF0CJ, REF0CZ 0 C to 70 C REF0CP, REF0CS, REF0E, and REF0H 0 C to +8 C Lead Temperature Range (Soldering 0 sec) 00 C Absolute maximum ratings apply to both DICE packaged parts, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTAE Table. Package Type θja θjc Unit TO-99 (J) 70 C/W 8-Lead CERDIP (Z) C/W 8-Lead PDIP (P) 0 0 C/W 0-Terminal Ceramic LCC (RC) 0 0 C/W 8-Lead SOIC (S) 0 C/W θja is specified for worst-case mounting conditions; device in socket for TO, CERDIP, PDIP, and LCC packages; and device soldered to printed circuit board for SOIC package. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. I Page 7 of

8 REF0 TYPICAL PERFORMAE CHARACTERISTICS OUTPUT NOISE (µv p-p) 0k k 00 = V T A = C k 0k 00k M FREQUEY (Hz) Figure. Output Wideband Noise vs. Bandwidth (0. Hz to Frequency Indicated) 007-F-00 MAXIMUM LOAD CURRENT (ma) 0 T A = C INPUT VOLTAGE (V) Figure 8. Maximum Load Current vs. Input Voltage 007-F = V LINE REGULATION (db) = V T A = C k 0k 00k M FREQUEY (Hz) LINE REGULATION (%/V) F-00 LOAD REG T/LOAD REG ( C) TEMPERATURE ( C) 007-F-009 Figure. Line Regulation vs. Frequency Figure 9. Normalized Load Regulation ( IL = 0 ma) vs. Temperature PERCENT CHANGE IN OUTPUT VOLTAGE (%) = V C DEVICE IMMERSED IN 7 C OIL BATH TIME (s) Figure 7. Output Change Due to Thermal Shock 007-F-007 LINE REG T/LINE REG ( C) TEMPERATURE ( C) Figure 0. Normalized Line Regulation vs. Temperature 007-F-00 Rev. I Page 8 of

9 REF0 0.0 T A = C 0 = V LINE REGULATION (%/V) F-0 MAXIMUM LOAD CURRENT (ma) F INPUT VOLTAGE (V) TEMPERATURE ( C) Figure. Line Regulation vs. Input Voltage Figure. Maximum Load Current vs. Temperature. = V. QUIESCENT CURRENT (ma) F-0 TEMPERATURE ( C) Figure. Quiescent Current vs. Temperature Rev. I Page 9 of

10 REF0 OUTPUT ADJUSTMENT The REF0 trim terminal can be used to adjust the output voltage over a V ± 00 mv range. This feature lets the system designer trim system errors by setting the reference to a voltage other than V. The output also can be set to exactly.00 V or to. V for binary applications. Adjustment of the output does not significantly affect the temperature performance of the device. The temperature coefficient change is approximately 0.7 ppm/ C for 00 mv of output adjustment. +V U REF0 V OUT TEMP TRIM R 70kΩ V O pot 0kΩ R kω µF V O REF0 TEMP TRIM kω 0kΩ 0kΩ +V OP0 V +V V 007-F-0 Figure. Output Adjustment Circuit Figure. ± V Reference +V V O + +.V R.kΩ +8V REF0 V REF R.kΩ 7 REF0 8V 007-F-0 R V O + = (V REF ), R + R R V O = (V REF ) R + R +V O.V OP0 9V F-0 Figure. Burn-In Circuit Figure 7. ±. V Reference Rev. I Page 0 of

11 REF0 TEMPERATURE MONITORING V+ (V TO V) The REF0 provides a TEMP output (Pin ) that varies linearly with temperature. This output can be used to monitor the temperature change in the system. The voltage at VTEMP is approximately 0 mv at C, and the temperature coefficient is approximately.9 mv/ C (see Figure 8) = 9V SAMPLE SIZE = HEATING ELEMENT V O REF0 TEMP (SEE NOTE ) R (9.kΩ) R (.kω) R R.kΩ + 8 V+ CMP0V 7 R7 7kΩ TEMP PIN OUTPUT (mv) Z PACKAGE AND 8 PRODUCT V TEMP / T =.mv/ C V TEMP / T =.9mV/ C J, S, AND P PACKAGES TEMPERATURE ( C) Figure 8. Voltage at TEMP Pin vs. Temperature A voltage change of 9. mv at the TEMP pin corresponds to a 0 C change in temperature. The TEMP function is provided as a convenience rather than a precise feature. Since the voltage at the TEMP node is acquired from the band gap core, current pulling from this pin has a significant effect on VOUT. Care must be taken to buffer the TEMP output with a suitable low bias current op amp, such as the AD80, AD80, or OP77. Using any of these three op amps results in less than a 00 µv change in ΔVOUT (see Figure 9). Without buffering, even tens of microamps drawn from the TEMP pin can cause VOUT to fall out of specification. V TEMP.9mV/ C U V V+ OP77 V TEMP U REF0 Figure 9. Temperature Monitoring V OUT TRIM V O 007-F F-07 R.kΩ NOTES. REF0 SHOULD BE THERMALLY CONNECTED TO SUBSTAE BEING HEATED.. NUMBERS IN PARENTHESES ARE FOR A SETPOINT TEMPERATURE OF 0 C.. R = R R R R.7kΩ Figure 0. Temperature Controller REFEREE STACK WITH EXCELLENT LINE REGULATION Two REF0s and one REF0 can be stacked to yield.00 V,.00 V, and.00 V outputs. An additional advantage is nearperfect line regulation of the.0 V and.0 V output. A 7 V to V input change produces an output change that is less than the noise voltage of the devices. A load bypass resistor (RB) provides a path for the supply current (ISY) of the.00 V regulator. In general, any number of REF0s and REF0s can be stacked this way. For example, 0 devices yield 0 outputs in V or 0 V steps. The line voltage can change from 00 V to 0 V. Care must be taken, however, to ensure that the total load currents do not exceed the maximum usable current (typically ma). 7V TO V VO REF0 TRIM VO VO REF0 TRIM V 0kΩ 0V 0kΩ V 007-F-09 REF0 TRIM 0kΩ R B.8kΩ 007-F-00 Figure. Reference Stack Rev. I Page of

12 REF0 PRECISION CURRENT SOURCE A current source with V output compliance and excellent output impedance can be obtained using this circuit. REF0 keeps the line voltage and power dissipation constant in the device; the only important error consideration at room temperature is the negative supply rejection of the op amp. The typical µv/v PSRR of the OP0E creates a 0 ppm change ( µv/v V/ V) in output current over a V range. For example, a ma current source can be built (R = kω) with 0 MΩ output impedance. V R O = 0 0 ma V O +0V REF0 SUPPLY BYPASSING For best results, it is recommended that the power supply pin be bypassed with a 0. µf disc ceramic capacitor. TEMP I OUT VOLTAGE COMPLIAE: 9V TO +V V O REF0 V TRIM R I OUT = + V R Figure. Current Sink + ma 007-F-0 V O REF0 kω +V MSB LSB kω +V kω B B B B B B B7 B8 V IN VO l O R DAC08 C (TRIM FOR 0.µF REF0 l O CALIBRATION) V+ V C C V LC OP0 E O R kω C +V V V 7 Figure. DAC Reference V OP0E O = 0V TO V +7.V (±0%) +7.V V I O = V R VO REF0HJ R 0kΩ V O (+) = +V Figure. Precision Current Source R V.kΩ A / OP0CK 007-F F-0 V O REF0 TEMP TRIM R I OUT = + V R + ma VOLTAGE COMPLIAE: V TO +8V I OUT 007-F-0 / OP0CK R kω 7.V 7.V A R kω 7.V (±0%) V O ( ) = V 007-F-0 Figure. Current Source Figure. ± V Reference Rev. I Page of

13 REF0 OUTLINE DIMENSIONS 0.00 (0.) MIN 0.0 (.0) MAX 0.00 (.08) MAX 0.00 (.) BSC 0.0 (0.9) MAX 0.00 (.08) 0. (.8) 0.0 (0.8) 0.0 (0.) (.78) 0.00 (0.7) (7.87) 0.0 (.9) 0.00 (.) 0.0 (0.8) 0.0 (.8) MIN SEATING PLANE (8.) 0.90 (7.7) 0.0 (0.8) (0.0) (9.0) 0.0 (8.) 0.0 (8.) 0.00 (7.7) 0.80 (.70) 0.0 (.9) REFEREE PLANE (.70) MIN 0.00 (.) MIN (.7) MAX (.08) BSC (.) BSC (0.8) (.) (.0) MAX 0.00 (0.) BSC 0.00 (0.8) (.0) (0.) 0.00 (0.) 0.00 (0.) (0.7) BSC BASE & SEATING PLANE (.0) 0.00 (.) 0.00 (.) (0.9) CONTROLLING DIMENSIONS ARE IN IHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF IH EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 7. 8-Lead Ceramic Dual In-Line Package [CERDIP] Z-Suffix (Q-8) Dimensions shown in inches and (millimeters) COMPLIANT TO JEDEC STANDARDS MO-00-AK CONTROLLING DIMENSIONS ARE IN IHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF IH EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 9. 8-Lead Metal Header Package [TO-99] J-Suffix (H-08) Dimensions shown in inches and (millimeters) PIN 0.0 (.) MAX 0.0 (.8) 0.0 (.0) 0. (.9) 0.0 (0.) 0.08 (0.) 0.0 (0.) 0.00 (0.) 0. (9.7) 0. (9.0) (.) BSC (.78) 0.00 (.) 0.0 (.) 0.80 (7.) 0.0 (.) 0.0 (.0) 0.0 (0.8) MIN SEATING PLANE 0.00 (0.) MIN 0.00 (.) MAX 0.0 (0.8) GAUGE PLANE 0. (8.) 0.0 (7.87) 0.00 (7.) 0.0 (0.9) MAX COMPLIANT TO JEDEC STANDARDS MS-00-BA CONTROLLING DIMENSIONS ARE IN IHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF IH EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 0.9 (.9) 0.0 (.0) 0. (.9) 0.0 (0.) 0.00 (0.) (0.0) 0.8 (9.09) 0. (8.9) SQ 0.00 (.) 0.0 (.) 0.8 (9.09) MAX SQ (.) 0.0 (.7) 0.07 (.9) REF 0.09 (.) 0.07 (.90) 0.0 (0.8) (0.8) R TYP 0.07 (.9) REF 0.0 (.0) 0.0 (.) 0 CONTROLLING DIMENSIONS ARE IN IHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF IH EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 9 8 BOTTOM VIEW 0.00 (.08) REF 0.00 (.) REF 0.0 (0.8) MIN (.8) BSC 0.08 (0.7) 0.0 (0.) 0.00 (.7) BSC TYP Figure 8. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body P-Suffix (N-8) Dimensions shown in inches and (millimeters) Figure 0. 0-Terminal Ceramic Leadless Chip Carrier [LCC] RC-Suffix (E-0A) Dimensions shown in inches and (millimeters) Rev. I Page of

14 REF0.00 (0.98).80 (0.890).00 (0.7).80 (0.97) 8.0 (0.0).80 (0.8) 0. (0.0098) 0.0 (0.000) COPLANARITY (0.000) BSC SEATING PLANE.7 (0.088). (0.0) 0. (0.00) 0. (0.0) 0. (0.0098) 0.7 (0.007) (0.09) 0. (0.0099).7 (0.000) 0.0 (0.07) COMPLIANT TO JEDEC STANDARDS MS-0-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; IH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 8-Lead Standard Small Outline Package [SOIC] Narrow Body S-Suffix (R-8) Dimensions shown in millimeters and (inches) Rev. I Page of

15 REF0 ORDERING GUIDE TA = C Model VOS Max (mv) Temperature Range Package Description Package Option REF0AJ/88C ± C to + C 8-Lead TO-99 J-Suffix (H-08) REF0AZ ± C to + C 8-Lead CERDIP Z-Suffix (Q-8) REF0AZ/88C ± C to + C 8-Lead CERDIP Z-Suffix (Q-8) REF0CJ ±0 0 C to 70 C 8-Lead TO-99 J-Suffix (H-08) REF0CP ±0 0 C to +8 C 8-Lead PDIP P-Suffix (N-8) REF0CPZ ±0 0 C to +8 C 8-Lead PDIP P-Suffix (N-8) REF0CS ±0 0 C to +8 C 8-Lead SOIC S-Suffix (R-8) REF0CS-REEL ±0 0 C to +8 C 8-Lead SOIC S-Suffix (R-8) REF0CS-REEL7 ±0 0 C to +8 C 8-Lead SOIC S-Suffix (R-8) REF0CSZ ±0 0 C to +8 C 8-Lead SOIC S-Suffix (R-8) REF0CSZ-REEL ±0 0 C to +8 C 8-Lead SOIC S-Suffix (R-8) REF0CSZ-REEL7 ±0 0 C to +8 C 8-Lead SOIC S-Suffix (R-8) REF0CZ ±0 0 C to 70 C 8-Lead CERDIP Z-Suffix (Q-8) REF0DP ±00 0 C to 70 C 8-Lead PDIP P-Suffix (N-8) REF0DPZ ±00 0 C to 70 C 8-Lead PDIP P-Suffix (N-8) REF0EJ ± 0 C to +8 C 8-Lead TO-99 J-Suffix (H-08) REF0EZ ± 0 C to +8 C 8-Lead CERDIP Z-Suffix (Q-8) REF0J ± C to + C 8-Lead TO-99 J-Suffix (H-08) REF0HJ ± 0 C to +8 C 8-Lead TO-99 J-Suffix (H-08) REF0HZ ± 0 C to +8 C 8-Lead CERDIP Z-Suffix (Q-8) REF0HP ± 0 C to +8 C 8-Lead PDIP P-Suffix (N-8) REF0HPZ ± 0 C to +8 C 8-Lead PDIP P-Suffix (N-8) REF0HS ± 0 C to +8 C 8-Lead SOIC S-Suffix (R-8) REF0HSZ ± 0 C to +8 C 8-Lead SOIC S-Suffix (R-8) REF0RC/88 ± C to + C 0-Lead LCC RC-Suffix (E-0A) REF0Z ± C to + C 8-Lead CERDIP Z-Suffix (Q-8) Consult sales for 88 data sheet. Z = Pb-free part. Rev. I Page of

MAX TEMPCO (ppm/ C) INITIAL ERROR (mv)

MAX TEMPCO (ppm/ C) INITIAL ERROR (mv) 19-0887; Rev 7; /07 General Description The are industry-standard precision voltage references. The stable 10V output of the REF01 can be adjusted over a ±% range with minimal effect on temperature stability.