SI/PI PCB Design Considerations for Thermal

Transcription

1 SI/PI PCB Design Considerations for Thermal HEESOO LEE Lead Application Developer PIPro Power Integrity Professional

2 Agenda Thermal effects on Signal Integrity and Power Integrity Case study Conclusion Q&A 2

3 Thermal Effects on Signal Integrity and Power Integrity

4 Thermal Effects: Mechanical or Electrical? Thermal Considerations Today, thermal designs and analyses are, by and large, mechanical design engineers tasks However, due to higher data speed, increasing complexity of systems, lower voltage and timing margins, the PCBs thermal effects on signal integrity and power integrity are also need to be carefully considered Temperature rise changes PCBs electrical properties 1. Copper s temperature coefficient is at 20 C. The resistance of copper increases 0.393% per 1 C 2. Dk and Df value increase with the temperature rise 3. Electrical energy (power dissipation) is transformed into heat 4. Electric current flow through a conductor generates heat (Joule Heating, or Ohmic/Resistive Heating) 4

5 Thermal Effects on Signal and Power Integrity 1. Copper s Conductivity/Resistivity Copper s resistivity increases with PCB temperature rise: Channel s Insertion loss increases Signal Integrity Power-rails DC IR-drop increases Power Integrity Cu Temperature Ex: Eye closure from 23 C to 75 C 6 inch line, 28Gbps, 0.5Vpp, 20ps risetime 23 C 75 Δ Δ 2.24 db 70 C 20 Δ Δ 5.46dB EH: 225mV EW: 30.89ps EH: 186mV EW: 29.82ps Eye Closure 39mV, 1.07ps 5

6 Thermal Effects on Signal and Power Integrity 2. Substrate s Properties Dk/Df Dk/Df increases with PCB temperature rise Tables: Thermal Effects on PCB Laminate Material Dielectric Constant and Dissipation Factor, Scott Hinaga Step response: Risetime degradation Higher Dk results in longer time delay, lowered impedance, higher crosstalk, etc Higher Df results in longer risetime and increased ISI Ex: Df = vs. Df= with 6 inch line, 28Gbps, 0.5Vpp, 20ps risetime Df = 0.05 Df = 0.02 Df = Df = C 75 C Eye Closure: 65mV, 3.03ps EH: 225mV EW: 30.89ps EH: 160mV EW: 27.86ps 6

7 Thermal Effects on Signal and Power Integrity Combined Results Conductivity and Dk/Df PCB temperature from 23 C to 75 C on 6 inch microstrip line Total Eye closure: 101mV, 5.35ps 23 C 75 C Complex dependencies: Line length, data/edge speed, etc 7

8 Thermal Effects on Signal and Power Integrity 3. Electric Power Dissipation Heat Source Electric power dissipation produces heat (energy), which becomes a heat source that may alter PCB temperature Simple power and temperature calculation Electric power dissipation Temperature (Heat source) - Ex: Power dissipation = 5W, R TH = 20 C/W - ΔT = Q * R TH = 5W * 20 C/W = 100 C Temperature Maximum electric power dissipation - Ex: R TH = 20 C/W, T J = 125 C, T A = 25 C P max = 5W - Ex: R TH = 20 C/W, T J = 125 C, T A = 65 C P max = 3W P max = T J TA R TH 8

9 Thermal Effects on Signal and Power Integrity 4. Joule Heating Heat Source Electric current flow through a conductor generates heat (Joule Heating, or Ohmic/Resistive Heating) Joule-Lenz law: P I 2 R 1 mω (½oz) Square Copper s sheet resistance 6 mω (½oz) 1oz copper ~ 0.5 mω/square, ½oz copper ~ 1 mω/square To reduce Joule heating, it is better to make the power rail square Square power rail ~9.2 C higher Narrower power rail ~15 C higher 9

10 The Need of Electro-Thermal PIPro (Power Integrity Professional) PCB thermal behavior is very complex process affected by the power dissipation of VRM and sinks, thermal pads, heat sinks, and joule heating, which are all interacting each other Electro Thermal numerical analysis is absolutely necessary for accurate prediction of PCB thermal behavior Thermal (copper s resistivity increase) Joule Heating (temperature rise) Thermal (copper s resistivity increase) Joule heating (temperature rise). This process is repeated until the temperature is converged to steady state Electric Thermal Electric Thermal Thermal Electric 10

11 Case Study 11

12 The Board Used for The Case Study Xilinx KCU105 UltraScale TM FPGA Evaluation Kit 9.27 inch 5 inch 16 layers PCB 1/25/

13 Power Scenario Planning for FPGA KCKU-040 UltraScale TM, 23.4W and 33W Power Usage FPGA devices can operate under a different device utilization More devices used may require more power delivered Will the power rails still meet the power specification under stressed conditions and what changes to the PCB temperature will be? Two scenarios 23.4W and 33W by Xilinx XPE (Xilinx Power Estimator) 23.4W, 250 LFM 33W, 250 LFM 1/25/

14 Power Rails Used for KCU-040 FPGA IR-Drop from Power Rails and Ground Planes Multiple power rails supplying power to FPGA KCU-105 Power Tree Map Multiple VRMs and multiple Sinks Include all power rails and grounds to accurately predict the true DC IR-Drop 1/25/

15 DC IR-Drop Power Map With higher device utilization, one of power rails fails (*) to meet the specification, 18mV higher IR-Drop 23.4W, 250 LFM 33W, 250 LFM Compare (*): The spec, here, is arbitrarily set as an example 1/25/

16 DC IR-Drop Power/Ground Vias With 2A max via current violation warning, there are 2 vias detected for 23.4W case and 5 vias for 33W case 23.4W, 250 LFM 33W, 250 LFM 1/25/

17 DC IR-Drop Various Visual Aids/Plots Voltage drop, current flow, power density, etc Current crowding 1/25/

18 PCB Thermal Analysis Temperature Plot 25 C 35 C 50 C 60 C The board gets, in general, 9 C hotter (peak) with 33W case than 23.4W We can expect higher insertion loss with 10 C temperature rise, for example, 0.73dB higher at 50GHz 1/25/

19 PCB Electro-Thermal DC IR-Drop Joule Heating Electric current flow through a conductor generates heat (Joule Heating, or Ohmic/Resistive Heating) The temperature rise is proportional to the square of current flow and the conductor resistance, which eventually increase DC loss Power map comparison w/ and wo Electro-Thermal Additional IR-Drop due to Joule Heating 1/25/

20 DC IR-Drop Comprehensive Full Report Generation Supports both.html and.docx 1/25/

21 More Than Just PI Simultaneous Switching Noise Analysis Channel + PDN model (PowerAware) provides an accurate SSN analysis Channels TX IBIS RX IBIS Kintex_FPGA Pin Voltage Power Rails 1/25/

22 Conclusion The thermal design considerations become an important task for PCB design engineers with faster speed and higher power design requirements The PCB temperature rise give rise to the performance degradation in power and signal integrity The interaction between thermal and electrical must be carefully taken care of 22

23 Q&A 1/25/

24 Thank you for attending! Questions? Want More Resources? Signal Integrity & Power Integrity Resources Stay ahead of evolving high-speed digital design challenges with Keysight s design and test software. Try it for free for 30 days with absolutely no obligation. Technologies