EFFECTIVE ROUGHNESS DIELECTRIC TO REPRESENT COPPER FOIL ROUGHNESS IN PRINTED CIRCUIT BOARDS 14-TH4

Transcription

1 EFFECTIVE ROUGHNESS DIELECTRIC TO REPRESENT COPPER FOIL ROUGHNESS IN PRINTED CIRCUIT BOARDS 14-TH4 Marina Koledintseva (Oracle), Oleg Kashurkin (Missouri S&T), Tracey Vincent (CST of America), and Scott Hinaga (Cisco Systems)

2 Abstract Conductor roughness must be included in simulations of PCB designs at frequencies above a few gigahertz - to accurately predict the insertion loss and delay time on the transmission lines. An effective roughness dielectric (ERD) model can be used to substitute an inhomogeneous interface between copper foil and laminate dielectric in a PCB. It is tempting to have an analytical model to predict ERD parameters. We provide a basis for such a model. However, an empirical approach based on the matching between the measured and numerically modeled results has proven to be simpler and more efficient. Based on the extracted ERD parameters design curves have been built. The verification using 3D full-wave numerical simulations of a set of stripline test vehicles has been done. The parameters of an ambient laminate dielectric free of conductor roughness effects in the striplines are determined using differential extrapolation roughness measurement (DERM) technique. The agreement of the 3D full-wave modeling results and measurements on multiple test structures validates the proposed approach.

3 Outline I. Introduction II. Description of S3 Technique to Extract DK and DF of PCB Substrate Dielectrics III. Copper Foil Roughness Quantification IV. PCB Dielectric Material Parameters Extraction V. Extraction of Effective Roughness Dielectric (ERD) Parameters VI. Validation of ERD Extracted Data by Numerical Simulations VII. Design Curves for Conductor Roughness Modeling in PCB Designs VIII. Conclusions 3

4 S 21, db S 11, db S3 Technique: from Measured S-parameters to DK & DF of a PCB Dielectric Substrate mil Test Lines Thru Test-Line 590 mil mil Line mil Line-2 Line-3 Line mil 872 mil 640 mil Periodic ground via wall mil Test lines for dielectric parameters extraction THRU OPEN mil 590 mil LINE mil 2176 mil 872 mil 640 mil LINE 2 LINE 3 LINE 4 New test lines For Crosssectional analysis 30 GHz 50 GHz Test-Line 5000 mil mil GHz Test Vehicle 50-GHz Test Vehicle Frequency, GHz GHz Test Vehicle 50-GHz Test Vehicle Frequency, GHz 4

5 S3 Technique to Extract DK & DF of a PCB Dielectric Substrate Measured S- parameters Causality, passivity, reciprocity check ABCD matrix parameters Total loss T C D Complex propagation constant arccosh( A D) ; T j line length Conductor roughness NOT taken into account Conductor roughness taken into account Curve-fitting total loss to terms containing angular frequency 2 P Q R - total loss T P - conductor loss C Q R or P - dielectric loss 2 D D T A. Koul, M. Koledintseva et al, Differential extrapolation method for separating dielectric and rough conductor losses in printed circuit boards, IEEE Trans. Electromag. Compat., vol. 54, no. 2, Apr. 2012, pp Model or experimentally retrieve conductor loss for a rough conductor in the transmission line modeled or experimental conductor loss * C Solving the system of equations for complex permittivity r r j r cos / 2 r r c D r r c c speed of light in vacuum sin / 2 - calculated dielectric loss * D T C Extracted Dk and Df: x y r= x and r= x x y x y Dk = 2 2 2cD c x and y r Df = tan = / r r Roughness characterization: Analytical Models Numerical Models Experimental 5

6 Copper Foil Types X Z Foils are mostly isotropic in X and Z 6

7 Roughness Profile Analysis & Quantification SEM or optical image Scale calculation Object selection Preprocessing noise removal Skin depth calculation & morphological processing Trace side selection Image Processing Part Trace profile (foreground) extraction High boost filtering Translation of pixel map to coordinate data A Rakov, S. De et al Quantification of conductor surface roughness profiles in printed circuit boards, IEEE Trans. Electromag. Compat., DOI: /TEMC , Roughness profile coding & maxima/minima searching Non-linear detrending Computer Vision Roughness Quantification Part Removal of artifacts Roughness quantification (Ar, Λr, QR) 7

8 y, m Roughness Profile Analysis & Quantification 5 Surface roughness profile image 4.5 Quasi-period A r Peak cutoff x, m S. De, A.Y. Gafarov, M.Y. Koledintseva, R.J. Stanley, J.L. Drewniak, and S. Hinaga, Semi-automatic copper foil surface roughness detection from PCB microsection images, Proc. Int. IEEE Symp. Electromag. Compat., Pittsburgh, PA, Aug. 5-10, 2012, pp

9 Metallic Inclusions Concentration Variation with Height Volume concentration,% Ar,um ACR STD Foil, foil side roughness y,um v f ( y) exp( y ) PDF x,um x,um Autocorrelation x,um

10 Basis for Analytical Model Development y t f ( ) k ( y) dy eff 0 0 eff incl matrix ( y) matrix 1 f ( y) matrix (1 f ( y)) Ny ( incl matrix ) F n f n 1 matrix eff metal ( eff, ) ( eff ) tan ( 1) 0 metal 4 matrix eff D. Marcuse, Theory of Dielectric Optical Waveguides (Optics and Photonics Series), Academic Press, 1991, Chapter 2. incl incl 1 j N y ln( a) 2 0 a 10

11 Geometrical Data of Test Vehicles Group BO Group CZ Group MB w 1, m w 2, m t, m P, m h 1, m h 2, m A r1, m A r2, m 1, m 2, m QR 1 QR 2 Σ QR STD VLP HVLP STD VLP HVLP STD VLP HVLP

12 Raw Measured Insertion Loss and Group Delay ( BO Group) 12

13 Dielectric Loss Extraction Using DERM 13

14 Dielectric Phase Constant Extraction Using DERM 14

15 Refined from Conductor Roughness DK & DF of PCB Laminate Dielectric (Megtron 6) 15

16 ERD Dielectric Extraction Procedure Measurements of S- parameters w1 Tr oxide Extraction of true DK and DF of PCB dielectric (DERM) w2 Tr foil 2D-FEM Model rough = rough -j rough Correction Not satisfied Criteria for acceptable agreement of measured and modeled S 21 (both IL & phase) Satisfied Extracted ERD rough = rough -j rough Validation by fullwave simulation 16

17 2D-FEM Model to Extract ERD Parameters 17

18 Modeled & Measured S-parameters for ERD Extraction 18

19 Scatter Plots for DK, DF, and VR of Roughness Layers 19

20 Validation by Full-wave 3D Numerical Modeling CST Studio Suite 3D (Full-wave FD MoM) model is used for validation of the extracted ERD data T. Vincent, M. Koledintseva, A. Ciccomancini, and S. Hinaga, Effective roughness dielectric in a PCB: measurement and full-wave simulation verification, IEEE Symp. Electromag. Compat., Raleigh, NC, 3-8 Aug. 2014, pp

21 Insertion Loss Agreement Validation 21

22 Phase Agreement Validation 22

23 Validation for Different Line Lengths 23

24 Power Dissipation Analysis 24

25 Design Curves for Effective Roughness Dielectric Parameters Sets 1,2,3 13mil traces Sets 4, 5 7 mil traces 25

26 Conclusions To model PCB designs, it is important to know the geometry of a transmission line, the correct roughness-independent DK and DF data of the laminate dielectric substrate used in this line, and a type of a foil. The parameters of a laminate dielectric substrate used in the modeling are determined using differential extrapolation roughness measurement technique (DERM). The effective roughness dielectric (ERD) approach to represent foil surface roughness in a PCB is validated using 3D full-wave simulations. Design curves (nomograms) to model roughness layers have been developed based on the collected data points from testing multiple test vehicles with different foils. If an electronics designer does not have possibilities of foil roughness inspection, e.g., using an SEM or optical microscopy cross-sectional analysis, the recommended design curves, or pre-computed values of complex permittivity and thickness of roughness dielectrics for the known types of foils may still be used in the numerical modeling. 26

27 Thank you! 27