The ESD5451R is available in DFP1006-2L package. Standard products are Pb-free and Halogen-free. Circuit diagram

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1 ESD5451R 1-Line, Bi-directional, Transient Voltage Suppressors http//: Descriptions The ESD5451R is a bi-directional TVS (Transient Voltage Suppressor). It is specifically designed to protect sensitive electronic components which are connected to low speed data lines and control lines from over-stress caused by ESD (Electrostatic Discharge), EFT (Electrical Fast Transients) and Lightning. DFP06-2L The ESD5451R may be used to provide ESD protection up to ±30kV (contact and air discharge) according to IEC , and withstand peak pulse current up to 8A (8/20μs) according to IEC Pin1 Pin2 The ESD5451R is available in DFP06-2L package. Standard products are Pb-free and Halogen-free. Circuit diagram Features Reverse stand-off voltage: ±5V Max Transient protection for each line according to IEC (ESD): ±30kV (contact and air discharge) IEC (EFT): 40A (5/50ns) IEC (surge): 8A (8/20μs) Capacitance: C J = 17.5pF typ. Low leakage current: I R < 1nA typ. Low clamping voltage: V CL = 11V I PP = 16A (TLP) Solid-state silicon technology Pin1 Top View Pin2 Applications Cellular handsets Tablets Laptops Other portable devices Network communication devices Order information Device Package Shipping ESD5451R-2/TR DFP06-2L 000/Tape&Reel Will Semiconductor Ltd. 1 Revision 1.4, 2018/04/23

2 Absolute maximum ratings ESD5451R Parameter Symbol Rating Unit Peak pulse power (t p = 8/20μs) P pk 80 W Peak pulse current (t p = 8/20μs) I PP 8 A ESD according to IEC air discharge V ESD ESD according to IEC contact discharge ±30 Junction temperature T J 125 Operation temperature T OP -40~85 Lead soldering temperature - SMT T L - SMT 260 Lead soldering temperature - manual T L manual <300 Storage temperature T STG -55~150 ±30 kv Electrical characteristics (T A =25, unless otherwise noted) I V RWM Reverse stand-off voltage I R V CL I PP Reverse leakage current Clamping voltage Peak pulse current I PP I HOLD V CL V TRIG V HOLD V BR V RWM I BR I TRIG I R I R I TRIG V RWM V BR V HOLD V TRIG V CL V I BR I HOLD I PP V TRIG Reverse trigger voltage I TRIG V BR I BR V HOLD I HOLD Reverse trigger current Reverse breakdown voltage Reverse breakdown current Reverse holding voltage Reverse holding current Definitions of electrical characteristics Will Semiconductor Ltd. 2 Revision 1.4, 2018/04/23

3 Electrical characteristics (T A =25, unless otherwise noted) Parameter Symbol Condition Min. Typ. Max. Unit Reverse stand-off voltage V RWM ±5 V Reverse leakage current I R V RWM = 5V <1 0 na Reverse breakdown voltage V BR I BR = 1mA 5.1 V Reverse holding voltage V HOLD I HOLD = 50mA 5.1 V Clamping voltage 1) V CL I PP = 16A, t p = 0ns 11 V Clamping voltage 2) V CL V ESD = 8kV 12 V I PP = 1A, t p = 8/20μs 6.5 V Clamping voltage 3) V CL I PP = 5A, t p = 8/20μs 8.5 V I PP = 8A, t p = 8/20μs V Dynamic resistance 1) R DYN 0.24 Ω Junction capacitance Notes: C J V R = 0V, f = 1MHz pf V R = 5V, f = 1MHz pf 1) TLP parameter: Z 0 = 50Ω, t p = 0ns, t r = 2ns, averaging window from 60ns to 80ns. R DYN is calculated from 4A to 16A. 2) Contact discharge mode, according to IEC ) Non-repetitive current pulse, according to IEC Will Semiconductor Ltd. 3 Revision 1.4, 2018/04/23

4 Typical characteristics (T A =25, unless otherwise noted) Peak pulse current (%) T T 1 Front time: T 1 = 1.25 T = 8 s Time to half-value: T 2 = 20 s T 2 20 Time ( s) 8/20μs waveform per IEC Current (%) ns t r = 0.7~1ns Time (ns) 60ns Contact discharge current waveform per IEC t V C - Clamping voltage (V) Pulse waveform: t p = 8/20μs Pin1 to Pin2 Pin2 to Pin1 C J - Junction capacitance (pf) f = 1MHz V AC = 50mV I PP - Peak pulse current (A) Clamping voltage vs. Peak pulse current V R - Reverse voltage (V) Capacitance vs. Reverse voltage 00 0 Peak pulse power (W) 0 % of Rated power Pulse time ( s) Non-repetitive peak pulse power vs. Pulse time T A - Ambient temperature ( ) Power derating vs. Ambient temperature Will Semiconductor Ltd. 4 Revision 1.4, 2018/04/23

5 Typical characteristics (T A =25, unless otherwise noted) ESD clamping (+8kV contact discharge per IEC ) ESD clamping (-8kV contact discharge per IEC ) TLP current (A) TLP voltage (V) TLP Measurement Z 0 = 50 t r = 2ns t p = 0ns Will Semiconductor Ltd. 5 Revision 1.4, 2018/04/23

6 Package outline dimensions DFP06-2L ESD5451R e W T L a Top View(Bottom View) Side View Symbol Dimensions in millimeter Min. Typ. Max. W L T a e 0.75 Typ. Will Semiconductor Ltd. 6 Revision 1.4, 2018/04/23

7 TAPE AND REEL INFORMATION Symbol A B C D E W W 1 Unit(mm) ± ± ± ± ± ± ±0.1 Symbol A 0 ±0.05 B 0 ±0.05 K 0 ±0.05 D P P 2 P 0 W E Unit(mm) F ± Will Semiconductor Ltd. 7 Revision 1.4, 2018/04/23

8 Recommended land pattern (Unit: mm) ESD5451R Notes: This recommended land pattern is for reference purposes only. Please consult your manufacturing group to ensure your PCB design guidelines are met. IR reflow and temperature of Soldering for Pb Free Peak Temp 260 (3~sec) Temperature ( ) Pre-Heat 175 (60~120sec) Peak Temp 245 (~20sec) 25 01:00:00 02:00:00 03:00:00 04:00:00 Time (min) IR reflow Pb Free Process suggestion profile (1) The solder recommend is Sn96.5/Ag 3.5 of 120 to 150μm (2) Ramp-up rate (217 to Peak) + 3 /second max (3) Temp. maintain at 175 +/ seconds max (4) Temp. maintain above seconds (5) Peak temperature range / - time within 5 of actually peak temperature (tp) ~20 seconds (6) Ramp down rate +6 /second max (7)Steel plate thickness 0.08mm Will Semiconductor Ltd. 8 Revision 1.4, 2018/04/23