Efficient Quantum Dot Cellular Automata (QCA) Implementation of Code Converters

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1 Efficient Quantum ot Cellular Automata (QCA) mplementation of Converters J. qbal, F. A. Khanday *, N. A. Shah epartment of Electronics and nstrumentation Technology, University of Kashmir, Srinagar , ndia * farooqsnn20@yahoo.co.in Abstract- Conventional CMS technology has a lot of limitations while scaling into a nano-level. Therefore, several alternative technologies have been proposed as solutions in the open literature. Quantum Cellular Automata (QCA) technology is one such technology which can be a perfect replacement of Complementary Metal xide Semiconductor (CMS) technology for digital designs. Several digital circuit designs using QCA have been reported in the open literature but to the author s best knowledge QCA based designs of code converters have not been given. Therefore, in this paper the QCA based implementation of code converters is introduced. The proposed QCA designs enjoy the features of small area, superior performance factors in respect of noise, circuit stability and low power dissipation. The operation of QCA circuit is simulated using QCA designer bistable vector simulation. Keyword- CMS; Quantum Cellular Automata; Combinational Circuits; Converters. NTRUCTN CMS technology is approaching its scaling limit very fast. From practical point of view this technology in nano-scales is facing a lot of problems. So in order to enhance the performance of a system, new nano-technology approaches should be taken into account. Quantum Cellular Automata [1, 2] is now one of the promising and emerging technologies which not only provide a solution at nano-scale, but also offer solutions to the problems that currently CMS technology is facing [3, 4]. QCA technology is based on the interaction of bi-stable QCA cells constructed from four quantum dots. The cell is charged with two free electrons, which are able to tunnel between adjacent dots. These electrons tend to occupy antipodal sites as a result of their mutual electrostatic repulsion. Thus, there exist two equivalent energetically minimal arrangements of the two electrons in the QCA cell, as shown in Fig. 1. These two arrangements are denoted as cell polarization P= +1 and P= -1. By using cell polarization P = +1 to represent logic 1 and P = -1 to represent logic 0, binary information is encoded in the charge configuration of the QCA cell [2, 5]. Fig. 1 QCA cell polarization t is possible to implement all combinational and sequential logic functions by properly arranging cells so that the polarization of one cell sets the polarization of a nearby cell [6]. According to previous studies, several logic gates and computing devices [6] are implemented with QCA. Basic implementations that have been reported are the binary wire [4], the majority gate [3], NT gate [3], XR gate [3], bit-serial adder [3, 7, 8, 9], full adder [10-12, 3, 13, 14], multiplier [15], multiplexer [12, 16], flip-flop [17-19], serial memory [20, 21], parallel memory [22], Arithmetic Logic Unit [12, 23], microprocessor [23], Programmable Logic Array (PLA) [24], etc. To the best knowledge of authors, the QCA design of code converters is not given in the open literature. n this paper an endeavor has been made to introduce the efficient QCA design of code converters.. BULNG BLCKS F QCA The fundamental QCA logic primitives include a QCA wire, QCA inverter, and QCA majority gate [4-6], as described below. A. QCA Wire n a QCA wire, the binary signal propagates from input to output because of the electrostatic interactions between cells. The propagation in a 90 QCA wire is shown in Fig. 2. ther than the 90 QCA wire, a 45 QCA wire can also be used. n this case, the propagation of the binary signal alternates between the two polarizations [4]. Fig. 2 QCA (90 0 ) and (45 0 ) wire

2 B. QCA nverter The QCA cells can be used to form the primitive logic gates. The simplest structure is the inverter shown in Fig. 3. The electrostatic interaction is inverted, because the quantum-dots corresponding to different polarizations are misaligned between the cells [3]. C. QCA Majority Gate Fig. 3 QCA inverter The QCA majority gate performs a three-input logic function. A layout of a QCA majority gate is shown in Fig. 4. Assuming the inputs are a, b and c, the logic function of the majority gate is given as M ( a, b, c) ab bc ac (1) Fig. 4 QCA majority gate The tendency of the majority device cell to move to a ground state ensures that it takes on the polarization of the majority of its neighbors. The device cell will tend to follow the majority polarization because it represents the lowest energy state [3]. By fixing the polarization of one input to the QCA majority gate as logic 1 or logic 0 an AN gate or R gate will be obtained, respectively, as shown in Fig. 5.. Fig. 5 2 input AN and 2 input R gate. QCA CLCKNG The QCA circuits require a clock, not only to synchronize and control information flow but also to provide the power to run the circuit since there is no external source for powering cells. With the use of four phases clocking scheme in controlling cells, QCA processes and forwards information within cells in an arranged timing scheme. Cells can be grouped into zones so that the field influencing all the cells in the zones will be the same. The QCA clocking scheme consists of four phases: Switch, Hold, Release and Relax. uring the Relax phase, the electrons are pulled into the middle dots, so the cell is in null state. uring the Switch phase, the interdot barrier is slowly raised which pushes the electrons into the corner dots, so the cell attains a definitive polarity under the influence of its neighbors (which are in the Hold phase). n the Hold phase, barriers are high and a cell retains its polarity and acts as input to the neighboring cells. Finally in the Release phase, barriers are lowered and the electrons are pulled into the middle dots so the cell loses its polarity. Here switching is adiabatic, i.e. the system remains very close to the energy ground state during transition, and the stationary state of each cell can be obtained by solving the time-independent Schrodinger equation. Clocking zones of a QCA circuit or system are arranged in periodic fashion, so that zones in the Hold phase are followed by zones in the Switch, Release and Relax phases. A signal is effectively latched when one clocking zone goes into the Hold phase and acts as input to the subsequent zone. n a clocked QCA circuit, information is transferred and processed in a pipelined fashion and allows multi-bit

3 information transfer for QCA through signal latching. All cells within the same zone are allowed to switch simultaneously, while cells in different zones are isolated. This clocking method makes the design of QCA different from CMS circuits. The Fig. 6 shows the four available clock signals. Each signal is phase shifted by 90 degrees. When the clock signal is low the cells are latched. When the clock signal is high the cells are relaxed and have no polarization. n between, the cells are either latching or relaxing when the clock is decreasing or increasing respectively. Fig. 6 Four phases of clock V. QCA MPLEMENTATN F CE CNVERTERS The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. t is sometimes necessary to use the output of one system as the input to the other. The conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus a code converter is a circuit that makes the two systems compatible even though each uses the different codes. ndeed, code converters have proven to be so effective that the National Security Agency (NSA) has made a career out of creating and breaking codes. converters are used for protecting private information from spies. They are also used to enhance data portability and tractability. converters have also found applications in algorithm generation and communication [25-30]. Some of the major codes are as follows: A. Binary A symbolic representation of data/information is called code. The base or radix of the binary number is 2. Hence, it has two independent symbols. The symbols used are 0 and 1. A binary digit is called a bit. A binary number consists of sequence of bits, each of which is either a 0 or 1. Each bit carries a weight based on its position relative to the binary point. The weight of each bit position is one power of 2 greater than the weight of the position to its immediate right. e. g. of binary number is which is equivalent to decimal number 35. B. BC Numeric codes used to represent decimal digits are called Binary d ecimal (BC) codes. A BC code is one, in which the digits of a decimal number are encoded-one at a time into group of four binary digits. There are a large number of BC codes in order to represent decimal digits 0, 1, 2, 9, it is necessary to use a sequence of at least four binary digits. Such a sequence of binary digits which represents a decimal digit is called code word. C. Gray s t is a non-weighted code; therefore, it is not suitable for arithmetic operations. t is a cyclic code because successive code words in this code differ in one bit position only i.e. it is a unit distance code. Applications of Gray :

n instrumentation and data acquisition system where linear or angular displacement is measured. n shaft encoders, input-output devices, A/ converters and the other peripheral equipment.

4 n instrumentation and data acquisition system where linear or angular displacement is measured. n shaft encoders, input-output devices, A/ converters and the other peripheral equipment.. Excess-3 t is a non-weighted code. t is also a self-complementing BC code used in decimal arithmetic units. The Excess-3 code for the decimal number is performed in the same manner as BC except that decimal number 3 is added to each decimal unit before encoding it to binary. The implementation of code converters in QCA needs their representation at conventional gate level first. For getting these representations, the conversion tables are depicted in Tables 1(a)-1(b). The logic expressions corresponding to Tables 1(a)-1(b) are as shown below Table 2. The QCA implementation layouts of the code converters given in Table 1(a)-(b) is depicted in Figs. 7(a)-7(i). The circuits of Figs. 7(a)-7(i) were designed and simulated using QCA designer tool. The overall QCA cell dimensions were defined as nm; the dot diameter was defined as 5 nm and the inter-cell distance as 2 nm. The various other specifications of the QCA tool which were used while performing the simulations are given in Table 3. Taking these specifications into consideration, the various performance parameters of the code converter designs were calculated and are given in Table 4. The simulation results of the designs, acquired by the QCA designer bistable vector simulation engine, are given in Figs. 8(a)-8(i). TABLE 1 TRUTH TABLE REPRESENTATNS F CE CNVERSNS Binary-Gray nput utput (a) 2421-BC Conversio 5421-BC BC BC-2421 BC-5421 BC-Excess-3 BC-Gray Excess-3- BC (b) (a)

5 (b) (c) (d)

6 (e) (f) (g)

7 (h) (i) Fig rotated QCA implementation of code converters. (a) binary to gray (b) 2421 to BC (c) 5421 to BC (d) BC to (e) BC to 2421 (f) BC to 5421 (g) BC to Ex-3 (h) BC to Gray (i) Ex-3 to BC (a)

8 (b) (c) (d)

9 (e) (f) (g)

BC to 5421 (g) BC to Ex-3 (h) BC to Gray (i) Ex-3 to BC TABLE 2 NPUT-UTPUT LGC EQUATNS F THE CE CNVERTERS Circuit W X Y Binary

10 (h) (i) Fig. 8 Simulation results of code converters (a) binary to gray (b) 2421 to BC (c) 5421 to BC (d) BC to (e) BC to 2421 (f) BC to 5421 (g) BC to Ex-3 (h) BC to Gray (i) Ex-3 to BC TABLE 2 NPUT-UTPUT LGC EQUATNS F THE CE CNVERTERS Circuit W X Y Binary to Gray A A B B C C 2421 to BC BC BC AB A C 5421 to BC A A B BC to BC to 2421 A C A BC B B BC BC C A BC B A BC B A BC BC A AB BC to 5421 A B A C A A BC to EX-3 A BC B BC B BC C BC to Gray A A B B C C EX-3 T BC AB AC B BC BC C

11 TABLE 3 SPECFCATNS F QCA TL Parameter Value Number of Samples Radius of Effect Convergence Tolerance Relative Permittivity Clock High e-022 Clock Low e-023 Clock Shift e+000 Clock Amplitude Factor Layer Separation Maximum terations per Sample 100 TABLE 4 CALCULATE PERFRMANCE PARAMETERS F THE CE CNVERTERS Circuit Total No of cells Cell Area (µm 2 ) Total Area (µm 2 ) 2421 to BC T BC BC T BC T BC T BC T EX BC T GRAY BNARY T GRAY EX-3 T BC Latency in clock zones V. CNCLUSN The design and simulation of a QCA code converter circuits has been presented in this paper. The operation of the converters has been analyzed using QCA designer bistable vector simulation. The designs are efficient in the sense that they contain less number of cells, utilize less number of clock phases and have significantly smaller maximum wire length which leads to kink-free operation at higher operating temperature. REFERENCES [1] C. S. Lent, P.. Tougaw, W. Porod, and G. H. Bernstein, Quantum cellular automata, Nanotechnology, vol. 4, iss. 1, pp , January [2] P.. Tougaw, C. S. Lent, and W. Porod, Bistable saturation in coupled quantum-dot cells, Journal of Applied Physics, vol. 74, iss. 5, pp , September 1, [3] P.. Tougaw and C. S. Lent, Logical devices implemented using quantum cellular automata, Journal of Applied Physics, vol. 75, iss. 3, pp , February 1, [4] C.S. Lent and P.. Tougaw, Lines of interacting quantum-dot cells: A binary wire, Journal of Applied Physics, vol. 74, iss. 10, pp , November 15, [5] C. S. Lent, P.. Tougaw, and W. Porod, Bistable saturation in coupled quantum dots for quantum cellular automata, Applied Physics Letters, vol. 62, iss. 7, pp , February 15, [6] C. S. Lent and P.. Tougaw, A device architecture for computing with quantum dots, Proceedings of the EEE, vol. 85, iss. 4, pp , April [7] P.. Tougaw and C. S. Lent, ynamic behavior of quantum cellular automata, Journal of Applied Physics, vol. 80, pp , [8] A.. rlov,. Amlani, G.H. Bernstein, C. S. Lent and G.L. Snider, Realization of a functional cell for quantum-dot cellular automata, Science, vol. 277, pp , [9] H. P. Wong,. J. Frank, P. M.Solomon, C. H. J. Wann, and J. J. Welser, Nanoscale CMS, Proceedings of the EEE, vol. 87, p. 537, [10] C. S. Lent, and P.. Tougaw, A device architecture for computing with quantum dots, Proc. EEE, vol. 85, pp , [11] T. Lantz and E. Peskin, A QCA implementation of a configurable logic block for an FPGA, EEE nternational Conference on Reconfigurable Computing and FPGA s, San Luis Potosi, Mexico, pp. 1-10, [12] A. Gin, S. Williams, H. Meng and P.. Tougaw, Hierarchical design of quantum-dot cellular automata devices, Applied Physics, vol. 5, pp , [13] K. Kim, K. Wu, and R. Karri, The robust QCA adder designs using composable QCA building blocks, EEE Transactions on

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Design of Optimized Quantum-dot Cellular Automata RS Flip Flops

Int. J. Nanosci. Nanotechnol., Vol. 13, No. 1, March. 2017, pp. 53-58 Design of Optimized Quantum-dot Cellular Automata RS Flip Flops A. Rezaei* 1 Electrical Engineering Department, Kermanshah University