Neotec Semiconductor Ltd. 新德科技股份有限公司

Transcription

1 rystalfontz Neotec emiconductor Ltd. L river INTROUTION The is a L driver LI that is fabricated by low power MO high voltage process technology. In segment drive mode, it can be interfaced in -bit serial or -bit parallel method by the controller. In common drive mode, dual type mode is applicable. And in segment mode application, the power down function reduces power consumption. FEATURE Power supply voltage:+5 V±0%, + V±0% upply voltage for display: 6 to V (V -V EE ) -bit parallel/-bit serial data processing (in segment mode).. ingle mode operation / dual mode operation (in common mode). Power down function (in segment mode). Applicable L duty:/6 ~ /56 Interface OM(cascade) RIVER EG(cascade) High voltage MO process. Available PKG type : bare chip, 00-LQFP, 00-QFP /

2 rystalfontz Neotec emiconductor Ltd. L river PKG TYPE PKG THIKNE PKG IZE PA PITH PA WITH PA LENGTH = 00-LQFP =.0 (± 0.05) mm =.00 (± 0.0) X.00 (± 0.0) mm = 0.5 mm = 0.0 ( +0.0,-0.0) mm =.0 (±0.) mm /

3 rystalfontz Neotec emiconductor Ltd. L river PKG TYPE PKG THIKNE PKG IZE PA PITH PA WITH PA LENGTH = 00-QFP =.00 (± 0.0) mm =.0(± 0.0) X. (± 0.0) mm = 0.65 mm = 0.0 (± 0.0) mm =. (± 0.0) mm /

4 rystalfontz Neotec emiconductor Ltd. L river PA IAGRAM Note: Please connects the substrate to V or Floating /

5 rystalfontz Neotec emiconductor Ltd. L river PA LOATION Pad No. Pad name X Y Pad No. Pad name X Y ERB VEE V V V V M IPOFFB V HL V _R _M _L _I L AM L ELB /

6 rystalfontz Neotec emiconductor Ltd. L river BLOK IAGRAM V0 V V V5 0-bit -level driver VEE M IPOFFB Output level selector LK 0-bit level driver bit data latch / common data bidirectional shift register _I _L _M _R K 0 X -bits segment data bidirectional shift register / L L lock control ata latch control AM Power down function ERB V V ELB 6/

7 rystalfontz Neotec emiconductor Ltd. L river BLOK ERIPTION NAME FUNTION OM / EG lock control Generates latch clock (LK), shift clock (K) and control clock timing according to the input of L, L and control inputs (, AM). In common driver application mode, this block generates the shift clock (LK) for the common data Bi-directional shift register. OM / EG etermines the direction of segment data shift, and input data of each ata latch Bi-directional shift register. In -bit segment data ata latch parallel transfer mode, data is shifted by a -bit unit. In common EG control driver application mode, data is transferred to the common data shift register directly, which disables this block. Power down function Output level selector 0x-bitsegm ent data bi-directional shift register 0-bit data latch / common data bi-directional shift register 0-bit level shifter 0-bit -level driver ontrols the clock enable state of the current driver according to the input value of enable pin (ELB or ERB). If enable input value is Low, every clock of the current driver is enabled and the clock control block works. But if enable input is High, current driver is disabled and the input data value has no effect on the output level. o power consumption can be lowered. ontrols the output voltage level according to the input control pin (M and IPOFFB) (refer to PIN ERIPTION). tores output data value by shifting the input values. In -bit serial interface mode application, all 0 shift clocks (K) are needed to store all the display data. But in -bit parallel transfer mode application, only 0 clocks are needed. In common driver application mode, this block does not work. In segment driver application mode, the data from the 0x-bit segment data shift register are latched for segment driver output. In single-type common driver application, -bit input data (from L or R pin) is shifted and latched by the direction according to the HL signal input. In dual-type common application mode, 0-bit registers are divided by two blocks and controlled Independently (refer to NOTE ). Voltage level shifter block for high voltage part. The inputs of this block are of logical voltage level and the outputs of this block are at high voltage level value. These values are input in to the driver. elects the output voltage level according to M and latched data value. If the data value is "High" the driver output is at selected voltage level (V0 or V5), and in the reverse case the driver output value is at the non-selected level (V or V). In segment driver application mode, non-selected output value is V or V and when in common driver application, this value becomes V or V. EG OM / EG EG OM / EG EG EG /

8 rystalfontz Neotec emiconductor Ltd. L river PIN ERIPTION PIN I/O NAME FUNTION INTERFAE Logical "High" input port (+5V±0%, +V± V Power 0%) Power V supply 0V (GN) VEE Logical "Low" for high voltage part L driver Bias supply voltage input to drive the L. V0,V, output Bias voltage divided by the resistance is I Power V,V5 voltage usually used as a supply voltage source (refer level to NOTE ). ~0 L M L O I I I L driver output ata shift clock A signal for L driver output ata latch clock isplay data output pin which corresponds to the respective latch contents. One of V0, V, V and V5 is selected as a display driving voltage source according to the combination of the latched data level and M signal (refer to NOTE ). lock pulse input for the bi-directional shift register. In segment driver application mode, the data is shifted to 0 x-bit segment data shift. The clock pulse, which was input when the enable bit (ELB/ERB) is in not active condition, is invalid. In common driver application mode, the data is shifted to 0-bit common data bi-directional shift register by the L clock. Hence, this clock pin is not used (Open or connect this pin to V). Alternate signal input pin for L driving. Normal frame inversion signal is input in to this pin. In segment driver application mode, this signal is used for latching the shift register contents at the falling edge of this clock pulse. L pulse "High" level initializes power-down function block. In common driver application mode, L is used as a shifting clock of common output data. L ontroller ontroller ontroller /

9 rystalfontz Neotec emiconductor Ltd. L river PIN ERIPTION (ONTINUE) PIN I/O NAME FUNTION INTERFAE ontrol input pin to fix the driver output IPOFFB I (~0) to V0 level, during "Low" value isplay input. L becomes non-selected by V0 level OFF control output from every output of segment drivers and every output of common drivers. ontroller I OM / EG mode control When = "Low", is used as an 0-bit segment driver. When = "High", is set to an 0-bit common driver According to the input value of the AM and the pin, application mode of is differs as shown below. V/V AM I Application mode select AM Application mode OM/EG 0 0 -bit parallel interface mode 0 -bit serial interface mode EG 0 ingle type application Mode ual type application mode OM V/V _I, _L, _M, _R I/O isplay data input/ serial input data/ left, right data input output -In segment driver mode, these pins are used as -bit data input pin (when -bit parallel interface mode AM= low ), or _I is used as serial data input pin and other pins are not used (connect these to V) (when -bit serial interface mode AM= high ). -In common driver mode, the data is shifted from _L (_R) to _R (_L), when in single interface mode (AM= Low ). In dual-type application case, the data are shifted from _L and _M (_R and _M) to _R(_L). In each case the direction of the data shift and the connection of data pins are determined by HL input (refer to NOTE, NOT ). ontroller 9/

10 rystalfontz Neotec emiconductor Ltd. L river PIN ERIPTION (ONTINUE) PIN I/O NAME FUNTION INTERFAE HL I When HL = "Low", data is shifted from left to hift right. direction When HL = "High", the direction is reversed. control (refer to NOTE) -In segment driver mode, the internal operation is enabled only when enable input (ELB or ERB) is "Low" (power down function). When several drivers a serially connected, the enable state of each driver is shifted according to the HL input. onnect these pins as below. Enable data V/V ELB, ERB I/O input/ egment driver output HL ELB ERB L Output (open) Input (V) H Input (V) Output(open) -In common driver mode, the power down function is not used. Open these pins. NOTE. Output level control "X": don't care M Latched data IPOFFB Output level (~0) EG Mode OM Mode L L H V(V) V(V) L H H V0 V5 H L H V(V) V(V) H H H V5 V0 X X L V0 V0 0/

11 rystalfontz Neotec emiconductor Ltd. L river NOTE. L riving Voltage Application ircuit () egment driver application ( = Low ) () ommon driver application ( = High ) /

12 rystalfontz Neotec emiconductor Ltd. L river NOTE. ata hift irection according to ontrol ignals () When = Low (segment driver application) AM HL Application ata irection mode Input pin L L -bit parallel data transfer mode (EG) Last data hift direction 5 6 Frist data 9 0 _I, _L, _M, _R H Frist data hift direction Last data L H H -bit serial data transfer mode (EG) Last data (_I) hift direction Frist data 9 0 _I Frist data hift direction Last data /

13 rystalfontz Neotec emiconductor Ltd. L river () When = High (common driver application) AM HL Application ata irection mode L hift direction Input pin _L L H ingle-type Application mode (OM) Input data (_L) hift direction Output data (_R) 9 0 _R Output data (_L) Input data (_R) hift direction L _L, _M H H ual-type Application mode (OM) Input data (_L) Input data (_M) hift direction Output data (_R) 9 0 _R, _M Output data (_L) Input data (_M) Input data (_R) /

14 rystalfontz Neotec emiconductor Ltd. L river NOTE. Usage of ata Pins OM / EG ( pin) EG ( = Low ) OM ( = High ) Application mode (AM pin) -bit parallel interface mode (AM = Low ) -bit serial interface mode (AM = High ) single-type application mode (AM = Low ) dual-type application mode (AM = High ) ata interface pin HL _I _L _M _R X (input) (input) (input) (input) X I (input) onnect to V L L (input) Open R (output) open H L (output) R (input) M L L (input) R (output) (input) open L (output) M H R (input) (input) MAXIMUM ABOLUTE LIMIT haracteristic ymbol Value Unit Power supply voltage V -0.~+.0 river supply voltage V L 0~+0 V Input voltage V IN -0.~V +0. Operating temperature Topr -0~+5 torage temperature Tstg -55~+50 NOTE: Voltage greater than above may do damage to the circuit. /

15 rystalfontz Neotec emiconductor Ltd. ELETRIAL HARATERITI HARATERITI () egment river Application L river (V = 0V, Ta = - 0 ~ +5 ) haracteristic ymbol Test ondition Min. Typ. Max. Unit Operating V Voltage V L V IN =V -V EE 6 - V V - 0.V - V Input voltage () IH V IL V Input voltage () V OH I H =-0.mA V V OL I OH =-0.mA V Input leakage current () I IL V IN =V to V -0-0 Input leakage current () I IL V IN =V to V EE -5-5 μa On resistance() R ON I ON =00μA - kω I TBY f L =khz, M=V V PIN μa upply V =5V I current(5) f L =khz F M =0HZ V =V - - ma V =5V μa I EE NOTE:. Applied to L, L, ELB, ERB, _I - _R, HL, IPOFFB, M,, AM pin. ELB, ERB pin. V0, V, V, V5 pin. V L = V - V EE, V0 = V = 5V, V5= V EE = - V V = V -/n(v L ), V = V EE +/n(v L ), n = (/56 duty, / bias) 5. V0 = V, V =.V(V = 5V) or -0.06V (V = V), V = -9. V(V = 5V) or -9.9V (V = V), V5 = V EE = -V, no-load condition (/56 duty, / bias) -bit parallel interface mode I TBY : V = 5V, f L = 5.MHz, HL = V, IPOFFB = V, M = V, display data pattern = 0000 I : V = V, f L = MHz, display data pattern = 00 V = 5 V, f L = 5.MHz, display data pattern = 00 I EE : V = 5V, f L = 5.MHz, display data pattern = 00, V EE pin 5/

16 rystalfontz Neotec emiconductor Ltd. HARATERITI (ONTINUE) () ommon river Application L river (V = 0V, Ta = - 0 ~ +5 ) haracteristic ymbol Test ondition Min. Typ. Max. Unit Operating V Voltage V L V IN =V -V EE 6 - V V IH - 0.V - V Input voltage () V IL V V OH I H =-0.mA V Input voltage () V V OL I OH =-0.mA Input leakage I current () IL V IN =V to V -0-0 μa Input leakage I current () IL V IN =0V, V =5V(Pull up) Input leakage I current () IL V IN =V to V EE -5-5 On resistance(5) R ON I ON =00μA - kω I TBY f L =khz, M=V V PIN upply V =5V I μa current(6) f L =khz F M =0HZ V =V I EE V =5V NOTE:. Applied to L, _L (HL = LOW), _R (HL = HIGH), HL, IPOFFB, M,, AM pin. Pull-up input pins : L, _I, _M (AM = HIGH), ELB (HL = LOW), ERB (HL = HIGH). _L (HL = HIGH), _R (HL = LOW) pin. V0, V, V, V5 pin 5. V L = V -V EE, V0 = V = 5V, V5 = V EE = -V V = V -/n(v L ), V = V EE +/n(v L ), n = (/56 duty, / bias) 6. V0 = V, V =.5V (V = 5V) or.v (V = V), V = -.5V (V = 5 V) or -.V (V = V), V5 = V EE = - V, no-load condition (/56 duty, / bias) single-type mode operation : AM = V, HL = V, IPOFFB = V _I = _M = V, _R = OPEN, ELB = ERB = OPEN, I TBY : V = 5V, M = V, _L = V I : f M = 0Hz, _L = V V = V, display data pattern = , , , ,.. V = 5 V, display data pattern = , , , ,.. I EE : f M = 0Hz, _L = V V = 5V, current through V EE Pin, display data pattern = , , , /

17 rystalfontz Neotec emiconductor Ltd. A HARATERITI () egment river Application haracteristic ymbol Test condition L river (V = 0V, Ta = - 0 ~ +5 ) () V=5V±0% () V=V±0% Unit Min. Typ. Max. Min. Typ. Max. lock cycle time t Y uty=50% lock pulse width t WK lock rise/ fall time t R / t F ata set-up time t ata hold time t H lock set-up time t lock hold time t H ELB output 60 5 Propagation delay time t PHL ERB output ELB,ERB set-up time t PU ELB input ERB input IPOFFB low pulse width t WL μs IPOFFB clear time t ns M OUT propagation delay time t P L OUT propagation delay time t P L =5pF μs IPOFFB OUT propagation delay time t P () ommon river Application (V = 0V, Ta = - 0 ~ +5 ) haracteristic ymbol Test condition () V=5V±0% () V=V±0% Min. Typ. Max. Min. Typ. Max. Unit lock cycle time t Y uty=50% lock pulse width t WK lock rise/ fall time t R / t F ns ata set-up time t ata hold time T H IPOFFB low pulse width t WL μs IPOFFB clear time t Output delay time t L ns M OUT propagation delay time t P L OUT propagation delay time t P L =5pF μs IPOFFB OUT propagation delay time t P ns /

18 rystalfontz Neotec emiconductor Ltd. L river () egment river Application Timing L 0.V 0.V t WK t 0.V 0.V t H L 0.V 0.V 0.V t WK t WK 0.V 0.V 0.V t R t F t Y t t H _I - _R 0.V 0.V IPOFFB t WL t L L ELB, ERB (Output ) ELB, ERB (Input ) V t PHL 0.V t PU 0.V 0.V M 0.V 0.V t P L 0.V t P IPOFFB - 0 (Latched data) 0.V 0.V t P /

19 rystalfontz Neotec emiconductor Ltd. L river () ommon river Application Timing t Y L 0.V 0.V t R t WKH t F 0.V 0.V t F t t H (*) I 0.V 0.V 0.V 0.V t L (*) O IPOFFB t WL t 0.V 0.V (*) When in single-type interface mode I=>L(HL=L), _R(HL=H) O=>_R(HL=L), _L(HL=H) When in dual-type interface mode I=>_L and _M(HL=L),_R and _M(HL=H) O=>_R(HL=L), _L(HL=H) M 0.V 0.V t P L 0.V t P IPOFFB 0.V 0.V t P - 0 (Latched data) 9/

20 rystalfontz Neotec emiconductor Ltd. L river POWER OWN FUNTION In the case of cascade connection of segment mode drivers, has a "power down function" In order to reduce the power consumption. HL Enable input Enable output urrent driver status The other drivers status L ERB ELB While ERB ="Low", current driver is enabled. isabled H ELB ERB While ELB ="Low", current driver is enabled. isabled * In the case of common driver application, power down function does not work. L L ELB(input) n- n n- n n- n n- n n- ERB/ELB (Output/Input) ERB/ELB (Output/Input) ERB/ELB (Output/Input) ELB(Output) NOTE:. HL = High (ELB = Input, ERB = Output). When in -bit parallel interface mode: n = 0 When in -bit serial interface mode: n = 0 0/

21 rystalfontz Neotec emiconductor Ltd. L river OPERATION TIMING IAGRAM () -bit parallel mode interface segment driver When HL= Low L _I _L _M _R ERB(Input) ELB(Onput) L - 0 When HL= High L _I _L _M _R ELB(Input) ERB(Onput) L - 0 /

22 rystalfontz Neotec emiconductor Ltd. L river () -bit serial mode interface segment driver When HL= Low L _I ERB(Input) ELB(Onput) L - 0 When HL= High L _I ELB(Input) ERB(Onput) L - 0 /

23 rystalfontz Neotec emiconductor Ltd. L river () ingle type interface mode common driver When HL= Low L _L _R OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA urrent river's OMMON area When HL= High L _R _L OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA urrent river's OMMON area /

24 rystalfontz Neotec emiconductor Ltd. L river () ual-type interface mode common driver When HL= Low L _L _M _R OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0 OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0 When HL= High L _L _M _R OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0 OM_ATA OM_ATA OM_ATA OM_ATA9 OM_ATA0 /

25 rystalfontz Neotec emiconductor Ltd. L river (5) ommon / egment driver timing (/00 duty) L Latched data (EG) OM M OM_ATA OM_ATA99 OM_ATA00 V0 V V V5 OM99 OM00 V0 V V V5 V0 V V V5 EG_ATA EG V0 V V V V V5 L 9 0 L - Latched data M Enable Out 5/

26 rystalfontz Neotec emiconductor Ltd. L river APPLIATION INFORMATION -bit serial interface mode (0 h. egment mode) a) Lower view (HL= L, AM= H) b) Upper view (HL= H, AM= H) 6/

27 rystalfontz Neotec emiconductor Ltd. L river -bit parallel interface mode (0 h. egment driver) a) Lower view (HL= L, AM = L) b) Upper view (HL= H, AM = L) /

28 rystalfontz Neotec emiconductor Ltd. L river ingle type interface mode (0 h. ommon driver) /

29 rystalfontz Neotec emiconductor Ltd. L river ual-type interface mode (0 h. + 0h. ommon driver) NOTE: Using this application mode (dual-type common mode), the duty ratio can be reduced to half. In case, /00 duty can be used to driver the 00 common L panel. 9/

30 rystalfontz Neotec emiconductor Ltd. L river APPLIATION IRUIT EXAMPLE 0/

31 rystalfontz Neotec emiconductor Ltd. L river PREAUTION Precautions when connecting or disconnecting the power supply This I has a high-voltage L driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the L drive power supply while the logic system power supply is floating. The details are as follows. When connecting the power supply, connect the L drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the L drive power. And when connecting the logic power supply, the logic condition of this I inside is insecure. Therefore connect the L drive power supply after resetting logic condition of this I inside on /IPOFF function. After that, cancel the /IPOFF function after the L drive power supply has become stable. Furthermore, when disconnecting the power, set the L drive output pins to level V5 on /IPOFF function. Then, disconnect the logic system power after disconnecting the L drive power. When connecting the power supply, follow the recommended sequence shown here. V /IPOFF VEE V V V V V VEE /

32