Novel Voltage Control of 18 Level Multilevel Inverter

Transcription

1 Noel Voltge Control of 18 Leel Multileel Inerter Sd Mekhilef Dept. of Eletril Engineering Uniersity of Mly Kul Lumpur 50603, Mlysi Mohmd N. Adul Kdir Dept. of Eletril Engineering Uniersity of Mly Kul Lumpur 50603, Mlysi Astrt This pper presents three-stge eighteen-leel inerter design with noel ontrol method. The inerter onsists of series onneted min high-oltge, medium-oltge nd low-oltge stges. The high oltge stge is mde of threephse, six-swith onentionl inerter. The medium nd low oltge stges re mde of three-leel inerters onstruted y H- ridge units. The proposed ontrol strtegy ssumes referene input oltge etor nd ims to operte the inerter in one stte per smpling time to produe the nerest etor to tht referene. The ontrol onept is sed on representing the referene oltge in 60 -sped two xis oordinte system. In this system, the inerter etors dimensions re integer multiples of the inerter s d oltge nd the expression of the inerter s etors in terms of its swithing riles is strightforwrd. Consequently, the swithing signls n e otined y simple fixed-point lultions. The pproh of the proposed ontrol strtegy hs een presented, the trnsformed inerter etors nd their reltion to the swithing riles he een defined, nd the implementtion proess hs een desried. The test results erify the effetieness of the proposed strtegy in terms of omputtionl effiieny s well s the pility of the inerter to produe ery low distorted oltge with low swithing losses. Keywords Conerters; multileel inerters; DSP ontrol; pulse width modultion. M I. INTRODUCTION ULTILEVEL inerter, MLI, refers to the lss of inerters of output points whih he more thn two oltge leels with respet to the negtie terminl of the input supply [1]. The essentil irtue of MLIs oer the onentionl inerters re the pity to he n output oltge nd urrent leels higher thn those of the swithing deies rtings, hene MLIs he een lssified s high power inerters[2]. Inresing the numer of leels of the MLI proides more steps for pproximting the desired output weform nd redued hrmoni distortion nd d/dt stress. The min drwks of MLI re: its iruit omplexity, high ost due to pplition of more omponents nd MLI is more diffiult to ontrol. Despite tht, reent studies reommended MLI topologies for medium oltge pplitions [3]. A. Reiew of hyrid MLI topologies The si MLI iruits he equl or eqully diided input d oltges nd its numer of leels is linerly relted to the numer of swithing deies [4]. The mximum numer of leels tht n e hieed with si MLI topologies is limited due to ost, size nd reliility onsidertions. On the other hnd, inresing the numer of leels enhnes the MLI merits. The pproh of symmetril MLI sed on supplying the inerter with unequl input oltges hs een found to he the pility of produing higher numer of leels for the sme numer of omponents ompred to the si MLI [5]. With symmetril MLI, the highest oltge stge opertes t lowest frequeny therefore swith utiliztion n e improed y seleting the swith hrterized y low onduting losses for high oltge stge, nd tht of fst swithing speed for the high frequeny stge [6]. The MLI design n e further optimized y hyridiztion; tht is to rete MLI y sding smller dissimilr inerter iruits [4]. Construting the inerter with sded stges of different topologies leds to onsiderle redution in the numer of d soures required. This hs een done in rious wys suh s onneting H-ridge three leel stge(s) in series with neutrl point lmped three-leel stge [7, 8] or to sixswith two-leel stge [9]. A. Reiew of hyrid MLI ontrol Mny studies he reported the ontrol of the MLI. Both high nd low frequeny swithing pprohes he een onsidered. Multirrier PWM strtegy hs een reported [10]. The spe etor modultion ontrol hs een introdued nd implemented [11-13]. And the rrier sed spe etor modultion hs een deeloped for MLIs with ny numer of leels [14]. The three pprohes re exmples of high swithing frequeny strtegies. Fundmentl frequeny swithing with seleted hrmonis elimintion hs een implemented exploiting the high numer of leels proided y symmetril MLI to redue the swithing losses [15]. This method howeer requires pre-lulted swithing ngles lookup tle. In [16] fundmentl frequeny SVM hs een pplied. The method is shown to e resonle due to high numer of leels proided y the 4-stge symmetril inerter. C. Csded H-ridge MLI One of the si MLI topologies is the sded H-ridge ells. This topology hs the dntge of modulr struture where the inerter onsists of smll identil ells. The min /13/$ IEEE

2 drwk of this topology is the requirement for high numer of isolted d soures. The k-ell per rm inerter hs (2k+1) leels nd requires 3k isolted d soures. The numer of leels n e gretly inresed when symmetril souring is dopted [16]. In symmetri sded inerter, indiidul ells d oltges differ using different oltge steps nd therefore higher numer of leels for the sme iruit topology. It hs een reported y mny reserhers tht the mximum numer of uniform steps is hieed when the d oltges of the rm ells form rtio 3- geometri sequene. Study of the pproprite oltge rtio shows tht the modultion ondition required to oid high frequeny opertion t high oltge stge is stisfied if ny two djent oltge leels n e hieed y swithing the lowest oltge ells only [17-19]. This ondition is not stisfied with rtio-3 relted d soures, nd hene this seletion is not pproprite for PWM ontrol. Yet this rtio hs een followed y some designs whih do not pply PWM ontrol [15, 16]. D.Sope of this pper This pper ims to oerome the two min drwks of the sded H-ridge MLI whih re the requirement of lrge numer of isolted d supplies nd high swithing frequeny of the high oltge stge. The presented iruit ses the ost of the d supplies y reduing the numer of the high oltge stge soures to one. Aoiding high swithing frequeny t the high oltge stge is insured y the suggested ontrol strtegy. The ontriution of this pper is to determine the swithing stte sed on oerll inerter stte rther thn the rm oltge leel, proiding the dntge of the pility to oid high swithing frequeny een with high frequeny PWM ontrol of the low oltge stge. A hyrid MLI with sded stges of two nd three leels inerters is presented in this pper. The inerter iruit nd its swithing riles definition re gien in the following setion. The ontrol onept is introdued in setion III. DSP implementtion is desried in setion IV. In setion V, seleted test results of the deeloped inerter nd the ontrol strtegy re presented. II. INVERTER TOPOLOGY AND SWITCHING STATES A. Inerter Topology The inerter iruit shown Fig. 1 onsists of the min high oltge six-swith inerter with eh output line in series to two sded single-phse full ridge inerters. The min nd H-ridge ells re fed y isolted d soures of 9Vs, 3Vs, nd Vs s shown in Fig.1. In this design the high oltge stge hs only one d soure opertes with redued urrent ripple ompred to the three d soures of the sded H-ridge design [16]. Therefore, onsiderle redution in the d soure ost nd losses n e hieed with this rrngement. In order to determine the numer of leels of the inerter iruit shown in Fig.1, onsider the oltge of ny output point (A, B or C) with respet to the negtie terminl of the 9Vs d soure. Output points oltges rnge etween mximum of (9+3+1)Vs =13Vs, nd minimum of (0 3)Vs = 4Vs, with uniform step of Vs. Therefore the sded inerter of Fig.1 forms n 18-leel inerter. B.Voltge Vetors nd Inerter Sttes The swithing riles of the inerter re denoted y {(x ),(y ),(z )} where x is inry digit while y nd z re trinry digits. The sttes of the high, medium nd low oltge stges re determined y x, y nd z respetiely. The output oltge etor n e represents in terms of the swithing stte s shown in the following derition. Line oltges re represented in terms of the swithing riles in (1) x x y y z z + + = 9 Vs x x 3Vs y y Vs z z (1) x x y y z z Phse oltges of the Y-onneted lod n e represented s follows: n n n 1 = 3 2 Vs = 2 3 9x 9x 2 9x + 3y + 3y + 3y The oltge etor is hieed y Prk s trnsformtion gien in (3) n D = 3 3 n Q n (3) Sustituting (2) into (3) gies: Fig. 1. Eighteen leel inerter topology. (2)

3 D Q = V s x + 3y 3 9x + 3y 2 9x + 3y Using (4), the oltge etor of ny inerter stte n e hieed. Alterntiely, the oltge etor digrm of the three-stge inerter is drwn y two superposition steps. First, the etor digrm of the 3-leel medium oltge stge inerter (omposed of 19 etors) is drwn t the end of eh of the seen etors of the high oltge stge. Then, the etor digrm orresponding to low oltge stge hs een superimposed t the ends of resultnt etors s shown in Fig. 2. The modultion ondition hs not een met y this design, i.e. when ontrolling the inerter y SPWM strtegy, the medium nd high oltge stges will e sujeted to high swithing frequeny. Howeer, the resolution of the 18-leel inerter proides suffiiently low distorted oltge without inluding high swithing frequeny PWM [17]. C. Voltge Vetors in G-H Axis System The 60 -sped g-h oordinte system shown in Fig.3 will e used to represent the oltge etor in the proposed ontrol lgorithm. This system is tht it llows simpler nd fster lultions s it is tightly relted to the inerter sttes oltge etors. This lso pplies lso to the three-leel medium nd low oltge stge inerters s shown in Fig.4.The integer oordintes of the inerter etors llow the inerter ontrol y simple fixed point lultions[20-22]. (4) of the 19 medium oltge etors. For illustrtion, one of the middle stte domins hexgons is shown in Fig. 6. With x =100 nd y =200, the low oltge stge seletion will oer the smll hexgon mrked t the rightmost side of Fig. 6, we shll refer to it s the domin of stte [100,200]. Fig. 2. Voltge etors of the 18-leel inerter s the sum of the three sded inerters etors. D. High nd Medium Sttes Domins Eh of the 18-leel inerter etors n e represented y the ddition of three etors, one hs norm of 9Vs or 0 determined y x, the seond hs norm of 6, 3 3, 3 or 0Vs determined y y, nd the third hs norm of 2, 3, 1 or 0Vs determined y z. With the exeption of the outmost etors, most of the 18-leel inerter etors n e represented y more thn one omintion of the three stges oltge etors. For exmple etor V1 shown in Fig. 2 is represented s V h 1+ V m 1+V l 1 nd sv h 1 + V m 1 +V l 1, where V h, V m nd V l re the oltge etors orresponding to high, medium nd low oltge stges respetiely. It is highly desirle for the swithing frequeny of the high oltge stge to e redued. The ontrol lgorithm explined in the next setion ims to hold the high oltge etor s long s the referene etor n e represented y dding other medium nd low etors to this high oltge etor. We shll refer to the hexgonl re mrked y the etors rehle through gien high stte etor y its domin. The seen domins of the high oltge stge etors re shown in Fig. 5. Diiding the spe etors re into domins is extended to the middle stge etors. Nineteen hexgons, eh represents the re oered y low oltge stge etor digrm, n e drwn within eh of the seen high stte domins t the tips Fig. 3. G-H xis oordinte system used to represent the oltge etor As shown in Fig. 6, within the grnd hexgon some of the regions re oered y extly one high stte domin without oerlp. If the referene etor is loted in suh re, the ontroller should selet the orresponding high stte. Other res re oered y two- or three- high stte domins; in this se there is more thn one option in the seletion of x. We he exploited this to minimize the swithing tions t the higher oltge stges. The medium stte domins lso oerlp nd this will e utilized in similr wy.

4 Fig. 4. The oltge etors of three leel inerter nd their G-H dimensions; Vm is the d supply oltge Fig. 6. Flow hrt of the 18 leel inerter ontrol lgorithm with of stte per smpling interl Fig. 5. The shded seen hexgons represent the domins of the high oltge stge etors. The rightmost smll hexgon represents the domin of the medium stte [100,200]. III. CONTROL STRATEGY A. The Control Algorithm The ontroller genertes the swithing signls {x, y, z } in order to produe the est pproximtion of the input referene oltge etor during the following swithing interl. The lulted stte ensures the minimum swithing tions nd the inerter opertes with one swithing stte during the entire smpling interl. The next swithing stte is determined s illustrted in ontrol lgorithm flow digrm shown in Fig. 6. This proess is rried out in three onseutie stges; the high, medium nd low stges [23-25]. Eh stge onsiders its preious output in the lultion of its new stte. The preious output is proided y the memory loks (Z ). B. High Voltge Stte Determintion Following the nottion gien in Fig. 3, the referene etor g- h omponents re lulted s follows: sin θ ref g ref = V ref os θ ref 3 (5) 2 sin θ ref h ref = V ref 3 The lultion of x egins y the determintion if the referene etor is loted in the domin of the urrent high oltge stte. If so, x holds its lue during the next swithing interl. Otherwise the nerest high oltge stte is determined y ompring the referene to the seen high stte domins. If the referene is loted in more thn one domin, the ontroller selets x whih is nerer to the initil lue. C. Medium Voltge Stte Determintion The middle referene is lulted y sutrting the oltge etor orresponding to the next x from the input referene oltge etor. The medium stge holds its stte if the medium referene oltge is loted within its domin [26-32]. If the referene etor is not within the urrent stte domin, the medium swithing stte will e hnged to the nerest stte. Where, eh of the medium stte etors is ompred to the medium referene to determine if the medium referene is loted within its domin. If the referene is loted within more thn one domin, the sttes ssoited with these domins re ompred to the initil medium stte,

5 nd the one rehle with minimum trnsition is tken s the next stte. D. Low Voltge Stte Determintion The referene oltge for the low oltge stge is determined y sutrting the etor orresponding to the lulted y from the medium stge referene etor s shown in Fig. 6. The three leel oltge etor digrm shown in Fig.5 suggest the following reltionship etween the swithing riles nd the orresponding etor g-h omponents: z g 1 0 = Vs z (6) h 0 1 z whih gies z z z g = 1 3Vs h 2 ref, low ref, low In (7) the three swithing riles z re determined from the two equtions expressed in (6) in the mtrix form, the third eqution ssumes the three riles dd up zero. The solution gien in (7) is treted s liner spe of solution from whih one or two speifi solutions n e otined y dding onstnt to z tht sets the minimum z to 0 or the mximum z to 2. When two solutions otined the one nerer to the initil stte is seleted. (7) A 16-it port hs een lloted for the output. Eh rm of the two nd three leel su-inerters is drien y one it. Externl logi iruit hs een used to deode the swithing signls nd insert lnking time. V. EXPERIMENTAL RESULTS A prototype of the proposed inerter hs een onstruted. The low nd medium oltge stges he een supplied y led id 12V -5.5Ah tteries. Three series onneted units re used for the medium oltge stge to supply 36V. The high oltge stge hs een fed y the lortory DC power supply. For high nd medium oltge stges, IGBTs re used, while MOSFETs he een used for the low oltge stge. A 1kW motor hs een supplied y the inerter to t s lod. Fig. 7 shows the mesured phse oltge weforms nd their orresponding frequeny spetrums for different lues of the referene mplitude. The inerter oltge qulity is ffeted t ery low referene mplitude due to the redution in the numer of steps. Howeer with referene input of 60% or higher, the output oltge THD is less thn 3.16%. Compred to preious studies whih pplied the high frequeny SVM tehnique, the hrmoni distortion hs een onsiderly redued. For exmple, in [12] the the 5- nd 7- leel SVM-ontrolled inerters he THD higher thn 10% when operted with 0.9 modultion index. This improement in the oltge qulity is minly due to the high numer of leels. IV. DSP IMPLEMENTATION The ontrol lgorithm hs een implemented using DSP ontroller ord ezdsp F2812. The 150MHz, fixed point, low ost CPU, exeuted the lgorithm with smpling frequeny exeeding 45 khz nd using the on-hip memory only, this reflets the omputtionl effiieny of the proposed lgorithm. A 16-it input port hs een lloted for the referene input. The 8 MSBs he een ssigned s the referene oltge mplitude where the step d oltge (Vs) is ssumed to e equilent to (10) h. With this sling the mximum referene mplitude (FF) h orresponds to referene mplitude pproximtely equls to 15.94Vs. This limit is justified y the ft tht the mximum norm of referene etor loted within the hexgon formed y the 18-leel inerter etors is 14.72Vs or ording to our sling (EB) h. This lue is tken s se or 100% of the normlized referene. The referene etor ngle is represented y the 8-LSBs of the input port. The resolution of this representtion is /it ompred to 2.83 ; the minimum ngle etween ny two djent oltge etors of the 18-leel inerter, there is no loss of resolution y this representtion. () Referene oltge mplitude =100% () Referene oltge mplitude =60% () Referene oltge mplitude =20% Fig.7. Lod phse oltge mesured with different lues of referene mplitude nd the orresponding frequeny spetrum. The referene oltge frequeny is Hz

6 VI. CONCLUSION A three stge, 18-leel inerter nd its innoted ontrol strtegy he een presented. The inerter onsists of three stges of two nd three-leel inerters. The topology ses the ost of the d soure. Asymmetril d supplies rtio mximizes the numer of leels. The suggested strtegy exploits the inerter s high resolution to pproximte ny referene etor y one inerter etors. With the integer lultions llowed y introdued etor trnsformtion, the ontrol lgorithm hs een tested using low memory fixed point low ost proessor. This proessor runs the ontrol lgorithm with speed whih is stisftory for most pplitions. The experimentl results show tht the output oltge weform hs ery smll hrmoni distortion for wide rnge of referene mgnitude. The urrent mesurements show tht the min d supply urrent hs low ripple while the medium nd low stges d urrents re highly retie. The high oltge stge inerter opertes in the squre we mode. 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