CORAL PA ADA. MB86296-ADA01 Rev CORAL PA Adapter Board. September Fujitsu Microelectronics Europe

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1 ORL P M-0 Rev..0 ORL P dapter oard Revision.0 00 Fujitsu Microelectronics Europe September 00.0 Page

2 M-0 Evaluation oard Manual Revision ontrol Revision Number ate escription of changes.0 0/0/0 Official release Page of Revision.0 00 Fujitsu Microelectronics Europe

3 M-0 Evaluation oard Manual ONTENTS Overview... Hardware Installation... System omponents... External ppearance... Jumper Settings and LEs... Expansion onnectors...0 ual isplay Mode of FPG... Worldwide Headquarters and isclaimer... Revision.0 Page of 00 Fujitsu Microelectronics Europe

4 M-0 Evaluation oard Manual Overview This evaluation board is designed to evaluate and test the dual display functions of the Fujitsu M oral P graphic controller. You need the M-E0 evaluation board in your system to test the functions with the M-0 board. The evaluation board can be used in any V or.v PI system (PI compliant V.). Hardware Installation In order to install the M-0 evaluation board in your system, follow these instructions:. Make sure all jumpers are set to their default position (refer to Jumper Settings ).. Power down your target system (P or other PI-environment) and insert the card. Note that either.v or V systems can be used. Level-converters allow to operate the evaluation board in a V environment, but the oral P graphic controller has a.v PI-interface only.. Make sure that an M-E0 evaluation board is also in your system and the connection between both boards is correct. You need an : connection between M-E0_J00 and M-0_J0 and between M-E0_J0 and M-0_J (see the picture on the first page).. Restart your target system. onnect two VG-monitors to the RG-output connectors J00 and J0 on the M- 0 board to see the examples provided. Page of Revision.0 00 Fujitsu Microelectronics Europe

5 M-0 Evaluation oard Manual System omponents RG IN RG RG OUT RG OUT NLOG SIGNL SWITHING Triple Video V Triple Video V LVS Transmitter S0 RG[0:] RG[0:] LVS Transmitter S0 FPG EPM RG[0:] Sync Signals oral Interface oral-p dapter Evaluation ard block diagram Main components of the M-0 evaluation board are : LTER FPG (EPMQ0-) LVS Transmitters (S0MT) s for nalog RG Output (V) Switching Logic for multiplexed Outputs VG Output connectors RG analog input connector Expansion onnector from oral P (x 0pin JP) Expansion onnector from FPG (x0pin JP) onfiguration Jumper Revision.0 Page of 00 Fujitsu Microelectronics Europe

6 M-0 Evaluation oard Manual External ppearance RG Output JP0, JP0, JP Expansion connector J J0 Expansion connector J J RG Input MOE Pins JTG Interface RG Output RG Output RG Output J00, JP0, JP0.V net JP0 LVS Transmitters FPG Expansion onnector # and # Position of main external components and jumpers Page of Revision.0 00 Fujitsu Microelectronics Europe

7 M-0 Evaluation oard Manual Jumper Settings This table gives an overview of the Jumpers on the oral P adapter board. e sure to set all jumpers according to the function you want to use. efore inserting the oral P adapter board for the first time, make sure all jumpers are correctly set to their default positions. The default jumper position is for the multiplex mode (Two screens are multiplexed and output at digital output). The jumpers in this table are logically grouped according to the sheet in the evaluation board schematics. Jumper Function Set escription Open isable (default) J00 Graphic/Video switch losed Enable - # nalog Outputs (default) JP0 RG Output Switch SEL - oral nalog Outputs - oral nalog Output Override JP00 Green Output # - Output Switch (use JP0) (default) - oral nalog Output Override JP0 Red Output # - Output Switch (use JP0) (default) - oral nalog Output Override JP0 lue Output # - Output Switch (use JP0) (default) - irect oral HSYN # line JP0 HYSN # line driver - HSYN # line driver (default) - irect oral VSYN # line JP0 VSYN # line driver - VSYN # line driver (default) J0 isable analogue switch for video output Open closed evice enabled evice disabled Open isable (default) J0 Graphic/Video switch losed Enable - # nalog Outputs (default) JP RG Output Switch SEL - oral nalog Outputs - oral nalog Input Override JP0 Green Output # - Output Switch (use JP) (default) Revision.0 Page of 00 Fujitsu Microelectronics Europe

8 M-0 Evaluation oard Manual - oral nalog Input Override JP0 Red Output # - Output Switch (use JP) (default) - oral nalog Input Override JP0 lue Output # - Output Switch (use JP) (default) - irect oral HSYN # line JP0 HYSN # line driver - HSYN # line driver (default) - irect oral VSYN # line JP0 VSYN # line driver - VSYN # line driver (default) J0 isable analogue switch for video output Open closed evice enabled evice disabled losed Enable Power save mode J0 # POWER SVE Open isable Power save mode (default) - SYN # enable JP # SYN SELET - SYN # disable (default) losed ctivate blanking J # LNK Open isable blanking (default) losed Enable Power save mode J # POWER SVE Open isable Power save mode (default) - SYN # enable JP0 # SYN SELET - SYN # disable (default) losed ctivate blanking J # LNK Open isable blanking (default) J (-) J (-) Interrupt Select (all are open by default) oard Power Indicator (all are open by default) x INT# - INT # - INT # - INT # - PRSNT# -0 PRSNT# - V net disable JP0 dapter.v net enable -.V supply pins enabled (default) Page of Revision.0 00 Fujitsu Microelectronics Europe

9 M-0 Evaluation oard Manual JP00 FPG I² interface (all are open by default) - I² - SL enable - I² - S enable J00 J0 FPG JTG Interface Output Mode Switch (all are closed by default) JTG_TI JTG_TMS JTG_TK JTG_TO - MOE_0 losed: normal operation V: FPG Reset - MOE_ losed: multiplex mode V: parallel mode - MOE_ losed: enable LVS V: disable LVS - MOE_ losed: enable LVS V: disable LVS -0 MOE_ Reserved - VSYN # enable (default) JP00 VSYN # SEL - VSYN oral enable - HSYN # enable (default) J0 HSYN # SEL - HSYN oral enable - HSYN # enable (default) JP0 HSYN # SEL - Input HSYN enable - VSYN # enable (default) JP0 VSYN # SEL - Input VSYN enable Table Jumper on the board There are further some LE s on the board what should show activity. LE connected function LE0 V voltage net If on, V voltage is available LE.V voltage net If on,.v voltage is available LE V voltage net If on, V voltage is available LE -V voltage net If on, -V voltage is available Table LEs on the board Revision.0 Page of 00 Fujitsu Microelectronics Europe

10 M-0 Evaluation oard Manual Expansion onnectors There are two expansion connectors available on the M-0 adapter-board, which must be attached, in order to make oral P output signals available for the adapter-board functionality. The physical locations in combination with the mirror-expansion connectors J and J allow a daughter-board design which can be mounted ontop of the adapter-board. J0/J dapter-board expansion and mirror-expansion connector J0 and J Page 0 of Revision.0 00 Fujitsu Microelectronics Europe

11 M-0 Evaluation oard Manual J/J dapter-board expansion and mirror-expansion connector J and J Revision.0 Page of 00 Fujitsu Microelectronics Europe

12 M-0 Evaluation oard Manual There are two FPG output expansion connectors available on the M-0 adapterboard which can be used to adapt two displays. ll signals are available to support two different digital displays. FPG expansion connectors for displays Page of Revision.0 00 Fujitsu Microelectronics Europe

13 M-0 Evaluation oard Manual ual isplay Mode of FPG The oral P device can drive two connected displays individually. The displays should have the same resolution and can be attached to the oral P adapter-board either to the digital connectors J0 and J0 or to the VG connectors J00 and J0. The adapter-board supports three different output modes from oral P. In Single Mode, the board outputs the same contents on RG analog (J00) and RG digital (J0) connector. In ual Mode, two different display contents are connected on RG analog and RG digital output. In Multiplexed Mode, two different digital display contents are output. oth output streams are available on the digital and also on the VG connectors. With this method, all kinds of dual display applications like rearseat entertainment systems or dual monitor control units can be realized. In dual display mode, each layer can be programmed to appear in isplay, or both. With this method it is possible to duplicate contents (like a video picture), but also to have two individually composed pictures on the two displays. Mode Function Setting escription 0 Operation Mode 0: Normal Operation : Reset FPG Mode 0: Multiplex Mode : Parallel Mode Normal Operation: FPG works dependent on Mode. Reset: FPG doesn't output signals if Mode 0 in Reset. Multiplex Mode: e-multiplex incoming signals Parallel Mode: ypass de-multiplex logic LVS Transmitter # 0: LVS enable : LVS disable LVS Transmitter # 0: LVS enable : LVS disable Enable/isable LVS transmitter # to connect LVS interface display Enable/isable LVS transmitter # to connect LVS interface display Reserved Reserved Reserved Revision.0 Page of 00 Fujitsu Microelectronics Europe

14 RG ONNETORS RG ONNETORS.SH VOR VOG VO VOVS VOHS VOR VOG VO VOVS VOHS VIR VIG VI VOR VOG VO VOVS VOHS VOR VOG VO VOVS VOHS VIR VIG VI RG OUT SWITH RG OUT SWITH.SH VOR VOG VO VOVS VOHS VOR VOG VO VOVS VOHS VIR VIG VI VR VG V VR VG V GV ORLVOR ORLVOG ORLVO ORLVOR ORLVOG ORLVO RG OUT S RG OUT S.SH VR VG V VR VG V EXP ONN EXP ONN.SH ORLVOR ORLVOG ORLVO GPON VOGRVSW GPON0 RGIR[0..] RGI[0..] RGIG[0..] RGIVS RGILK VOHSYN RGIHS VOVSYN EXP ONN EXP ONN.SH ORLVOR ORLVOG ORLVO GPON0 GPON RGIHS RGIVS VOOTLK RO[0..] GO[0..] O[0..] K SYN RO[0..] GO[0..] O[0..] K SYN VOOTLK VOGRVSW VOVSYN VOHSYN RGIR[0..] RGIG[0..] RGI[0..] RGILK S SL RO[0..] GO[0..] O[0..] K SYN RO[0..] GO[0..] O[0..] K SYN EXP ONN EXP ONN.SH RO[0..] O[0..] GO[0..] VOP VOSYN VOLKI EPM EPM.SH RO[0..] GO[0..] O[0..] K SYN RO[0..] GO[0..] O[0..] K SYN GV RO[0..] O[0..] GO[0..] VOP VOSYN S SL VOOTLK VOGRVSW EXP ONN EXP ONN.SH VOSYN VOP VOLKI SL S RO[0..] GO[0..] O[0..] HSYN VSYN K E RES RO[0..] GO[0..] O[0..] HSYN VSYN K E RES RO[0..] GO[0..] O[0..] HSYN VSYN K E RO[0..] GO[0..] O[0..] HSYN VSYN K E VOVSYN VOHSYN RO[0..] GO[0..] O[0..] RO[0..] GO[0..] O[0..] HSYN VSYN K E RES RO[0..] GO[0..] O[0..] HSYN VSYN K E RES RO[0..] GO[0..] O[0..] HSYN VSYN K E RO[0..] GO[0..] O[0..] HSYN VSYN K E PNEL LINK PNEL LINK.SH RO[0..] GO[0..] O[0..] HSYN VSYN K E RES RO[0..] GO[0..] O[0..] HSYN VSYN K E RES FPG OUT onnector FPG OUT onnector.sch RO[0..] GO[0..] O[0..] HSYN VSYN K E RO[0..] GO[0..] O[0..] HSYN VSYN K E VOVSYN VOHSYN RO[0..] GO[0..] O[0..] SYN SYN VOVSYN VOHSYN VOVSYN VOHSYN VOVSYN VOHSYN VOVSYN VOHSYN VOVSYN VOHSYN VIHS VIVS VIR VIG VI VIHS VIVS VIR VIG VI PI V OR V IT onnector PI V OR V IT onnector.sh oral P dapter oard Number: Project Top Sheet Revision: Time: 0: oral P ual isplay oard Title Size: ate: File: Sheet of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

15 V 00 R00 0K VOR VOG VO VOHS VOVS JUMPER WY SIL VOHS VOVS JP0 JUMPER WY SIL U0 MH0RMTR JP0 -V U0 MH0RMTR VOVSYN U/ VOHSYN U00 LL0 VIN VIN VIN VIN VOUT N N VOR VOG VO 0 U VO 0 00N JP00 VO JP0 M_SEL JP0 MG_SEL - VO MR_SEL 0 00N MROUT MGOUT MOUT VO 0 U U0 OUT OUT OUT VEE 0 VO IN IN IN IN IN IN / SEL V POWN EL_ VO VR ORLVOR VG ORLVOG V ORLVO SEL R0 00 0K J0 RGSW_PN JP0 SEL VO V J00 SEL GV VR ORLVOR VG ORLVOG V ORLVO VOHSYN VOVSYN VOR VOG VO - VOR VOG VO JP0 JP0 JP0 M_SEL MG_SEL MR_SEL MROUT MGOUT MOUT U0 OUT OUT OUT VEE IN IN IN IN IN IN VR VIR VG VIG V VI 00 R0 0K J0 SEL GV VR VIR VG VIG V VI VOHS VOVS JUMPER WY SIL VOHS VOVS JP0 JUMPER WY SIL U0 MH0RMTR JP0 U0 0 MH0RMTR VOVSYN VOHSYN 0 U VO 0 00N VO VO 0 00N VO / SEL V 0 U 0 VO POWN EL_ VO SEL R0 00 0K J0 RGSW_PN JP SEL VO VOHSYN VOVSYN 0 00N V U0E MH0RMTR oral P dapter oard Number: RG Out Switch Revision: Time: 0: oral P ual isplay oard Title Size: ate: File: Sheet of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

16 Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich oral P dapter oard RG Out S : oral P ual isplay oard Title Size: Number: ate: File: Revision: Sheet of Time: 00 R R 00 R 0R RO[0..] GO[0..] O[0..] RO[0..] GO[0..] O[0..] VO V K SYN VR VG V + 0U/ V 00N VO 00N VO 00N VO 00N TP.V VOLK 0N VO VR VG V 00 R 0K V J LNK VO SYN K 00 R R 00 R R 00 R R VO VO VO 00 R 0K J PSVE V VRF 0N VO VO JP0 JUMPER WY SIL VO G0 G G G G G G G 0 LNK SYN V 0 0 V 0 LK /IO IO V /IOG /IOR IOG IOR R0 R R R R R R R OMP VREF RSET POW SVE 0 U VKST0_ V VO 00 R R 00 R0 0R RO0 RO RO RO RO RO RO RO GO0 GO GO GO GO GO GO GO O0 O O O O O O O RO[0..] GO[0..] O[0..] RO[0..] GO[0..] O[0..] VO V K SYN VR VG V + 0 0U/ V VO V 00N VO 00N VO 00N VO 00N TP0.V VOLK 0N VO VR VG V 00 R 0K V J LNK VO SYN K 00 R R 00 R R 00 R R VO VO VO 00 R0 0K J0 PSVE V VRF F0 L0RN- + 0 U/ 0N VO VO JP ISEN VO G0 G G G G G G G 0 LNK SYN V 0 0 V 0 LK /IO IO V /IOG /IOR IOG IOR R0 R R R R R R R OMP VREF RSET POW SVE 0 U0 VKST0_ V VO RO0 RO RO RO RO RO RO RO GO0 GO GO GO GO GO GO GO O0 O O O O O O O

17 J00 RG OUTPUT R G HSYN VSYN N N N N N 0 ROUT GOUT OUT HSO VSO VHO VHO 00 0 LL 0 LL 0 LL 0 VHO LL 0 LL VHO 0 LL 0 LL 0 VHO LL 0 LL LL VHO 00 P L00 0N R0 00 R 0 P R0 00 R 0 P R0 00 R R 00 0R R 00 0R VOR VOG VO VOHS VOVS VOR VOG VO VOHS VOVS 00 R00 NF-0R 0 0P VO VO VO VO VO VO VO VO VO VHO VHO VHO VHO VHO J0 RG OUTPUT R G HSYN VSYN N N N N N 0 ROUT GOUT OUT HSO VSO 0 LL LL LL LL 0 LL LL LL LL LL LL 0 P R0 00 R 0 P R0 00 R 0 P R0 00 R R 00 0R R 00 0R VOR VOG VO VOHS VOVS VOR VOG VO VOHS VOVS 00 R0 NF-0R 0 0P VO VO VO VO VO VO VO VO VO J0 0 HRX F00 L0RN F0 L0RN F0 L0RN RI GI I HSI VSI VHI VHI VHI LL LL LL VHI LL VHI LL VHI L0 0N R0 00 R R0 00 R R 00 R R 00 0R R0 00 0R VIR VIG VI VIHS VIVS VIR VIG VI VIHS VIVS VI VI LL LL LL LL LL 00 R R 0 P 00 R R 0 P 00 R R 0 P 00 R0 NF-0R 0P VI VI VI VI VI VI VI VI VI VI VI oral P dapter oard Number: RG Out onnectors Revision: Time: 0: oral P ual isplay oard Title Size: ate: File: Sheet of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

18 V V -V 00 R0 0R 00 LE0 RE R 0R LE RE 00 R K LE RE 00 R K LE RE -V V 00N 00N J0 R / T 0 R / T R / T R / T R / T R / T R / T R / T / E0# R / T R / T R / T 0 R / T R / T R / T R / T R / T / E# R / T R / T R / T R / T R / T 0 R / T R / T R / T / E# R / T R / T R / T R / T R / T R / T R / T 0 R / T SONE SO# LOK# FRME# IRY# TRY# EVSEL# STOP# PERR# SER# PR V -V V V V V V V V V VIO VIO VIO VIO VIO.V.V.V.V.V.V.V.V.V.V.V.V 0 0 V -V JP0 U0 LMTX-V IN+ OU V SOURE SELET PIV V 00N + 0 0U/ J 0 HRX INT# INT# INT# INT# PRSNT# PRSNT# TI TMS TRST# TK TO ISEL / E# GNT# LK RST# REQ# M EN K# REQ# RESERVE RESERVE RESERVE RESERVE RESERVE RESRVE PI-V OR V-IT-EGE F0 F F H0 FIUIL FIUIL FIUIL HOLE.MM-NPTH F F F FIUIL FIUIL FIUIL oral P dapter oard Number: PI it onnectorrevision: Time: 0: oral P ual isplay oard Title Size: ate: File: Sheet of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

19 Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich oral P dapter oard FPG-EPM : oral P ual isplay oard Title Size: Number: ate: File: Revision: Sheet of Time: _IO _IO _IO _IO 0 _IO 0 _IO _IO _IO _IO _IO 0 _IO _IO _IO _IO _IO _IO 00 V_IO V_IO V_IO V_IO V_IO V_IO 0 V_IO 0 V_IO V_IO V_IO V_IO V_IO 0 V_INT V_INT V_INT V_INT _INT _INT _INT 0 _INT IN/OE/GLK IN/OE IN/nGLR IN/GLK / JTG_TI 0 0 E E E E E0 F F F F 0 F G G0 G0 G0 G0 H H H H H H 0 I I 0 I I I J J J J J / JTG_TMS J0 K K K K K 0 K L 0 L 0 L L L0 L M 0 M 0 M0 0 M0 0 M0 0 N0 N N N N N 00 O O O 0 O O O0 P P 0 P P P Q Q Q Q Q0 Q 0 R R R R R R S S S 0 S S0 S0 T0 T0 T T T T0 U U U U U U V V V V0 V W W W W W / JTG_TK 0 W X X X X X Y Y Y 0 Y Y Y00 Z0 Z0 Z0 Z Z EE EE EE EE FF FF0 0 FF0 / JTG_TO FF0 FF U00 EPM_0 V RO0 RO RO RO RO RO RO RO GO0 GO GO GO GO GO GO GO O0 O O O O O O O RO0 RO RO RO RO RO RO RO GO0 GO GO GO GO GO GO GO O0 O O O O O O O RO[0..] GO[0..] O[0..] RO[0..] GO[0..] O[0..] RES HSYN VSYN E K SYN RES HSYN VSYN E K SYN GV RO[0..] GO[0..] O[0..] VOHSYN VOVSYN VOSYN VOP VOGRVSW RO0 RO RO RO RO RO RO RO GO0 GO GO GO GO GO GO GO O0 O O O O O O O VOHSYN VOVSYN VOSYN VOP VOGRVSW RES HSYN VSYN E K SYN RES HSYN VSYN E K SYN GV RO[0..] GO[0..] O[0..] RO[0..] GO[0..] O[0..] RO[0..] GO[0..] O[0..] 0 J0 MOE_SW VOOTLK VOOTLK 0 J00 HRX JT_TI JT_TMS JT_TK JT_TO JP00 HX SL S SL S FSL FS

20 RO[0..] GO[0..] O[0..] RES HSYN VSYN E K V RO[0..] GO[0..] O[0..] RES HSYN VSYN E K 0 00N 00N 00N RO0 RO RO RO RO RO RO RO GO0 GO GO GO GO GO GO GO O0 O O O O O O O 00N V0 V V TXIN0_R0 TXIN_R TXIN_R TXIN_R TXIN_R TXIN_R TXIN_R TXIN_R TXIN_G0 TXIN_G TXIN_G TXIN_G TXIN_G TXIN_G TXIN0_G TXIN_G TXIN_0 TXIN_ TXIN_ TXIN0_ TXIN_ TXIN_ TXIN_ TXIN_ TXIN_RES TXIN_HSYN TXIN_VSYN TXIN_EN TXLKIN V_PLL _PLL _PLL VO TXOUT_0 - TXOUT_0 + TXOUT_ - TXOUT_ + TXOUT_ - TXOUT_ + TXOUT_ - TXOUT_ + TXLK - TXLK + PWRN R_F O O O U0 0 TXO_0 TXO_ TXO_ TXO_ TXO_ TXO_ TXO_ TXO_ TXO_ TXO_ TXO_0 TXO_ TXO_0 TXO_ TXO_ TXO_ TXO_ TXO_ O_ J0 0 HRX TXO_ TXO_0 TXO_ TXO_ TXO_ TXO_ S0MT F0 L0RN- O_ RO[0..] GO[0..] O[0..] RES HSYN VSYN E K V RO[0..] GO[0..] O[0..] RES HSYN VSYN E K 00N 00N 00N RO0 RO RO RO RO RO RO RO GO0 GO GO GO GO GO GO GO O0 O O O O O O O 00N V0 V V TXIN0_R0 TXIN_R TXIN_R TXIN_R TXIN_R TXIN_R TXIN_R TXIN_R TXIN_G0 TXIN_G TXIN_G TXIN_G TXIN_G TXIN_G TXIN0_G TXIN_G TXIN_0 TXIN_ TXIN_ TXIN0_ TXIN_ TXIN_ TXIN_ TXIN_ TXIN_RES TXIN_HSYN TXIN_VSYN TXIN_EN TXLKIN V_PLL _PLL _PLL VO TXOUT_0 - TXOUT_0 + TXOUT_ - TXOUT_ + TXOUT_ - TXOUT_ + TXOUT_ - TXOUT_ + TXLK - TXLK + PWRN R_F O O O U 0 S0MT TXO_0 TXO_ TXO_ TXO_ TXO_ TXO_ TXO_ TXO_ TXO_ TXO_ TXO_0 TXO_ TXO_0 TXO_ TXO_ TXO_ TXO_ TXO_ O_ J 0 HRX TXO_ TXO_0 TXO_ TXO_ TXO_ TXO_ oral P dapter oard Number: LVS Transmitter Revision: Time: 0: oral P ual isplay oard F L0RN- O_ Title Size: ate: File: Sheet of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

21 O[0..] GO[0..] RO[0..] K HSYN VSYN E SYN VOVSYN O[0..] GO[0..] RO[0..] K HSYN VSYN E SYN JP00 JUMPER WY SIL VOVSYN O[0..] GO[0..] RO[0..] K HSYN VSYN E SYN O[0..] GO[0..] RO[0..] K HSYN VSYN E SYN O0 O O O O O O O GO0 GO GO GO GO GO GO GO RO0 RO RO RO RO RO RO RO V V V J0 EXP HR X 0 O0 O O O O O O O GO0 GO GO GO GO GO GO GO RO0 RO RO RO RO RO RO RO V V V J0 EXP HR X 0 VOHSYN VOVSYN VOHSYN VOHSYN VOVSYN VOHSYN JP0 JUMPER WY SIL VOHSYN VOHSYN JP0 JUMPER WY SIL VOVSYN VOVSYN JP0 JUMPER WY SIL VIR VIG VI VIHS VIVS VIR VIG VI VIHS VIVS VIR VIG VI VIHS VIVS J00 0 HRX oral P dapter oard Number: FPG Out onnectorrevision: Time: 0: oral P ual isplay oard Title Size: ate: File: Sheet of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

22 RGIR[0..] VOOTLK RGIG[0..] RGI[0..] RGIHS RGIVS RGILK ORLVOG ORLVOR ORLVO VOVSYN VOHSYN GPON GPON0 VOGRVSW RGI[0..] RGIHS RGIVS RGILK VOOTLK RGIR[0..] RGIG[0..] ORLVOG ORLVOR ORLVO VOVSYN VOHSYN GPON GPON0 VOGRVSW RGIG0 RGIG RGIG RGIG RGIG RGIG RGIR0 RGIR RGIR RGIR RGIR RGIR RGI0 RGI RGI RGI RGI RGI V V -V J EXP HR X 0 oral P dapter oard Number: EXP onnector Revision: Time: 0: oral P ual isplay oard Title Size: ate: File: Sheet of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

23 RGIR[0..] VOOTLK RGIG[0..] RGI[0..] RGIHS RGIVS RGILK ORLVOG ORLVOR ORLVO VOVSYN VOHSYN GPON GPON0 VOGRVSW RGI[0..] RGIR[0..] RGIHS RGIVS RGILK VOOTLK RGIG[0..] ORLVOG ORLVOR ORLVO VOVSYN VOHSYN GPON GPON0 VOGRVSW RGIG0 RGIG RGIG RGIG RGIG RGIG RGIR0 RGIR RGIR RGIR RGIR RGIR RGI0 RGI RGI RGI RGI RGI V V -V J0 EXP HR X 0 oral P dapter oard Number: EXP onnector Revision: Time: 0: oral P ual isplay oard Title Size: ate: File: Sheet 0 of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

24 O[0..] GO[0..] RO[0..] VOLKI VOP VOSYN S SL O[0..] GO[0..] RO[0..] VOLKI VOP VOSYN S SL O0 O O O O O O O GO0 GO GO GO GO GO GO GO RO0 RO RO RO RO RO RO RO V V V J EXP HR X 0 oral P dapter oard Number: EXP onnector Revision: Time: 0: oral P ual isplay oard Title Size: ate: File: Sheet of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

25 O[0..] GO[0..] RO[0..] VOLKI VOP VOSYN S SL O[0..] GO[0..] RO[0..] VOLKI VOP VOSYN S SL O0 O O O O O O O GO0 GO GO GO GO GO GO GO RO0 RO RO RO RO RO RO RO V V V J EXP HR X 0 oral P dapter oard Number: EXP onnector Revision: Time: 0: oral P ual isplay oard Title Size: ate: File: Sheet of Fujitsu Microelectronics Europe GmbH m Siebenstein -0 0 reieich

26 M-0 Evaluation oard Manual Worldwide Headquarters and isclaimer Japan sia Tel: + Fax: + Fujitsu Limited Kamikodanaka -- Nakahara-ku Kawasaki-shi Kanagawa-ken - Japan Tel: + 00 Fax: + 00 Fujitsu Microelectronics sia PTE Limited #0-0, Lorong hauan New Tech Park Singapore US Europe Tel: Fax: + 0 Tel: Fax: + 0 Fujitsu Microelectronics Inc North First Street San Jose -0 US ustomer Response enter Mon-Fri am-pm (PST) Tel: Fax:+ 0 0 Fujitsu Microelectronics Europe GmbH m Siebenstein -0-0 reieich-uchschlag Germany The contents of this document are subject to change without notice. ustomers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. lso, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. No license is granted by implication or otherwise under any patent or patent rights of Fujitsu Microelectronics GmbH. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications and measurement equipment, personal or household devices, etc.). UTION: ustomers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. ny semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade ontrol Law of Japan, the prior authorisation by Japanese government should be required for export of those products from Japan. Page of Revision.0 00 Fujitsu Microelectronics Europe