THE continuous scaling of transistor dimensions over more

Transcription

1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL., NO. 7, JULY Under-the-Barrier Model: An Extension of the Top-of-the-Barrier Model to Efficiently and Accurately Simulate Ultrascaled Nanowire Transistors Áron Szabó and Mathieu Luisier Abstract In this paper, we present a computationally efficient full-band method to determine the current characteristics of circular, gate-all-around nanowire (NW) FETs in the sub-0-nm regime. The well-established top-of-the-barrier model is extended to consider intraband tunneling through the Wentzel Kramers Brillouin approximation. The required electrostatic potential is obtained using a parabolic approximation for its radial component, thus reducing Poisson equation to an -D problem and the computational burden by several orders of magnitude. After validating the model with 3-D, full-band, atomistic quantum transport simulations, the properties of Si, Ge, and InAs NW FETs are studied as function of their diameter and gate length. It is found that below 0-nm gate lengths Si <> NW transistors outperform Ge <>, independently from their diameter. On the other hand, InAs <> wires with diameters below 6 nm exhibit higher ON-currents than their Si counterparts. Index Terms Device simulation, intraband tunneling, nanowire transistor, top-of-the-barrier (ToB) model. I. INTRODUCTION THE continuous scaling of transistor dimensions over more than 40 years for the sake of performance improvement and increased packing densities has pushed conventional single-gate Si MOSFETs to their limits [], []. To minimize short-channel effects, such as poor gate control and high leakage current, nonplanar devices with a multigate configuration are developed and investigated. The recent introduction of FinFETs at the -nm technology node has successfully demonstrated the advantages of 3-D over planar devices [3]. To keep Moore s scaling law continuous as gate lengths shrink below 5 nm, device structures with excellent electrostatic properties will be needed. Hence, the FinFET cross section will have to decrease and their design will have to evolve toward gate-all-around nanowires (NWs). The development of such ultrascaled devices requires a deep understanding of the transport mechanisms that govern their behavior. Manuscript received January 8, 03; revised March 8, 03 and May 8, 03; accepted May 9, 03. Date of publication June 4, 03; date of current version June 7, 03. This work was supported by the Swiss National Science Foundation under Grant PP00P 3359 and a grant from the Swiss National Supercomputing Centre (CSCS) under Project ID s363. The review of this paper was arranged by Editor J. Knoch. The authors are with the Integrated Systems Laboratory, ETH Zürich, Zürich 9, Switzerland ( aron.szabo@iis.ee.ethz.ch; mluisier@iis.ee.ethz.ch). Digital Object Identifier 0.9/TED /$ IEEE Computational simulations based on proper physical models can accelerate this miniaturization process by helping in the selection of adequate materials and structural parameters and by supporting the experimental research [4] []. 3-D full-band quantum transport (QT) simulations currently represent the most advanced techniques to investigate NW field-effect transistors (NWFETs) with sub-0-nm cross sections. Indeed, such simulations were already performed, either using k p or tight-binding semiempirical approaches [] [5]. Because of the heavy computational burden associated with 3-D full-band methods, there is, however, an increasing demand for numerically more efficient, but still accurate simulation models. The semiclassical top-of-the-barrier (ToB) model [6] provides an alternative to 3-D simulations. It is used to rapidly analyze the performance of NWFETs [7], [8], but it suffers from a severe deficiency. Through reducing the device physics to a single point along the transport axis (top of the barrier), it only captures the thermionic component of the device current and fails to consider source-to-drain (intraband) tunneling. As the latter dominates in transistors with gate length shorter than 0 5 nm, the ToB model must be extended to become a useful design and/or analysis tool at this scale. The aim of this paper is therefore to: ) introduce an under-the-barrier (UB) model that captures short-channel effects in ultrascaled NWs, while keeping the computational efficiency of ToB; ) demonstrate its validity by comparing results with 3-D, atomistic, full-band simulations for selected device structures; 3) apply it to a comparative study of Si, Ge, and InAs NWFETs with varying gate lengths and diameters. This paper is organized as follows: in Section II, the UB simulation approach is introduced. It is then validated in Section III before simulation results are presented in Section IV. Finally, the paper is concluded in Section V. II. APPROACH The key idea of the UB model is to improve the ToB approach by considering intraband tunneling through the potential barrier. The Wentzel Kramers Brillouin (WKB) approximation [9] is widely used for that purpose because of its

2 354 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL., NO. 7, JULY 03 straightforward application [0] []. In the semiclassical and ballistic ToB picture, electrons with an energy E higher than E CB (x ToB ), the conduction band edge at the top of the barrier location (x ToB ), have a % transmission probability from source to drain, i.e., the thermionic transmission component T th (E > E CB (x ToB )) = [3]. If at energy E, n sub-bands are available, then T th (E) = n. To calculate the transmission probability below the conduction band edge and extend the ToB model, the WKB approximation is used as follows: T WKB (E) = ( ) xn,d (E) exp dxκ n (x) () n x n,s (E) where κ n (x) is the decay rate of an electron at position x, in sub-band n, and with energy E. It is extracted from the complex band structure of the considered devices. Initially, the decay rate κˆ n (ε) of sub-band n is calculated in the tight-binding formalism for all the electron energies ε [0], [4]. Then, it is shifted hence κˆ n (ε = 0) is aligned with the conduction band edge of sub-band n. Finally, κ n (x) is evaluated between the integration boundaries x n,s (E) and x n,d (E) as κ n (x) = κˆ n (E E CB,n (x)), wheree CB,n (x) is the mean position-dependent profile of sub-band n along the axis joining the source and drain contacts. The variables x n,s (E) and x n,d (E) determine the locations where E CB,n (x) = E on the source and drain sides of the potential barrier, respectively, as shown in Fig.. Combining the UB and ToB approaches, the total current I D that flows through a NWFET can be calculated. It contains a tunneling I D,WKB and a thermionic I D,th part, both consisting of forward (+) and backward ( ) propagating components I D = I D,WKB + I D,WKB + I D,th + I D,th = q h + q h ECB (x ToB ) E CB (0) E CB (x ToB ) de π T WKB(E) ( f S (E) f D (E)) de π T th(e) ( f S (E) f D (E)). () In (), f S (E) and f D (E) are the Fermi Dirac distribution of the electrons in the source and drain contacts, respectively. They are characterized by their Fermi levels E f,s and E f,d. The difficulty to solve () resides in the tunneling probability T WKB (E) in (). To determine it, an accurate knowledge of the electrostatic potential (x) of the device is required as the decay rate κ n (x) and the integration boundaries x n,s (E) and x n,d (E) strongly depend on it. Hence, the simulation of ultrashort NWFETs cannot be reduced to a single point, as in the ToB model. A 3-D simulation is, however, also excluded as the computational burden would explode and there would be no reason to use an approximated model (ToB + UB) instead of a full QT simulation. To resolve this issue, the NWFETs here are treated as -D quantities, assuming an average charge density n(x) is sufficient to capture their electrostatic properties. To calculate this -D electron charge density, the following considerations are made. ) On the ToB, all forward propagating states are filled according to the source Fermi level, whereas backward ToB E E CB,n b a E f,s L S 0 x n,s (E) x ToB x n,d (E) L L D E f,d Fig.. Schematic view of a cylindrical gate-all-around NW FET where a is the radius of the semiconductor channel, which is surrounded by a t ox = b a thick oxide layer. L s, L g,andl d are the source, gate, and drain lengths of the device structure. Illustration of the -D charge calculation. All states in sub-band n on the left and right of the ToB with an energy E < E CB,n (x ToB ) are in equilibrium with the Fermi level of the contact situated on the same side of the potential barrier as them. States with an energy E > E CB,n (x ToB ) are filled according to their direction of propagation [6]. Variables x n,s (E) and x n,d (E) are integration boundaries for the calculation of the WKB transmission in () at energy E. propagating states are filled according to the drain Fermi level. ) On the source (drain) side of the barrier, all forward (backward) propagating states are filled according to the source (drain) Fermi level. So are the backward (forward) propagating states with an energy lower than the top of the barrier, because of reflection against the potential barrier. Tunneling is neglected in this phase, considering its minor effect on the shape of the potential in the subthreshold region. Backward (forward) propagating states with an energy higher than the barrier are filled according to the drain (source) Fermi level. Through formulating the previous considerations into mathematical equations, the charge density can be written as follows: n(x) = n S (x) x xtob + n D (x) x xtob (3) with n S/D (x) = q n + q n + q ECB,n (x ToB ) n E CB,n (x) E CB,n (x ToB ) E CB,n (x ToB ) de g n (E E CB,n (x)) f S/D (E) de g n (E E CB,n (x)) f S/D (E) de g n (E E CB,n (x)) f D/S (E). (4) In (4), g n (E) is the nth sub-band s contribution to the density-of-states (DOS) of an infinite NW with the same cross

3 SZABÓ AND LUISIER: UNDER-THE-BARRIER MODEL: AN EXTENSION OF THE TOP-OF-THE-BARRIER MODEL 355 section as the device under consideration. For convenience, g n (0) corresponds to the DOS at the conduction band edge here. The DOS is extracted from the NW band structure and contains the contribution of both forward and backward propagating states. To determine the conduction band profile E CB,n (x), (3) has to be solved self-consistently with Poisson equation. For that purpose, E CB,n (x) is rewritten as E CB,n + q (x), E CB,n being the minimum of the nth sub-band of an infinite NW without any applied voltage, (x) is the average electrostatic potential along the transport direction x, and q the electron charge. To describe the behavior of (x) in the gate region (x S x x D ) of a circular gate-all-around NW transistor, the following equation is used [5]: d (x) dx + g bi (x) λ = n tot(x) ε 0 ε sc (5) where g is the gate potential ( g = qv gs ), bi is the builtin potential between the semiconductor and the gate electrode, ε 0 is the vacuum permittivity, and ε sc the relative permittivity of the channel material. n tot (x) = n(x) + ρ(x), with ρ(x) being the doping-induced background charge. The parameter λ = a ε sc ln a b + a ε ox /4ε ox refers to the natural length of the device [5], with a and b being the inner and outer radii of the oxide, as shown in Fig., and ε ox is the oxide permittivity. The derivation of (5) is based on a parabolic approximation for the potential inside the channel as follows: (r, x) = (x) + c (x)r (6) where c (x) is an arbitrary -D function and (x) corresponds to (r = 0, x). Poisson equation in cylindrical coordinates takes the following form: r r ( r (r, x) r At the channel center, (7) simplifies to d (x) dx ) + (r, x) x = n tot(r, x) ε 0 ε sc. (7) + 4c (x) = n tot(x) ε 0 ε sc. (8) Equation (5) is then obtained from (8) by expressing c (x) as a function of (x). This is achieved by matching the radial electric displacements at the oxide semiconductor interface and by treating the oxide layer as an ideal coaxial capacitor below the gate. The same method can be applied to the source and drain regions, provided that the fringing electric fields are correctly handled. A technique based on the treatment of the oxide thickness as a spatially dependent variable obtained from geometric mapping was recently proposed for that purpose [6]. Here, another approach is chosen that better reproduces the results of 3-D full-band atomistic simulations. As the oxide is charge free, the right-hand side of (7) is zero in that region and by a variable separation, an analytic solution of the equation can be found as follows: (r, x) = (A e ±γ x ) (B J 0 (γ r) + C Y 0 (γ r)) (9) where J n and Y n are the Bessel functions of order n of the first and second kind, respectively, and γ is related to the characteristic screening length. Considering that the three constants (A, B, andc) are redundant, and that a constant field is also a solution, the electrostatic potential in the oxide region surrounding the source/drain extension can be written as follows: with (r, x) = S/D + X S/D (x) R S/D (r) (0) X S/D (x) = ( g bi S/D ) e ±γ S/D (x x S/D ) being the axial, and () R S/D (r) = c 3 J 0 (γ S/D r) + c 4 Y 0 (γ S/D r) () being the radial part of the solution, with the restriction that R S/D (r = b) =. (3) Equation (0) describes a function that tends toward the constant S = (0) ( D = (L)) at the end of the source (drain) extension. It also matches the potential g bi S/D at the gate edges. The coordinates x S = L S and x D = L S + are the positions of the source-channel and drain-channel interfaces. The explicit treatment of S and D allows us to consider the floating of the CB at the contacts because of the decrease of the electron reflection rate as the potential barrier lowers [6]. Matching (6) and (0) at the semiconductor oxide interface (r = a), setting the ratio of their derivatives in the radial direction to ε sc /ε ox there, and using the restriction in (3) give us enough conditions to eliminate c 3 and c 4, express c (x) as a function of (x), and derive a similar differential equation as (5) as follows: d (x) dx + 4 X S/D(x) à S/D (x) B S/D = n tot(x) ε 0 ε sc. (4) The constants à S/D and B S/D depend on the value of γ S/D. The latter is determined by assuming far from the gate, the potential has an exponentially decaying shape in the center of the NW too. Through imposing floating boundary conditions there, an analytic γ (x) relationship can be derived in that region, then γ can be determined by forcing this solution to match the solution of (4) at some arbitrary point far enough from the gate. For the derivation of these conditions and the values of à S/D and B S/D, see the Appendix. Equation (4) is only solved close to the gate in the source and drain regions. Below the gate, (5) has to be solved. Far from the gate, the analytical solution derived in the Appendix is used. The source ( S ) and drain ( D ) potentials are adjusted during the simulation to maintain charge neutrality at the contacts, just as the γ, à and B constants are recalculated at each steps on both sides of the device. Equations (5) (4) must be solved together with (3) until full self-consistency is reached with a continuous and smooth variation of the -D potential at the interfaces between the different regions.

4 356 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL., NO. 7, JULY 03 ID (A ) D model OMEN V DS =0.6 V V DS =0.05 V V DS =0.6 V V DS =0.05 V 0.5 x V GS (V ) Fig.. Transfer characteristics I D V G at V DS = 0.05 and 0.6 V of a 4-nm thick InAs NW FET with a 5-nm gate length. Dashed lines: -D ToB + UB model results. Solid lines: 3-D full-band atomistic results of OMEN. Fig. 3. Comparison of the electron density and electrostatic potential in a 4-nm thick InAs NW FET with a 5-nm gate length. Results obtained from OMEN (solid lines) and the ToB + UB model (dashed lines) are compared at V DS = 0.6 V. III. MODEL VALIDATION To demonstrate the validity of the coupled ToB and UB (ToB + UB) model, Si <>, Ge<>, andinas<> gate-all-around NW FETs with a 4-nm channel diameter and different gate lengths (5, 0, and 5 nm) are simulated. In the Si and Ge wires, a -nm SiO layer forms the gate insulator and a 0 0 cm 3 uniform donor doping concentration is assumed in the source and drain regions. In the InAs structure, the gate region is covered by a 3-nm- thick HfO layer with ε R = 0, whereas the source and drain extensions are surrounded by spacers characterized by a relative dielectric constant ε R = 5. This minimizes gate fringing effects and.5.5 offers a better electrostatic integrity. The doping concentration in the source and drain regions is further set to cm 3. The I V characteristics, charge density, and potential profile of the selected devices are compared with results obtained with a full-band, atomistic QT simulator called OMEN [4], [7]. OMEN is a 3-D self-consistent Schrödinger Poisson solver based on the semiempirical tight-binding method and the nonequilibrium Green s function formalism. Here, the sp 3 d 5 s tight-binding parameters from [8], [9] are employed, both for the QT simulations and for the complex band structures in (). Spin-orbit coupling is neglected and replaced by a factor in () and (4). Fig. shows the transfer characteristics I D V G of the InAs wire with a 5-nm gate length. The ToB + UB model reproduces the OMEN results with a high accuracy, both below and above threshold, with a low and high drain voltage. Furthermore, it helps to reduce the simulation time from hours on multiple CPUs down to minutes on a single computer. Fig. 3 shows that the charge density and the potential profile are also relatively well captured by the simple model for the same structure as in Fig.. At high gate voltages (lower potential barrier height), the charge distributions in the channel start to deviate from OMEN results. This is because the DOS of an infinite wire, as used in the simple model, has a sharp peak at E = E CB,n (x), whereas in reality this peak broadens in the presence of a varying electrostatic potential. This discrepancy is, however, small enough to make no notable difference in the potential profile. The floating of the CB edge in the contact regions is also predicted fairly precisely by the ToB + UB model. As shown in Fig. 4, the simple model results agree well with those of OMEN for devices with shorter gate lengths, where intraband tunneling plays a significant role. There are minor differences around the threshold voltage and in the ONstate region. The first ones are inherent to the ToB model: the thermionic component of the transmission is a steplike function that counts the number of bands participating to the electron transport. In reality, because of velocity and mode mismatch between the source, gate, and drain regions [30], the transmission function has a more complicated shape than predicted by the ToB model. The magnitude of the discrepancy caused by this effect strongly depends on the barrier height and on the channel material (Si/Ge versus InAs). Furthermore, it is partly compensated if the comparisons between the ToB + UB model and OMEN are performed at matched OFF current. The discrepancy in the ON-state current is caused by tunneling-induced charges. In the ballistic limit of transport, even at high V GS, the electrostatic potential still exhibits a thin barrier that is almost transparent for electrons [3]. Although the current through this barrier is considered by the ToB + UB model, the charge density situated inside of it is omitted, affecting the shape of the electrostatic potential and the resulting current. Different attempts to include this charge contribution are made, but none of them is really successful. The ToB + UB model quite accurately reproduces OMEN current results if the same electrostatic potential is used in both cases.

5 SZABÓ AND LUISIER: UNDER-THE-BARRIER MODEL: AN EXTENSION OF THE TOP-OF-THE-BARRIER MODEL 357 ID (A ) ID (A ) ID (A ) D model OMEN InAs <> =0 nm.5 =5 nm =5 nm 0.5 x V GS (V ) D model OMEN.5 Si<> =0 nm.5 =5 nm =5 nm 0.5 x V GS (V ) D model OMEN Ge<> =0 nm.5 =5 nm =5 nm 0.5 x V GS (V ) (c) Fig. 4. Transfer characteristics I D V G of 4-nm thick InAs <>, Si <>, and(c) Ge <> NW FETs with 5-, 0-, and 5-nm gate lengths at V DS = 0.6 V. Solid lines: OMEN. Dashed lines: -D ToB + UB model. Points for which convergence could not be reached in the QT simulations because of the limitations of the ballistic model are omitted. IV. RESULTS After validating the ToB + UB model with different devices, we investigate the crystal orientation, diameter, and gate length dependence of the intrinsic current characteristics of Si, Ge, and InAs NWs, taking advantage of the speedup the new method offers. The studied gate lengths vary from 5 to 5 nm. The gate work functions are always adjusted hence the device normalized OFF-current (diameter normalization) amounts to 0. μa/μm atv GS = 0VandV DS = 0.6 V. The ON-current is measured at V GS = V DS = 0.6 V. Initially, the performance of Si and Ge NWFETs with diameters varying between 3 and 5 nm is studied as a function of their crystal orientation. It is found that Si <> NW transistors outperform Ge <> below 0 nm gate lengths, independently from their diameter. For all the materials and crystal orientations, the ON-current and the subthreshold slope deteriorate as the NW gate length is reduced. Fig. 5 shows the subthreshold slope versus gate length for three differently oriented Si and Ge structures with diameters.5.5 SS (mv/dec) SS (mv/dec) Si d = 3 nm Ge d = 3 nm SS (mv/dev) SS (mv/dec) Si d = 5 nm Ge d = 5 nm Fig. 5. Subthreshold slopes of 3- and 5-nm-thick Si and Ge NWFETs with different crystal orientations. of 3 and 5 nm. At large gate lengths, each configuration exhibits a SS very close to its theoretical limit of mv/dec, but at short gate lengths, the SS drastically increases. In this case, the transistor characteristics are mainly determined by the imaginary band structure within the band gap. A low decay rate κ 0 shows a high electron transmission probability through the potential barrier separating the source and drain extensions, thus increasing the intraband tunneling currents and the subthreshold slope (SS). For example, κ 0 = 0.86 /nm when measured 0. ev below the ToB potential in a Si NWFET with d = 3 nm and transport along the <> axis, but κ 0 =.9 /nm if transport occurs along <>. The long-channel behavior of the ON-current is directly related to the electron effective mass in the transport direction, m.asmallm leads to a high ON-current. In Si NWFET with d = 3nm,m exhibits the lowest value in the <> direction (0.57 m 0 compared with 0.87 m 0 for the <>, and 0.4 m 0 for the <> direction). It is important to realize that m and κ 0 are not two independent quantities. They strongly depend on each other: a low m induces a low κ 0 too. Hence, in devices with 5 nm gate lengths, the performance boost obtained through a decrease of the transport effective mass and an increase of the injection velocity might be compensated by a severe deterioration of the subthreshold characteristics caused by a low decay rate κ 0. Finding a material with a good (m ;κ 0 ) compromise is therefore the key to design ultrashort transistors. On the basis of these considerations, Si NWFETs with <> as transport direction are investigated in the rest of this paper, as the (m ;κ 0 ) compromise is relatively favorable. In Ge, the crystal orientation that, however, offers the best

6 358 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL., NO. 7, JULY 03 Subthreshold slope (mv/dec) Si<> Si<> d=3nm d=4nm d=5nm d=6nm d=7nm d=8nm Ge<> Ge<> InAs<> InAs<> I on (µ A/µ m) Fig. 6. Intrinsic properties of Si, Ge, and InAs NWFETs as a function of their gate length and diameter. Subthreshold slope. Normalized ON-current. Points for which I OFF = 0. μa/μm could not be reached are omitted. performance at = 5 nm, <> (m = m 0, κ 0 = 0.67 /nm) poorly scales hence it is outperformed by <> (m = m 0, κ 0 =.0 /nm, indirect band structure) in short-channel devices. As this paper focuses on devices with sub-0-nm gate lengths, the <> orientation represents a better test case. Finally, the <> transport direction (m = m 0, κ 0 = 0.65 /nm) is chosen for InAs NWFETs. The SS and ON-state current per unit width of <> Si, <> Ge, and <> InAs NWFETs with diameters ranging from 3 to 8 nm and gate lengths varying from 5 to 5 nm are compared in Fig. 6. Each structure shows a monotonously increasing SS as its gate length decreases or its diameter increases. Hence, to maintain a good electrostatic control when the gate length shrinks to 5 nm, devices with a diameter below 5 nm are needed. The Si NWFETs produce the steepest SSs in all the d/l g configurations, as compared with Ge and InAs, except for the devices with the longest gate contact or with the smallest diameter (3 nm), where InAs dominates in every aspect. In terms of ON-current, the advantage of InAs is obvious, especially among the small diameter devices. The superiority of InAs over Si and Ge NWFETs at small diameters and short gate lengths, despite its smaller decay rate κ 0, can be attributed to the electrostatics and the band structure. Because of the high-κ gate dielectric and the low DOS, the InAs device operates in the quantum capacitance limit, making the band edge of the gate still controllable even when pushed below the source s CB edge [3]. On the other hand, the effective gate length of the InAs NWFETs is larger than that of their Si and Ge counterparts because of a lower doping concentration (3e9 versus e0 cm 3 ) and thus a larger Debye length [33]. This reduces sourceto-drain tunneling without affecting the ON-state current. The increased effective mass and hence increased decay rate in small diameter NWs also improve the performance [34]. At larger diameters, but still short gate lengths, the electrostatic control, however, becomes poorer, κ 0 smaller, intraband tunneling larger hence the InAs NWFETs exhibit no advantage over the Si and Ge ones any more. Furthermore, in some cases, it is not even possible to find a gate voltage or work function for which I OFF = 0. μa/μm. V. CONCLUSION A computationally very efficient -D ToB + UB model was introduced to simulate circular, gate-all-around NWFETs. The method was validated by comparing its results with 3-D, atomistic, full-band simulations, demonstrating that it accurately captured the relevant characteristics of ultrascaled devices. A systematic investigation of Si, Ge, and InAs devices was performed. NWs with diameters that were usually too large to be simulated in a 3-D, atomistic, full-band approach were considered. This paper revealed that small diameter InAs NWs provided significantly higher ON-currents per unit width than Si or Ge at matched OFF-current, although intraband tunneling was larger. As a next step, this methodology will be applied to study p-type NW transistors and compare the performance of different materials. There was no additional restriction to deal with hole instead of electron transport. More generally, the ToB + UB model can be employed to simulate any kind of -D (ultrathin body) and 3-D (NW) devices as long as a simple -D electrostatic model can be derived. The approach presented here will help device engineers investigate more rapidly the entire design space of structures they intend to fabricate. The code that was used to produce the above results is publicly available at:

7 SZABÓ AND LUISIER: UNDER-THE-BARRIER MODEL: AN EXTENSION OF THE TOP-OF-THE-BARRIER MODEL 359 APPENDIX DERIVATION OF THE MODIFIED POISSON EQUATION The derivative of the radial part of (9) is given by dr(r) = γ (c 3 J (γ r) + c 4 Y (γ r)). (5) dr Floating boundary conditions in the radial direction at r = b can be satisfied only if dr(r) dr = γ (c 3 J (γ b) + c 4 Y (γ b)) = 0. (6) b Using the above restriction along with (3), c 3 and c 4 can be expressed as follows: c 3 = Y (γ b)/ (Y (γ b)j 0 (γ b) J (γ b)y 0 (γ b)) c 4 = J (γ b)/ (Y 0 (γ b)j (γ b) J 0 (γ b)y (γ b)). (7) Through matching the electric displacement at the oxide semiconductor interface (r = a), we obtain from (6) and (0) c (x) = ε ox X (x) dr(r) a ε sc dr. a (8) Using the same two equations, and matching the potential too, (x) becomes (x) = 0 + X (x) R a c (x). (9) Through substituting the value of c and R in (9) using (5), (7), and (8), (x) depends only on the γ parameter. This ansatz is only valid far from the gate contact, where the electrostatic potential varies exponentially. Close to the gate region, the floating boundary condition described in (6) is neglected. The variable c (x) then expressed as a function of (x) before (8) is solved. From (3) and (8), we have the following: c 3 = c (x)/ X (x) α + λ, with α = aε sc γ (J (γ a) J 0 (γ b)y (γ a) / Y 0 (γ b)) ε ox λ = / (J (γ a)y 0 (γ b)/y (γ a) J 0 (γ b)). From (3), (8) (0), it follows that ( ) c (x) = X (x) à (x) / B, with à = λj 0 (γ a) + ( λj 0 (γ b)) Y 0(γ a) Y 0 (γ b) ( B = a α J 0 (γ a) J 0 (γ b) Y ) 0(γ a). Y 0 (γ b) (0) () Substituting () into (8) gives (4). The parameter γ is determined in each step such that the potential obtained from (9) [with the values of c (x), c 3,andc 4 from (5), (7), and (8)] matches the potential resulting from (4) at the interface between the far-from-gate and near-to-gate regions. REFERENCES [] D. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, and H.-S. P. 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