Simultaneous Device and Interconnect Optimization

Transcription

1 Smultaneous Devce and Interconnect Optmaton Smultaneous devce and wre sng Smultaneous buffer nserton and wre sng Smultaneous topology constructon, buffer nserton and wre sng WBA tree (student presentaton) P-tree Smultaneous devce and wresng Domnance-Property based approach to mnme weghted sum of delay Smultaneous drver/buffer and wresng [Cong-Koh, TVLSI 94] [Cong-Koh-Leung, ISLPED 96] Smultaneous transstor and nterconnect sng [Cong-He, PDW 96, ICCAD 96] Lagrangan relaxaton based approach to mnme maxmum delay Smultaneous buffer and wre sng [Chen-Chang-Wong, DAC 96] Mathematcal programmng based approach to mnme area whle meetng performance requrement Smultaneous gate and wresng [Menees-Baldck-Plegg, ICCAD 95] Fall 1999, Prof. Le He 1

2 Cg RC Delay Model for Drvers Rp Rn Cd Swtch level RC Model for mnmum se drver d 1 d 2 t D (T,D) Delay of -th Drver = R mn = resstance of mn-se drver d = se of -th drver C g = gate capactance of mn-se drver C d = dffuson capactance of mnse drver d R d mn dk (dc d+d + 1C g) Delay from 1st to 2nd last drver, t d(t,d) = Delay of -th drver k-1 =1 Total Delay Measure t(k,d,w) Interconnect delay from last drver to snks t(w) l = λ t(n) snk N where λ s user - specfed normaled non - negatve parameter to prorte snk N Total Delay Measure: t(k, D,W) = t D(k,D) + t l(w) Where t D (T,D) s the delay from 1st to 2nd last drver t l (W) s the nterconnect delay from last drver to snks Fall 1999, Prof. Le He 2

3 Power Dsspaton Formulaton Short-crcut: ScP() d Short crcut Power = ScP() Capactve: CP() (d C d +d +1 C g ) for I< k CP(k) (d k C d +C IL ) C IL : load due to routng tree Capactve Power = = 1 k = 1 CP() Total Power = Capactve + Short-Crcut k Man Theorem: Relaton between Drver and Wre Sng Gven (D,W) and (D, W ) for k drvers f W = opt-ws(d) and W = opt-ws(d ) Â D domnates D => W domnates W f D = opt-ds(w) and D = opt-ds(w ) Â W domnates W => D domnates D Fall 1999, Prof. Le He 3

4 K-SDWS LU-Bound algorthm for Delay Optmaton Lower bound of SDWS optmal soluton Domnate W 0 = Mn. Wdth Assgnment (domnated by opt. sol.) D 0 = Opt-DS(W 0 ) (D,W ) monotoncally nreases W 1 = Opt-WS(D 0 ) D 1 = Opt-DS(W 1 ) (D,W ) domnated by optmal soluton K-SDWS Optmal algorthm for Delay Optmaton Case 1: the bounds meet Optmal k-sdws soluton Case 2: bounds do not meet Dscrete drver ses of k-th drver between the bounds For each dscreted drver compute optmal ses for k-1 drvers and wres Select best d-sdws soluton SDWS Optmal Algorthm for Delay Optmaton Lnear search for the optmal stage number, k* ln C ( T, W )/ C * k = s ln * D IL MAX g 1+ a/ s = and s* = e where a Cd/Cg MAX ( 1 k k* D MAX ) Fall 1999, Prof. Le He 4

5 K-SDWS Optmal algorthm for Combned Delay and Power Optmaton Compute Optmal Drver Sng Solutn by MAPLE 1 d A+ B d 1 d 1 A+ B dk dl 2 dk C = 0 Select Monotone = 0 for all = 2 to k -1 g Soluton Lnear search for the optmal stage number, k* (1 k* k k DP MAX DP MAX -1 ) : smallest stage number s.t. w MAX has no monotone drver soluton Experments to Evaluate SDWS Algorthm Compared wth other desgn methods: CDSMIN (Constant Drver Sng, rato e and MINmum wre wdth) 1 / k ODSMIN (Optmal Drver Sng, d + 1 C L = d C g MINmum wre wdth) DWSA [Cong-Koh-Leung, LPDW 94) (Independent constant Drver Sng wth rato e, optmal wre wdth) Fall 1999, Prof. Le He 5

6 Expermental Results on Power-Delay Trade-off Smultaneous Transstor and Interconnect Sng [Cong-He,PDW & ICCAD 96] Gven: Determne: Mnme: Intal layout desgn for multple nets, Table-based models for devce delay and nterconnect couplng capactances Dscrete ses for transstors/wres α Delay + β Power + γ Area Fall 1999, Prof. Le He 6

7 Objectve for Delay Mnmaton R ( ) (, ) 0 ( ) R0 ( ) t X = F j C0( j) x F(, j) C1( j j + ) x x, j, j R ( ) 0 ( ) R0 ( ) H ( ) C1( x + x + G : C 0 R 0 : resstance for unt-wdth transstor/wre area capactance for unt-wdth transstor/wre C 1 : frngng capactance for transstor/wre X = x, x,..., x }: dscrete wdths for transstors/wres { 1 2 n To mnme t(x) s a smple CH-posynomal program ) Domnance Property for Smple CH-posynomal Programs To mnme f ( X ) m m = p = 0 q = 0 = 1 j = 1, j n ) ( b s a smple CH-posynomal program where a p and b qj are postve constants. Theorem ([Cong-He, pdw 96] The domnance property holds for smple CH-posynomal program w.r.t. the local refnement. If X domnates optmal soluton X* X = local refnement of X Then, X domnates X* Symmetrc for X domnated by X* n ( a p p x qj x q j ) Fall 1999, Prof. Le He 7

8 Overvew of STIS Algorthm Support mxed transstor sng formulatons: fnd an optmal se for each gate, each pull-up or pull-down block, or each transstor Algorthm Flow n Partton devces and nterconnects nto DC-Connect- Components (DCCs) o Compute TIGHT lower and upper bounds by teratve LR (local refnement) for devces and wres wthn each DCC p Compute optmal soluton wthn bounds by bottom-up dynamc program [Llls-et al, ICCAD 95] wthn each DCC Expermental Results Clock nets of 12.7Mchp/s all dgtal BPSK drect sequence spread spectrum IF transcever Chp n UCLA1 rado for wreless multmeda nformaton systems Clock nets routed nteractvely wth Flnt, fabrcated by 1.2um SCMOS technology CLK net: 112 nverters and 255 snks DCLK net: 31 nverters and 123 snks Manually desgned drver/buffer: cascade chan of 4 nverters Ideal nter-clock skew = 0: Fall 1999, Prof. Le He 8

9 Manual Desgn versus LR-Based Optmatons manual SBWS STIS max delay (ns) (-6.2%) (-14.4) average power(mw) (-24.3%) 46.29(-24.2%) clock skew 470ps 130ps(-3.6x) 40ps(-11.7x) Transstor sng formulaton can acheve hgher delay and skew reducton at a smlar power dsspaton Runtmes (wre segmentng: 10um) LR-based SBWS 1.18s, STIS 0.88s Dynamc programmng run out of memory Total HSPICE smulaton ~2000s Trend of Devce Effectve Resstance effectve-resstance R 0 for unt-wdth n-transstor se = 100x c l \t t 0.05ns 0.10ns 0.20ns 0.225pf pf pf se = 400x c l \t t 0.05ns 0.10ns 0.20ns 0.501pf pf pf R 0 s NOT a constant. It depends on se, nput slope t t and output load c l May dffer by a factor of 2 NOT a functon of a sngle sng varable Invaldate smple CH-posynomal Fomulaton! Fall 1999, Prof. Le He 9

10 Bounded CH-Posynomal Program and Extended Local Refnement To mnme f ( X ) m m = p = 0 q = 0 = 1 j = 1, j n n ( a p ( X ) q ) ( b qj ( X ) p x x j s a general CH-posynomal, when a p and b qj are arbtrary functons of X, but each has an upper and lower bound. Extended local refnement on w.r.t X s local refnement usng followng coeffcents: When X domnates X*, for any p, q and j, we use max mn 1 a ( ), p nstead of a p X for 1p x a q qj nstead of aqj ( X ) for x j p q b nstead of (X ) for x, b nstead of (X ) for x j mn p b p x max qj Symmetrc operaton when X s domnated by X* b qj ) Domnance Property for Bounded CH-Posynomal Program Theorem ([Cong-He, ISPD 98]: The domnance property holds for bounded CH-posynomal program w.r.t. the extended local refnement. If X domnates optmal soluton X* X = extended local refnement of X Then, X domnates X* If X s domnated by X* X = extended local refnement of X Then, X s domnated by X* Applcaton: Devce and wre sng problem under general capactance model under table-based devce delay model Fall 1999, Prof. Le He 10

11 Extended Local Refnement for Devce When max R 0 ( ) mn R 0 ( ) * X X, we use: for LR optmaton on transstor for LR optmaton on transstors rather than * When X X, we use: mn R 0 ( ) for LR optmaton on transstor max R 0 ( ) for LR optmaton on transstors rather than max R ( ) and are determned 0 R mn 0 ( ) under assumpton that R 0 ncreases w.r.t. ncreases of se and nput slope decrease of output load table lookup usng keepng updated lower and upper bounds on transstor se, nput slope and output load Comparson between STIS Formulatons Dfferent formulatons on DCLK and 2cm lne Parameters are based on 0.18um process Optmal buffer nserton s used for 2cm lne DCLK step-model table-model sgws (-6.8%) sts 1.13 (-2.5%) 0.96 (-17.2%) 2cm lne step-model table-model sgws (-0.4%) sts 0.75 (-8.6%) 0.69 (-16.5%) Total runtme LR-based optmaton ~10 seconds HSPICE smulaton ~3000 seconds Fall 1999, Prof. Le He 11

12 GISS can be Solved as General CH-Posynomal Program Center spacng Average Delays(ns) Runtmes (s) MIN GISS/DP GISS/LR GISS/DP GISS/LR 2 x ptch (-47% ) 0.79 (-47% ) x ptch (-61% ) 0.52 (-61% ) x ptch (-67% ) 0.42 (-67% ) x ptch (-71% ) 0.36 (-71% ) x ptch (-72% ) 0.32 (-73% ) bt bus Mn GISS/DP GISS/LR each a 10mm-long lne, 500um per segment mn wdth (max spacng) dynamc programmng based and under varable c a and c f LR-based and under general cap table Smultaneous Devce and Interconnect Optmaton Smultaneous devce and wre sng Smultaneous buffer nserton and wre sng Smultaneous topology constructon, buffer nserton and wre sng Fall 1999, Prof. Le He 12

13 Buffer Inserton wth Wresng [Llls-Cheng-Ln, ICCAD 95] Objectve s to mnme power subject to delay constrants Incorporate the effect of sgnal slew on buffer delay usng pece-wse lnear functons In the bottom-up phase, consder dscrete wresng for each edge e, For each opton (c, q), canddate wre wdth w, cap(e, w) = wre cap. of e wth wdth w res(e, w) = wre res. of e wth wdth w Compute new opton (c, q ): c = c + cap(e, w); q = q - res(e, w) (cap(e, w)/2 + c) Addtonal prunng rule consdered for power mnmaton: Optons (c, q) wth power p, and (c, q ) wth power p, prune (c, q) f p < p, c c, q q Smultaneous Buffer Inserton/Sng and Wresng [Chu-Wong, ISPD 97] Assumptons: Consder only area capactance Contnue wre wdths and buffer ses wthout bounds Problem: Gven a sngle lne, drver resst., load, and the total number of segments n to be used Objectve: fnd () the optmal number of buffers to be nserted n ther locatons and ses () the optmal length and wdth of each segment Fall 1999, Prof. Le He 13

14 Smultaneous Buffer Inserton/Sng and Wresng contnued Results and Implcatons: Closed form formula for optmal number of buffers All segments n the optmal soluton are of equal length Closed form formulas for buffer and wre ses, for any gven buffer locatons Buffer locatons do not matter, as long as delay s the only objectve and the buffer and wre ses are not bounded For delay mnmaton, a chan of cascade drvers s as good as usng buffers to break a long lne However, power and area wll be affected by buffer locatons For nterconnect tree, apply the formulas on edges teratvely; keep buffer locatons/ses and wre wdths of other edges fxed whle optmng one edge Shortcomng: Ignore frngng capactance whch s sgnfcant n deep submcron Comparson of Several Interconnect Optmaton Algorthms T+B+W:Topology (T), followed by optmal buffer nserton and sng B (B=10) then followed by optmal wre sng (W=18) TB+BW: Smultaneous T and B (B=3), followed by smultaneous buffer and wre sng (BW) wth B=40, W=18 Tbw+BW: Smultaneous TBW wth small number of B=3 and W=3, then followed by BW as above TBW: Smultaneous TBW wth larger number of B=10 and W=8 Provded by the UCLA TRIO (Tree, Repeater, & Interconnect Optmaton) package Fall 1999, Prof. Le He 14

15 Comparson of Optmaton Results by Dfferent Algorthms 5-pn nets 10-pn nets 20-pn nets Delay (ns) Algorthms T+B+W TB+BW Tbw+BW TBW CPU (S) Delay (ns) CPU (S) Delay (ns) CPU (S) Fall 1999, Prof. Le He 15