Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V th Assignment and Path Balancing

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1 Leakage and Dynamc Gltch Power Mnmzaton Usng Integer Lnear Programmng for V th Assgnment and Path Balancng Yuanln Lu and Vshwan D. Agrawal Auburn Unversty, Department of ECE, Auburn, AL 36849, USA luyuanl@auburn.edu, vagrawal@eng.auburn.edu Abstract. Ths paper presents a novel technque, whch uses nteger lnear programmng (ILP) to mnmze the leakage power n a dual-threshold statc CMOS crcut by optmally placng hgh-threshold devces and smultaneously reduces the gltch power usng the smallest number of delay elements to balance path delays. The constrant set sze for the ILP model s lnear n the crcut sze. Expermental results show 96%, 40% and 70% reducton of leakage, dynamc and total power, respectvely, for the benchmark crcut C755 mplemented n the 70nm BPTM CMOS technology. 1 Introducton In the past, the dynamc power has domnated total power dsspaton of a CMOS devce. Snce dynamc power s proportonal to the square of the power supply voltage, lowerng the voltage reduces the power dsspaton. owever, to mantan or ncrease the performance of a crcut, ts threshold voltage should be decreased by the same factor, whch ncreases the subthreshold (leakage) current of transstors exponentally [1]. Therefore, wth the trend of CMOS technology scalng, leakage power s becomng a domnant contrbutor to the total power consumpton. To reduce leakage power, a large number of technques have been proposed, ncludng transstor szng, mult-vth, dual-vth, optmal standby nput vector selecton, stackng transstors, etc. Dual-V th assgnment [-6] s an effcent technque to decrease leakage power. We et al. [3] descrbe an algorthm to fnd the optmal hgh V th for dfferent crcut structure. owever, n realty, the avalable threshold voltages n a process are predetermned and a desgner does not have the choce of arbtrary V th. The back trace algorthm [3] used to determne the dual-v th assgnment also has a dsadvantage. Because the back trace search drecton for non-crtcal paths s always from prmary outputs to prmary nputs, the gates close to the prmary outputs always have the prorty to be assgned hgh V th, even though ther leakage power reducton due to V th ncrease may be smaller than that of gates close to the prmary nputs. Ths algorthm only gves a possble soluton, not an optmal one. On the contrary, usng ILP, a global optmzaton soluton can be easly acheved. Nguyen et al. [6] use lnear programmng (LP) to mnmze the leakage and dynamc power by gate szng and dual-threshold voltage devces assgnment. owever, they have not consdered the gltch power, whch can account for 0%-40% of the dynamc swtchng power [7]. To elmnate these unnec- V. Palouras, J. Vounckx, and D. Verkest (Eds.): PATMOS 005, LNCS 378, pp. 17-6, Sprnger-Verlag Berln edelberg 005

2 18 Yuanln Lu and Vshwan D. Agrawal essary transtons, a desgner can adopt technques of hazard flter [7] or path balance [8]. Raja et al. [8] have proposed a technque whch uses a reduced constrant set lnear program (LP) to elmnate dynamc gltch power. The present work was motvated by the above research. A new ILP model s proposed to mnmze leakage power by dual-v th assgnment and smultaneously elmnate dynamc gltch power by nsertng zero-subthreshold delay elements to balance path delays. To our knowledge, no prevous work on optmzng dynamc and statc power has adopted such a combned approach. Ths ILP method s specfcally devsed wth a set of constrants whose sze s lnear n the number of gates. Thus, large crcuts can be handled. The ILP ether holds the crtcal path delay correspondng to the all-low V th gates, or allows an ncrease by a user-specfed amount. As a result, a tradeoff between power savng and performance degradaton can be allowed. To deal wth the complextes of delay models and leakage calculaton, two look up tables for the delay and leakage current are constructed n advance for each cell. Ths greatly smplfes the optmzaton procedure. To further reduce power, other approaches such as gate szng can be easly mplemented by extendng our cell lbrary and look up tables. Leakage and Delay The leakage current of a transstor s manly the result of gate leakage, reverse bas PN juncton leakage and subthreshold leakage. Compared to the subthreshold leakage, the reverse bas PN juncton leakage can be gnored. The subthreshold leakage current s the weak nverson current between source and dran of an MOS transstor when the gate voltage s less than the threshold voltage [1]. Subthreshold current s gven by []: I sub = u C 0 ox W L eff eff 1.8 T e V Vgs V exp nvt th V 1 exp VT where u 0 s the zero bas electron moblty, and n s the subthreshold slope coeffcent. Due to the exponental relaton between V th and I sub, we can ncrease the V th to reduce the subthreshold current sharply. Our SPICE smulaton results on the leakage current of a two-nput NAND gate show that, for 70nm CMOS technology (Vdd=1V, Low V th =0.0V, gh V th =0.3V), the leakage current n a hgh V th gate s only about % of the leakage current n a low V th gate. If all gates n a CMOS crcut could be assgned the hgh threshold voltage, the total leakage power consumed n the actve and standby modes can be reduced by 98%, whch s a sgnfcant mprovement. owever, the gate delay ncreases wth the ncrease of V th. From SPICE smulaton result for a NAND gate delay when the output fans out to a specfed number of nverters, we observe that the gate delay ncreases 30%-40% by ncreasng V th form 0.0V to 0.3V. Thus, we can make tradeoffs between leakage power and performance, leadng to a sgnfcant reducton n the leakage power whle sacrfcng only some or no crcut performance. Such a tradeoff s made n the ILP. Results n Secton 4.1 show that the ds (1)

3 Leakage and Dynamc Gltch Power Mnmzaton Usng Integer Lnear Programmng 19 leakage power of all ISCAS85 benchmark crcuts can be reduced by over 90% f the delay of the crtcal path s allowed to ncrease by 5%. 3 Integer Lnear Programmng To mnmze the leakage power, we use an ILP model to determne the optmal assgnment of V th whle controllng any sacrfce n performance. Due to the constrants on the maxmum path delay, all the gates on the crtcal path are assgned low V th. The V th assgnments of gates on the non-crtcal path are determned jontly by ther delay ncreases and leakage reductons f hgh V th were assgned to them. To elmnate the gltch power, addtonal ILP constrants determne the postons and values of the delay elements to be nserted to balance path delays. Unlke the heurstc algorthms [-5], ths ILP gves us a globally optmal soluton. We can easly make a tradeoff between power reducton and performance degradaton by changng the constrant for the maxmum path delay n the ILP model. 3.1 ILP for Leakage Power reducton Raja et al. [8] proposed a LP formulaton to reduce dynamc gltch power by a reduced constrant set lnear program whose number of constrants s proportonal to the total number of gates. We frst modfy ther formulaton nto an nteger lnear program (ILP) to reduce subthreshold leakage power as descrbed below Varables Each gate has two varables. T : the latest tme at whch the output of gate can produce an event after the occurrence of an nput event at prmary nputs of the crcut. X : the assgnment of low or hgh V th to gate ; X s an nteger whch can only be 0 or 1. A value 1 means that gate s assgned low V th, and 0 means that gate s assgned hgh V th Objectve functon In a CMOS statc crcut, the leakage power s P = V I () leak dd leak If we know the leakage currents of all gates, the leakage power can be easly obtaned. Therefore, the objectve functon for ths ILP s to mnmze the sum of all gate leakage currents, whch s gven by ( X I L + ( X ) I ) Mn 1 (3) I L s the leakage current of gate wth low V th; I s the leakage current of gate wth hgh V th;

4 0 Yuanln Lu and Vshwan D. Agrawal The leakage current of a gate depends on the nput vector. Therefore, we make a leakage current look up table, whch s ndexed by the gate type and the nput vector. I L and I can both be searched from ths look-up table. The values n ths lookup table, as found by Smart-SPICE smulaton, are the total leakage currents ncludng subthreshold and gate leakages of a cell under specfc nput vector condtons Constrants Constrants for each gate: j L ( X ) D T T + X D + 1 (4) 0 X 1 (5) Constrant (5) assgns ether low V th (X =1) or hgh V th ( X =0) to gate ; D s the delay of gate wth hgh V th ; D L s the delay of gate wth low V th. Wth the ncrease of the fanout, the delay of the gate also ncreases proportonately. Therefore, a second look-up table s constructed and specfes the delay for gven gate type and fanout number. D and D can be searched from ths look-up table ndexed by the gate type and the number of fanout of gate. We explan constrant (4) usng the crcut of Fgure 1. Let us assume that all prmary nput (PI) sgnals on the left arrve at the same tme. For gate, one nput s from gate 0 and the other nput s drectly from a PI. Its constrants correspondng to nequalty (4) are gven by Fg. 1. Crcut for explanng ILP constrants. + ( X ) D ( X ) D T T + X D (6) T (7) 0 L X DL + 1 T that satsfes both nequaltes s the latest tme at whch an event (sgnal change) may occur at the output of gate. Max delay constrants for prmary outputs (PO): T T max (8) T max can be the crtcal path delay when all the gates are assgned low V th or the maxmum delay specfed by the desgner. We use a smplfed ILP model, whose descrpton s omtted here, to fnd the delay T c of the crtcal path. If T max equals T c the objectve functon of our ILP model wll be to mnmze the total leakage current

5 Leakage and Dynamc Gltch Power Mnmzaton Usng Integer Lnear Programmng 1 wthout affectng the crcut performance. By makng T max larger than T c, we can further reduce leakage power wth some performance compromse, and thus make a tradeoff between leakage power consumpton and performance. 3. ILP for Leakage Power and Dynamc Gltch Power reducton Gltches can account for 0%-40% dynamc power [7]. To elmnate these unnecessary transtons, a desgner can adopt technques of hazard flter [7] or path balance [8]. Combned wth the method of path balance, the technque of Secton 3.1 can be extended to reduce leakage power and dynamc gltch power smultaneously. Such an extended ILP model s developed below Varables Each gate has four varables: X : the assgnment of low or hgh V th to gate ; X s an nteger whch can only be 0 or 1. A value 1 means that gate s assgned low V th, and 0 means that gate s assgned hgh V th. T : the latest tme at whch the output of gate can produce an event after the occurrence of an nput event at prmary nputs of the crcut. t : the earlest tme at whch the output of gate can produce an event after the occurrence of an nput event at prmary nputs of the crcut. d,j : the delay of the nserted buffer at the j th nput path of gate. 3.. Objectve Functon The objectve functon for ths ILP s to mnmze the sum of all gate leakage currents and the sum of all nserted delays: Mn I leak + d, j j = Mn ( X + ) + I L (1 X ) I d, j j Besdes the objectve to mnmze the leakage power consumpton whch s the same as Equaton (3), an addtonal objectve functon s to mnmze the gltch power. We nsert mnmal delays to balance path delays and elmnate gltches. Ths leads to another objectve functon: Mn, j d j Our objectve functon (9) combnes objectves (3) and (10). When mplementng these delay elements, we use transmsson gates wth only the gate leakage, whch s much smaller than the subthreshold leakage and can be gnored. (9) (10) 3..3 Constrants Constrants for each gate: 0 X 1 (11) j ( X D + (1 X D ) T >= T + d ) j + (1), L

6 Yuanln Lu and Vshwan D. Agrawal j ( X D + (1 X D ) t <= t + d ) L j + (13), L X D + ( 1 X ) D >= T t (14) where, s the the gate on whch constrants are set, and j s the the gate whose output s gate s fann. Constrants (1-14) ensure that gate s nertal delay s always larger than the delay dfference of ts nput paths by nsertng some delays on ts faster nput paths. Therefore, gltches can be elmnated. We explan constrants (1-14) usng the crcut shown n Fgure 1. Let us assume that all prmary nput (PI) sgnals on the left arrve at the same tme. For gate, one nput s from gate 0 and the other nput s drectly from a PI. Its constrants correspondng to nequalty (1-14) are: X DL + ( X ) D DL + ( X ) D X DL + ( X ) D DL + ( X) D ( X ) D T T T0 + 1 (15) T 0 + X 1 (16) t t (17) t 0 + X 1 (18) X DL + 1 t (19) Tme T that satsfes both nequaltes (15) and (16) s the latest tme at whch an event (sgnal change) may occur at the output of gate. Tme t s the earlest tme at whch an event may occur at the output of gate, f t satsfes both nequaltes (17) and (18). Constrant (19) means that the dfference of T and t, whch equals the delay dfference between two nput paths, s smaller than gate s nertal delay, whch may be ether low V th gate delay, D L, or hgh V th gate delay, D. Max delay constrants for prmary outputs (PO): T T max (0) As n Secton 3.1, T max can be the maxmum delay specfed by the crcut desgner or the crtcal path delay. When we use the ILP model to smultaneously mnmze leakage power wth dual- V th assgnments and reduce dynamc power by balancng path delays wth nserted delay elements, the optmzed verson for the crcut n Fgure s shown n Fgure 3. The label n or near a gate s ts nertal delay. Three black shaded gates are assgned hgh V th snce they are not on the crtcal path and ther delay ncreases do not affect the crtcal path delay. Two delay elements (grey shaded) are nserted to elmnate gltches. Although delay elements, f mplemented as buffer gates, may consume addtonal leakage power, we may assgn hgh V th to them. Therefore, the three low V th gates (wthout shadng) on the crtcal path stll domnate the total leakage power. Actually, n our desgn, delay elements are mplemented by CMOS transmsson gates that have no subthreshold leakage. Transmsson gates also consume very lttle dynamc power snce they are not drven by any supply rals [9].

7 Leakage and Dynamc Gltch Power Mnmzaton Usng Integer Lnear Programmng 3 Fg.. Unoptmzed crcut wth potental gltches Fg. 3. Optmzed crcut 4 Results To study the ncreasngly domnant effect of leakage power dsspaton, we use the BPTM 70nm CMOS technology. Low V th for NMOS and PMOS are 0.0V and - 0.V. gh V th for NMOS and PMOS are 0.3V and -0.34V, respectvely. We regenerate the netlsts of all ISCAS 85 benchmark crcuts usng a cell lbrary n whch the maxmum gate fann s 5. Two look-up tables for gate delays and leakage currents, respectvely, of each type of cell are constructed usng SPICE smulaton. A C program parses the netlst and generates the constrant set (see Secton 3) for the CPLEX ILP solver n the AMPL software package [10]. CPLEX then gve the optmal V th assgnment as well as the value and poston of every delay element. 4.1 Leakage Power Reducton The results of the leakage power reducton for ISCAS 85 benchmark crcuts are shown n Table 1. The numbers of gates n column are for the gate lbrary used and dffer from those for orgnal benchmark netlsts. T c n column 3 s the mnmum delay of the crtcal path when all gates have low V th. Column 4 shows the leakage reducton (%) for optmzaton wthout sacrfcng any performance. Column 6 shows the leakage reducton wth 5% performance sacrfce. The CPU tmes shown are for the ILP runs and are, as expected, lnear n crcut sze snce both number of varables and number of constrants are lnear n crcut sze. From Table 1, we see that by V th reassgnment the leakage current of most benchmark crcuts s reduced by more than 60% wthout any performance sacrfce (column 4). For several large benchmarks leakage s reduced by 90% due to a smaller percentage of gates beng on the crtcal path. owever, for some hghly symmetrcal crcuts, whch have many crtcal paths, such as C499 and C1355, the leakage reducton s less. Column 6 shows that the leakage reducton reaches the hghest level, around 98%, wth some performance sacrfce. The curves n Fg. 4. show the relaton between normalzed leakage power and normalzed crtcal path delay n a dual-v th process. Unoptmzed crcuts wth all low V th gates are at pont (1,1) and have the largest leakage power and smallest delay. Wth optmal V th assgnment, leakage power can be reduced sharply by 60% (from pont(1,1) to pont(1,0.4)) to 90% (from pont(1,1) to pont(1,0.1)), dependng on the

8 4 Yuanln Lu and Vshwan D. Agrawal crcut, wthout sacrfcng any performance. When normalzed T max becomes greater than 1,.e., we sacrfce some performance, leakage power further decreases n a slower reducton trend. When the delay ncrease s more than 30%, the leakage reducton saturates at about 98%. Therefore, Fgure 4 provdes a gude for makng a tradeoff between leakage and power. Ckt. Table 1. Leakage reducton due to dual-v th reassgnment 7 ). Gates # T c (ns) Leakage Red. (%) (T max=t c) Sun OS 5.7 CPU secs. Leakage Red. (%) (T max=1.5t c) Sun OS 5.7 CPU secs. C C C C C C C C C C Normalzed Leakage Power C43 C880 C Normalzed Crtcal Path Delay Fg. 4. Tradeoff between leakage power and performance. 4. Leakage, Dynamc Gltch and Total Power Reducton The leakage current strongly depends on the temperature. Our SPICE smulaton shows that for a -nput NAND gate wth low V th, when temperature ncreases from 7 to 90, the leakage current ncreases by a factor 10X. For a -nput NAND gate wth hgh V th, ths factor s 0X. The leakage n the look-up table s from smulaton for a 7 operaton. To manfest the domnant effect of leakage power, we estmate the leakage currents at 90 by multplyng the total leakage current obtaned from

9 Leakage and Dynamc Gltch Power Mnmzaton Usng Integer Lnear Programmng 5 CPLEX [10] by a factor between 10X and 0X as determned by the proporton of low to hgh threshold transstors. The dynamc power s estmated by a gltch flter event drven smulator, and s gven by P dyn E = T dyn dd ( T ) 0.5 Cnv V = c T FO where C nv s the gate capactance of one nverter, T s the number of transtons at gate s output when 1,000 random test vectors are appled at PIs, and FO s the number of fanouts. Vector perod s assumed to be 0% greater than the crtcal path delay, T c. By smulatng each gate s transton number, we can estmate the gltch power reducton. Table. (1) Leakage, dynamc and total power reducton comparson for unoptmzed and optmzed crcuts 90 ). Ckt. P leak1 P leak Leak. Red. (%) P dyn1 P dyn Dyn. Red. (%) P total1 P total Total Red. (%) C C C C C C C C C C We compare the leakage power and dynamc power at 90 n Table. The suffx-1 means the unoptmzed crcut whch has all the low threshold gates and the largest gltch power, and suffx- means the optmzed crcut whose V th has already been optmmally assgned and most of the gltches have been elmnated. We observe that for 70nm BPTM CMOS technology at 90, unoptmzed leakage power (column ) of some large ISCAS 85 benchmark crcuts can account for about one half or more of the total power consumpton (column 8). Wth V th reassgnment, the optmzed leakage power of most benchmark crcuts s reduced to less than 10%. Wth further gltch (dynamc) power reducton, total power reductons for most crcuts are more than 50%. Some have a total reducton of up to 70%. 5 Concluson A new technque to reduce the leakage and gltch dynamc power smultaneously n a dual-v th process s proposed n ths paper. An nteger lnear programmng (ILP) model

10 6 Yuanln Lu and Vshwan D. Agrawal s generated from the crcut netlst and the AMPL CPLEX [10] solver determnes the optmal V th assgnments for leakage power mnmzaton and the delays and postons of nserted delay elements for gltch power reducton. The expermental results for ISCAS 85 benchmark show reductons of 0%-96% n leakage, 8%-76% n dynamc (gltch) and 7%-76% n total power. We beleve some of the other technques, such as gate szng and dual power supply can also be ncorporated n the ILP formulaton. References [1] L. We, K. Roy and V. K. De, Low Voltage Low Power CMOS Desgn Technques for Deep Submcron ICs, Proc. 13th Internatonal Conf. VLSI Desgn, 000, pp [] M. Ketkar and S. S. Sapatnekar, Standby Power Optmzaton va Transstor Szng and Dual Threshold Voltage Assgnment, Proc. ICCAD, 00, pp [3] L. We, Z. Chen, M. Johnson and K. Roy, Desgn and Optmzaton of Low Voltage gh Performance Dual Threshold CMOS Crcuts, Proc. DAC, 1998, pp [4] L. We, Z. Chen, K. Roy, Y. Ye and V. De, Mxed-Vth (MVT) CMOS Crcut Desgn Methodology for Low Power Applcatons, Proc. DAC, 1999, pp [5] Q. Wang, and S. B. K. Vrudhula, "Statc Power Optmzaton of Deep Submcron CMOS Crcuts for Dual V T Technology," Proc, ICCAD, 1998, pp [6] D. Nguyen, A. Davare, M. Orshansky, D. Chnney, B. Thompson, and K. Keutzer, Mnmzaton of Dynamc and Statc Power Through Jont Assgnment of Threshold Voltages and Szng Optmzaton, Proc. ISLPED, 003, pp [7] V. D. Agrawal, Low Power Desgn by azard Flterng, Proc. 10 tth Internatonal Conference on VLSI Desgn, 1997, pp [8] T. Raja, V. D. Agrawal and M. L. Bushnell, Mnmum Dynamc Power CMOS Crcut Desgn by a Reduced Constrant Set Lnear Program, Proc. 16 tth Internatonal Conference on VLSI Desgn, 003, pp [9] N. R. Mahapatra, S. V. Garmella. A. Tarbeen, An Emprcal and Analytcal Comparson of Delay Elements and a New Delay Element Desgn, Proc. IEEE Computer Socety workshop on VLSI, 000, pp [10] R. Fourer, D. M. Gay, and B. W. Kernghan, AMPL: A Modelng Language for Mathematcal Programmng. South San Francsco, Calforna: The Scentfc Press, 1993