Distributed Sleep Transistor Network for Power Reduction

Transcription

1 11.3 Dstrbuted Sleep Transstor Network for Power Reducton Changbo Long ECE Department Unversty of Wsconsn, Madson Le He EE Department UCLA ABSTRACT Sleep transstors are effectve to reduce dynamc and leakage power. The cluster-based desgn was proposed to reduce the transstor area by clusterng gates to mnmze the smultaneous swtchng current per cluster and then nsertng a transstor per cluster. In the paper, we propose a novel dstrbuted transstor network (DSTN), and show that DSTNs ntrnscally better than the clusterbased desgn n terms of the transstor area and crcut performance. We reveal propertes of optmal DSTN desgns, and then develop an effcent algorthm for gate level DSTNsynthess. The algorthm obtans DSTNdesgns wth up to 70.7% transstor area reducton compared to cluster-based desgns. Furthermore, we present custom layout desgns to verfy the area reducton by DSTN. Categores and Subject Descrptors B.7.1 [Integrated Crcuts]: Types and Desgn Styles. General Terms Desgn. 1. INTRODUCTION Lowerng supply voltage s effectve for power reducton because of the quadratc relatonshp between supply voltage and dynamc power consumpton. To compensate the performance loss due to a lower supply voltage, transstor s threshold voltage V t should be also reduced, whch causes exponentally ncrease n the sub-threshold leakage current [1]. Mult-threshold CMOS (MTCMOS, see fgure 1) has been ntroduced wth low V t modules connected to ground through hgh V t transstors called transstors [2]. The Ths research s partally supported by NSF CAREER Award , SRC grant HJ-1008, and a grant from Intel. We used computers donated by Hewlett-Packard, Intel and SUNMcrosystems. Address comments to lhe@ee.ucla.edu. Permsson to make dgtal or hard copes of all or part of ths work for personal or classroom use s granted wthout fee provded that copes are not made or dstrbuted for proft or commercal advantage and that copes bear ths notce and the full ctaton on the frst page. To copy otherwse, to republsh, to post on servers or to redstrbute to lsts, requres pror specfc permsson and/or a fee. DAC 2003, June 2 6, 2003, Anahem, Calforna, USA. Copyrght 2003 ACM /03/ $5.00. transstor s turned off to reduce dynamc and leakage power n the standby mode, and s turned on to retan functonaltes n the actve mode. ates V dd V st Vrtual Ground Sleep transstor Fgure 1: MTCMOS crcut structure In ths paper, we propose a novel dstrbuted transstor network (DSTN) wth nherent advantages n area and performance compared to module-based and cluster-based transstor desgns [3, 4]. We wll dscuss background knowledge n Secton 2, ntroduce the concept of DSTNn Secton 3, and propose a gate-level DSTNsynthess methodology n Secton 4. We wll present experments of gate-level synthess and custom layout desgn n Secton 5 and conclude n secton 6. Proofs of all theorems can be found n the techncal report[5]. 2. BACKGROUND When transstors are absent, the propagaton delay for a CMOS gate can be approxmated by T pd C LV dd (V dd V tl) α, (1) where C L s the load capactance, V tl s the threshold voltage n the low V t module, and α s the velocty saturaton ndex for modelng short channel effects [6]. When the transstor s present and the source dran voltage drop s V st, the gate propagaton delay ncreases to T pd MT C LV dd (V dd V st v tl) α. (2) In order to measure the ncrease n propagaton delay, the followng performance loss (PL) s defned [4]: PL = T pd T pd MT. (3) 181

2 Accordng to the analyss n [4], for PL = δ, wehave V st = δ(v dd V tl), (4) R st = δ(v dd V tl) I st, (5) ( W L )st = I st δµ nc ox(v dd V tl)(v dd V th), (6) where I st s the swtchng current n the low V t module, V th s the threshold voltage of the transstor and s hgher than V tl n the low V t module (we assume V tl = 350mV and V th = 500mV n ths paper), and R st s the channel resstance of the transstor n the lnear-operaton regon. The tolerable performance loss can be dfferent among transstors. For example, f all the gates n a partcular low V t module are not n the crtcal path, large performance loss n ths module s acceptable as long as the module does not become a part of the crtcal path. For the smplcty of presentaton, we assume n ths paper that all modules share the same PL value. On the other hand, I st s dfferent wth respect to dfferent nput vectors. To guarantee that the PL constrant holds for all possble nput vectors, the maxmum smultaneous swtchng current (MSSC) should be used to replace I st n (6) to calculate the sze of the transstor. Our work s nspred by the followng MSSC analyss. In cluster-based desgns [4], one cluster of gates share one transstor. The area of the transstor st s proportonal to MSSC(c ), where c P denotes a cluster. If transstors are deally szed, the total area A of all transstors s proportonal to MSSC(c),.e., A = k P MSSC(c) wthk beng a constant. On the other hand, the entre crcut s accommodated only by one large transstor n module-based desgns [3]. The deal sze of ths transstor P s k MSSC(ckt), where MSSC(ckt) s MSSC of the entre crcut. Note that MSSC(ckt) smuch smaller than MSSC(c) when the cluster sze s small. For example, consder an extreme case that every cluster contans only one gate. P MSSC(c) s the sum of the peak current for all gates. MSSC(ckt) sthesumofpeak current for those gates that smultaneously swtch under a same nput vector. Snce only a small part of gates can swtch smultaneously, MSSC(ckt) s much smaller than P MSSC(ct). Therefore, the module-based desgn saves transstor area compared to the cluster-based desgn. Let vrtual-ground wres be nterconnects connectng the transstor to low-v t gates. The above analyss does not consder the vrtual-ground wres. The module-based desgn, however, leads to long vrtual-ground wres as ponted out n [4]. The ncreased resstance of vrtual-ground wres has to be compensated by more area n the transstor. Such overhead can be avoded by havng a local transstor per cluster, and transstor area can be further reduced by clusterng gates to mnmze the MSSC n the cluster. Mnmzng MSSC ntroduces extra constrants for placement, and may conflct wth tmng-drven placement. In the next secton, we wll propose our DSTNdesgn, and show that DSTNhas a reduced area for both transstors and vrtual-ground wres, and s compatble wth tmng-drven placement. Owng to the fact that the clusterbased desgn s better than the module-based desgn [4], we compare DSTNmanly wth cluster-based desgn n the rest of the paper. 3. SLEEP TRANSISTOR NETWORK We llustrate the cluster-based transstor desgn n fgure 2.(a), where gates n a cluster are connected to the transstor for ths cluster by vrtual-ground wres. Vrtualground wres of dfferent clusters are not connected. By addng more wres to form a mesh contanng all vrtualground wres, we obtan the DSTNstructure n fgure 2.(b). We assume that all transstors share a common control sgnal n both desgns. Gates VDD Sleep Transstor (a) Vrtual Ground Tappng Pont (b) Vrtual Ground Fgure 2: (a) Cluster-based desgn, and (b) Dstrbuted transstor network Module 1 Dschargng current Dschargng current Transstor 1 Transstor 2 Module 2 Module 3 Dschargng current Transstor 3 Fgure 3: Current dschargng balance n DSTN We wll show that DSTNreduces the transstor area compared to the cluster-based desgn. The area savng can be explaned by the dschargng current balance phenomenon. As shown n fgure 3, the swtchng current n module 2 s larger than those n module 1 and module 3. When dschargng current flows over transstors, the voltage drop n transstor 2 tends to be larger than the voltage drop n transstor 1 and 3, whch causes a part of current from module 2 flowng to transstors 1 and 3 1. The total area of all the transstors n DSTNcan thus be sgnfcantly reduced wth presence of such current dschargng balance. However, owng to the parastc resstance and capactance n vrtual-ground wres, the total transstor area should be larger than the followng MSSC(ckt) δµ nc ox(v dd V tl)(v dd V th), (7) whch s the optmum area for the sngle transstor n the module-based desgn ntroduced n [3], and also the deal total transstor area n DSTN. 1 A smlar dschargng current balance has been dscussed n P/G modelng [7]. 182

3 Addtonal connecton for STN MSSC(Cluster) Sleep transstor Path connectng transstors Low Vt Module R Rst Fgure 4: Physcal desgn of the STN Fgure 5: Resstance network modelng of the DSTN The routng area overhead s a crucal aspect for all three types of transstor desgn because every gate n the crcut has to be connected to a transstor. Dfferent transstor desgns mpose dfferent requrements for routng n terms of wre length and wre sze. We assume n ths paper that transstors are connected to the deal ground. Although DSTNand the module-based desgn may have the same topology for vrtual-ground wres, the wre sze for DSTNs found to be smaller due to the proxmty of transstors. On the other hand, DSTNneeds more vrtual-ground wre segments than the cluster-based desgn. As llustrated by the DSTNlayout n fgure 4, where the dotted lnes are vrtual-ground wres nsde modules and are requred by both DSTNand cluster-based desgn. Sold lnes are vrtual-ground wres that are needed by DSTN. These sold lnes are short for compacted layout desgn. When the chp has a few solated compacted layout regons such as IP-blocks n system-on-chp desgns, we can smply apply ndvdual DSTNnsde each IP-block wthout ntroducng extralongvrtual-groundwres. Furthermore, ntroducng cluster methodologes n the transstor desgn can affect placement. A good clusterng soluton mnmzng the cluster MSSC s crucal to reducng transstor area n the cluster-based desgn. Such clusterng helps DSTNas well. However, our experments to be presented shows that DSTNwthout cluster current mnmzaton acheves sgnfcant transstor area reducton compared to the cluster-desgn wth cluster current mnmzaton. Due to the adverse effect of MSSC mnmzaton on tmng-drven placement, we suggest not applyng cluster current mnmzaton to DSTN. 4. GATE LEVEL DSTN DESIGN In ths secton, we frst present the DSTNmodelng, then formulate and solve the DSTNszng problem. In order to compare dfferent desgn styles, we wll also ntroduce a rgorous algorthm for cluster-based transstor desgn. 4.1 DSTN modelng We model both transstors and vrtual-ground wres as resstors. Therefore, DSTNcan be modeled as a resstance network shown n fgure 5, wth resstance R st for a transstor and R for a vrtual-ground nterconnect. Note that R s needed to accurately model the dscharge current balance. Exact estmaton of R, however, requres detaled layout nformaton. In gate level desgn, we assume that R s unform for each wre. Specfcally, we assume that the wre resstance s 0.05Ω/µm. We consder vrtual-ground wres that are 200µm and 1000µm long,.e., we consder R = 10Ω and 50Ω, respectvely. Gven our assumpton that each cluster has about sx gates (decded by the typcal transstor sze n secton 4.2), 200µm s a conservatve estmaton for vrtual-ground wres between clusters, and 1000µm serves as the worst-case scenaro to analyze the mpact of R. 4.2 DSTN szng Problem formulaton We assume n ths paper that the topology of DSTNs defned as apror, and formulate the followng DSTNszng problem: Formulaton 1. DSTN szng problem(dstn-sp): For gven DSTN topology, the DSTN-SP problem fnds a sze for every transstor n DSTN such that the total area of DSTN s mnmzed and the PL constrant s satsfed for every cluster. Note that DSTN szng s totally dfferent from the transstor szng n the cluster-based desgn. The sze of the transstor n the cluster-based desgn s solely determned by the MSSC of the accommodated cluster. Owng to dschargng current balance n DSTN, the sze of a transstor n DSTNdepends on the current gong through the accommodated cluster, the adjacent clusters, and even non-adjacent clusters. Ths makes the DSTNszng problem much harder than the szng problem of the cluster-based desgn. More precsely, DSTNcan be modeled by a resstance network, and then the accurate transstor szng can be obtaned by algorthms smlar to P/G szng algorthms n [8]. We expect that well-desgned heurstcs may as well lead to good solutons, but n a more effcent fashon. We reveal below a few mportant propertes n order to develop effectve heurstcs Propertes Note that our propertes are based on an mportant observaton about the resstance network: R s normally much smaller than R st. The channel resstance of the transstor n the lnear-operaton regon s 1 R st = µ nc ox(v dd V ( L ). (8) th) W We assume V th = 500mV, a typcal transstor n DSTNhas W =6,andV L dd =1.3V n 100nm technology. 183

4 Thus, the typcal resstance value for R st s around 218 Ω. On the other hand, a 200µm long vrtual-ground wre has R of about 10Ω n 100nm technology. Therefore, t s reasonable to assume that R st s much larger then R. Theorem 1. Assumng R =0and PL = δ, the total transstor area n DSTN s determned by: X ( W L ) = MSSC(ckt) δµ nc ox(v dd V tl)(v dd V th) When R = 0, all transstors n DSTNcan be vewed as one sngle transstor wth channel resstance and (W/L) of: 1 R = (10) P W L =X 1/Rst (9) ( W L )st (11) Because the current of the entre crcut goes through ths sngle transstor, the followng equaton holds: W L = MSSC(ckt) δµ nc ox(v dd V tl)(v dd V th) Combnng (12) and (11) leads to (9). We can also prove: (12) Theorem 2. To mantan PL as a constant, the total area of DSTN ncreases when R ncreases. As R ncreases, the effectve resstance seen by the current source at each tappng pont ncreases. Thus, the voltage drop n the transstor ncreases when the current s constant. To mantan PL as a constant, the transstor resstance has to be decreased, whch results n more area consumpton n DSTN. The total area of DSTNcan be roughly determned by Theorems1and2together.IfR = 0, the total area of the DSTNs gven by (9). However, accordng to Theorem 2, the total transstor area n DSTNmust be larger than the value n (9). Nevertheless, the effectve resstance ncrease at the tappng pont s lmted because R s much smaller than R st. The ncrease of transstor area n DSTNs therefore lmted. Theorem 3. Assumng the current I that flows nto each tappng pont t beng constant and the total area of the DSTN gven, every transstor st accommodatng t should be szed proportonal to current I n order to mnmze the maxmum voltage drop among all transstors. Note that Theorem 3 s an deal case to allocate area to ndvdual transstors n DSTN. Although the current at each tappng pont t s not constant n real desgns, Theorem 3 helps gudng the desgn of our DSTNtransstor szng scheme below Algorthm The overall flow of the transstor szng scheme s descrbed as follows. We frst calculate MSSC(ckt) for example by genetc algorthm [9]. We then compute the total area n DSTNaccordng to the followng formula: MSSC(ckt) A =(1+β) δµ nc ox(v dd V tl)(v dd V. (13) th) Our experment shows that β should range from 0.05 to 0.5 and a larger β should be used for a bgger crcut. Fnally, accordng to Theorem 3, the total DSTNarea s allocated to each transstor st proportonally to the correspondent cluster MSSC. 4.3 Cluster based transstor nserton The total area of transstors for the cluster-based transstor P P desgn s proportonal to MSSC(c). Clusterng together gates wth dfferent swtchng tmes helps reduce MSSC(c), and n turn reduce the total area of transstors. The cluster based transstor nserton problem s formulated as follows, Formulaton 2. Cluster based transstor nserton: Gven a crcut and cluster sze, partton gates nto clusters such that the sum of MSSC for these clusters, and n turn the total area of all transstors s mnmzed. A cluster-based desgn methodology has been proposed wth placement constrants [4]. In ths paper, we target at reachng the P maxmum potental of transstor area reducton. Therefore we propose to apply smulated annealng (SA) for MSSC(c) mnmzaton wthout placement constrants. In SA, each cluster s assocated wth a cost of MSSC. The cost for the entre crcut s the sum of costs for all clusters. The objectve s to mnmze the cost for the entre crcut. We take advantage of the freedom that a gate can be assgned to any cluster. Specfcally, two gates are randomly pcked from two clusters and exchanged n each move. We start SA from temperature of 100 and termnate at 0.1. The number of moves at a partcular temperature s 200x of the number of clusters n the crcut. After these moves, the temperature s decreased by a factor of Cluster MSSC calculaton The prmary objectve of MSSC calculaton s to search the nput vector space to dentfy the maxmum swtchng current value. The genetc algorthm(ga) based [9] and automatc test pattern generaton(atpg) based algorthm[10] have been developed for MSSC estmaton. We employ GA algorthm to calculate the MSSC for the entre module n ths paper. However, GA algorthm s neffcent to calculate MSSC for a large number of clusters. Therefore, we propose an effcent heurstc algorthm for cluster MSSC calculatons n ths secton. The reader who s only nterested n experments may skp secton 4.4. MSSC estmaton searches for the maxmum current value consderng both swtchng tme and nput vector. In order to smplfy the problem, we frst solve the MSSC estmaton problem at a fxed tme, that s, we frst estmate MSSC(c, t) based on a small number of random smulatons. For example, we want to estmate the maxmum current for the cluster of gates G1 to G7. We frst smulate the cluster for a number of random nput vectors. The swtchng actvtes at tme t for all gates n all smulatons can be encoded n a table shown n fgure 6, where 1 stands for swtchng and 0 means no swtchng. For example, row S1 (.e., smulaton S1) means that G1, G2 and G6 swtch whle G3, G4,G5orG7donotswtch. AlthoughG3,G4,G5and G7 never swtch smultaneously wth G1, G2 and G6 at S1, they may swtch smultaneously wth G1, G2 and G6 under 184

5 S1 S2 S3 S4 S30 S31 S32 S33 G1 G2 G3 G4 G5 G6 G G1G2G {G1G2G4, G1G4G6, G2G4G6} G2G4G G1G4G Fgure 6: Database contanng pre-smulatons for cluster MSSC other nput vectors. In ths case, the swtchng current at those nput vectors s larger than the one n S1. We want to capture ths potental and expand the lst of smultaneous swtchng gates as much as we can. We llustrate the dea of expandng smultaneous swtchng lsts by usng lst S1, n whch the smultaneous swtchng gates are G1, G2 and G6. Instead of checkng whether G4 can swtch smultaneously wth G1, G2 and G6, we check whether all the combnatons of three gates,.e., G1G2G4, G1G4G6 and G2G4G6 canswtchsmultaneously. Asshownnfgure6,G1G2G4, G2G4G6 and G1G4G6 do happen n S3, S30 and S33. Thus, G4 has a large potental to swtch smultaneously wth G1, G2 and G6. G4 s then set to be swtchng at S1 and the swtchng current of G4 s added nto the total swtchng current of S1. The swtchng lst for each smulaton s expanded untl no more expanson s possble. The maxmum current value among all the smulatons s MSSC(c, t). Overall, our method for cluster MSSC estmaton contans two phases. In the frst phase, we carry out a number of random smulatons and choose the tme (called peak tme) for the peak current of each smulaton. In the second phase, we apply the above MSSC(c, t) for every peak tme. 5. EXPERIMENT RESULTS 5.1 Gate level synthess All proposed algorthms have been mplemented nsde SIS[11] envronment. We use ISCAS benchmark crcuts and report experment results n Table 1. A gate-level smulator has also been mplemented to calculate voltages and current waveforms. Parameters needed to smulate a crcut, such as gate delay, loadng capactance, and swtchng current, are all extracted from SPICE smulatons and bult nto tables. Smulaton results from our smulator are wthn 20% dfference from SPICE smulatons, but t s much faster than the SPICE smulaton. Ths smulator was used to verfy the gate level synthess n ths sub-secton. We frst compare the area (.e., transstor wdth) used by DSTNand cluster-based desgn (CB-STD), respectvely. We measure area by the total channel wdth of transstors. One can see that DSTNuses sgnfcantly smaller area than CB-STD does. On average, the area reducton s 49.8%. Because we do not consder the delay constrant durng placement for CB-STD, we obtan a lower bound of the cluster MSSC n a tmng-drven placement and n turn a lower bound of the transstor area n CB-STD. Therefore, the area reducton by DSTNwould be larger compared to CB-STD f consderng practcal placement constrants. We then compare performance loss. We have used extensve random smulatons to verfy the qualty for both szng schemes. Specfcally, 10,000 random smulatons for each crcut have been conducted to calculate the maxmum PL (n short, MPL) for each crcut. For DSTN, the peak current for each module n each smulaton s appled to the resstance network as the current source. We compute the transstor channel resstance by (8), and use R = 10Ω and 50Ω for vrtual-ground wres. The resultng resstance network s solved by a sparse lnear equaton solver ntegrated wth SIS. The calculated voltages at tappng ponts are used to compute the performance loss va (3). Note that the resultng MPL value n Table 1 s an upper bound of MPL for the followng reasons: () the above R values are conservatve as dscussed n Secton 4.1. () the peak current for an ndvdual module normally happens at dfferent tmes, but we assume that all the peak current happens at the same tme n our experment. The same random smulatons have been appled to calculate MPL n CB-STD, where PL s calculated va (6). Although the peak current value s also used to calculate MPL, t wll not overestmate the PL because each module only dscharge from one transstor n CB-STD. Instead, gnorng the resstance of vrtual ground n CB-STD leads to a lower bound estmaton. As shown n Table 1, when R = 10Ω (a conservatve case as dscussed n Secton 4.1), MPL of DSTNs on average 10% smaller than that of CB-STD. When R = 50Ω,.e., an extreme worst-case scenaro as dscussed n Secton 4.1, MPL of DSTNs about 6% worse than CB-STD. However, R s normally 5 15 Ω n 100nm technology when the cluster sze s 6. Furthermore, the MPL presented n Table 1 s an upper bound of the real MPL n DSTN, and s a lower bound of the real MPL n CB-STD. Therefore, t s far to say that DSTNs better than CB-STD n terms of MPL. Note that MPL for both DSTN and CB-STD are larger than 5%, the PL bound n our experments. It s because the current values n a large number of random smulatons may be bgger than the estmated cluster MSSC. Ths underdesgn can be easly removed by scalng up the estmated MSSC. 5.2 Custom Layout Desgn The exact evaluaton of most parameters, such as PL and transstor area, can only be obtaned after a layout desgn. Therefore, we mplement and compare three layout desgns, transstor free(st-free) desgn, clusterbased transstor desgn(cb-std) and DSTN, for a 4- bt carry-lookahead(cla) adder. The three layout desgns are mplemented as follows. Frst, a ST-free layout, consstng of four sum modules and one CLA module, s mplemented. Then, a CB-STD layout s mplemented by parttonng each module nto 2-3 clusters and accommodatng each cluster by one transstor. Sleep transstor szes are determned by SPICE smulatons to keep PL below 5%. Fnally, we mplement a DSTNdesgn by accommodatng the entre CLA adder va sx dstrbuted transstors. All these transstors are connected 185

6 Table 1: Area and MPL for DSTN and CB-STD Crcut #Gate* #PI #PO Area (W/L) MPL(%) CB-STD DSTN Reducton CB-STD DSTN(upper bound) (%) (lower bound) R =10 R =50 C C C C C C C C C C Avg *Crcut gate number after mappng n SIS. together and have a same sze 2. As n the cluster-based desgn, szes of the transstors n DSTNare determned by SPICE smulatons to make PL below 5%. Propertes ST-free CB-STD DSTN Leakage(nA) Crtcal path delay(ns) ST area(µm 2 ) Chp area(µm 2 ) Table 2: Layout desgn comparson. As shown n Table 2, compared to the ST-free desgn, both CB-STD and DSTNacheve sgnfcant leakage current reducton but DSTNs approxmately fve tmes better than CB-STD. Both CB-STD and DSTNncrease the crtcal path delay but DSTNhas a much smaller delay than CB-STD. DSTNhas a transstor area several tmes smaller than CB-STD. These comparsons are consstent wth prevous theoretcal analyss and experment results. 6. CONCLUSION AND FUTURE WORK Sleep transstors are effectve to reduce both dynamc and leakage power. We have proposed a novel dstrbuted transstor network (DSTN), and have convncngly llustrated that DSTNhas reduced area, less supply voltage drop, and no conflct wth tmng-drven placement when compared to exstng module-based and cluster-based transstor structures. We have revealed several propertes of the optmal soluton to the DSTNszng problem, and have proposed an effectve and effcent DSTNszng algorthm based on these propertes. Based on the expermental comparson wth a rgorous cluster-based desgn, DSTN assumng conservatve vrtual-ground wres acheves on average 49.8% transstor area reducton and leads to less performance lost. Havng these advantages, DSTNcan be used to mplement power gatng for reducng dynamc and leakage power [12]. Sleep transstor can be vewed as an essental part of the power/ground network. We assume that the power/ground 2 Same sze s used because transstor area optmzaton technques for ndvdual transstors make lttle dfference n ths small crcut. network (both global and vrtual) s gven aprorn ths study, and plan to nvestgate the co-desgn of DSTNand power/ground network n the future. 7. REFERENCES [1] J. Kao, S. Narendra, and A. Chandrakasan, Subthreshold leakage modelng and reducton technques, n Proc. Int. Conf. on Computer Aded Desgn, pp , Nov [2] S.Mutah and et al., 1-v power supply hgh-speed dgtal crcut technology wth multthreshold-voltage cmos, IEEE Journal of Sold-State Crcuts, August [3] J. Kao, S. Narendra, and A. Chandrakasan, Mtcmos herarchcal szng based on mutual exclusve dscharge patterns, n DAC, [4] M. Ans, S. Areb, and M. Elmasry, Dynamc and leakage power reducton n MTCMOS crcuts usng an automated effcent gate clusterng technque, n DAC, [5] C. Long and L. He, Dstrbuted transstor network for power reducton, tech. rep., UCLA EE Dept., [6] T. Sakura and A. Newton, Alpha-power law MOSFET model and ts applcatons to CMOS nverter delay and other formulas, IEEE Journal of Sold-State Crcuts, vol. 25, pp , Aprl [7] Y.M.Jang,K.T.Cheng,andA.C.Deng, Estmatonof maxmum power supply nose for deep sub-mcron desgns, n IEEE Proc. Of Sym. On Low Power Electroncs and Desgn, pp , [8] X. D. Tan and C. J. Sh, Relablty-constraned area optmzaton of VLSI power/ground networks va sequence of lnear programmngs, n Proc. Desgn Automaton Conf, pp , [9] Y.M.Jang,K.T.Cheng,andA.Krstc, Estmatonof maxmum power and nstantaneous current usng a genetc algorthm, n Proc. IEEE Custom Integrated Crcuts Conf.., pp , May [10] A. Krstc and K. T. Cheng, Vector generaton for maxmum nstantaneous current through supply lnes for cmos crcuts, n Proc. Desgn Automaton Conf, pp , June [11] E. M. Sentovch, K. J. Sngh, L. Lavagno, and etc., Ss: a system for sequental crcut synthess, Memorandum NO. UCB/ERL M92/41, May [12] W. Lao and L. He, Leakage power modelng and reducton wth data retenton, n Proc.Int.Conf.on Computer Aded Desgn, pp ,