Gated Clock Routing Minimizing the Switched Capacitance *

Transcription

1 Gated Clock Routng Mnmzng the Swtched Capactance * Jaewon Oh and Massoud Pedram Dept. of Electrcal Engneerng Systems Unversty of Southern Calforna Los Angeles, CA 989 Tel: (3) e-mal: [oh, massoud]@zugros.usc.edu Abstract Ths paper presents a zero-skew gated clock routng technque for VLSI crcuts. The gated clock tree has maskng gates at the nternal nodes of the clock tree, whch are selectvely turned on and off by the gate control sgnals durng the actve and dle tmes of the crcut modules to reduce swtched capactance of the clock tree. Ths work extends the work of [4] so as to account for the swtched capactance and the area of the gate control sgnal routng. Varous tradeoffs between power and area for dfferent desgn optons and module actvtes are dscussed and detaled expermental results are presented. Introducton Clock gatng s an effectve way of reducng power dsspaton n dgtal crcuts. In a typcal synchronous crcut, e.g. a general purpose mcroprocessor, only a porton of the crcut s actve at any gven tme. By shuttng down the dle modules n the crcut, we can prevent the crcut consumng unnecessary power. In addton, we can shut down a porton of the clock tree by maskng off the clock at the nternal node of the tree usng an AND-gate. Ths prevents unnecessary swtchng n the clock tree and saves power n the clock tree n addton to the power savngs n the modules. In ths paper, we address an nstance of the gated clock routng problem. In our gated clock tree, we nsert gates mmedately after every nternal node of the clock tree to mnmze the dynamc power consumpton. These gates also serve as buffers and can be szed to adust the phase delay of the clock sgnal. They are turned on and off by the control sgnals generated from a centralzed gate controller. An nstance of the gated clock tree s shown n Fgure, where the snks correspond to the locatons of modules and the Steners are the nternal nodes of the clock tree. A gate n the clock tree must be enabled (.e. the control sgnal s true) whenever any of ts descendant gates are enabled. Ths suggests that the control sgnal of a gate s the OR functon of the control sgnals of ts descendant gates. * Ths research was funded n part by DARPA under contract no. F C67 and by NSF under contract no. MIP Controller source - snks - Steners clock tree edges gate control sgnals Fgure : Gated clock tree In [5], a gated clock tree topology constructon based on module actvty patterns was suggested. The authors used hgh-level synthess nformaton to extract the actvty patterns. However, the routng of the clock tree and the control sgnals, the actual power dsspaton and the area of them were not consdered. In contrast, our method consders all of these. In addton, we propose a method for clock tree constructon based on the nstructon statstcs of the processor. Ths can be extracted from nstructon level smulaton of the processor wth a number of benchmark programs. The nstructon statstcs are used to extract the actvtes of the nodes and the swtchng actvtes of the control sgnals as wll be dscussed n the followng sectons. More precsely, we wll nvestgate how the probablstc nformaton (nstructon statstcs) and the geometrcal nformaton (snk locatons) are used to gude the low power clock routng. The remander of ths paper s organzed as follows. Secton gves the termnology and the precse problem statement. Secton 3 descrbes how the probabltes of the gate control sgnals are calculated. Secton 4 presents the clock tree constructon algorthm. Sectons 5 and 6 show our expermental results and conclusons.

2 . Problem Defnton We assume that the topology of the clock tree s full bnary, that s, every non-leaf node has exactly two chldren. However, the tree s not necessarly a balanced tree (depth of leaf nodes may not be the same). Let T be the rooted clock tree topology. Let {M, M,,M N } be the modules. If there are N modules, there are N nternal nodes. Let {v, v,,v N- } be the nodes of the clock tree where {v, v,,v N } are leaves and the rest are nternal nodes of the tree. Let {e, e,,e N- } be the edges of the tree. We dentfy each pont v, except the root, of the rooted topology T wth edge e, so e connects v to ts parent n T. Let e be the length of edge e. We assume that the controller s located at the center of the chp. The control sgnal routng s a star routng as shown n Fgure. We denote the controller tree as S. We label each edge n the controller tree as EN. Edge EN controls the gate on edge e of the clock tree. The sgnal probablty of EN (probablty that EN s ) s denoted as P(EN ) and the transton probablty of EN (probablty that EN changes logc value per cycle) s denoted as P tr (EN ). Let EN be the length of edge EN.. Swtched Capactance of the c lock tree Consder a clock tree wthout gates. For a partcular edge e, the power dsspaton on the edge e s gven by power ( e ) = c e α f Vdd () where c, α, f, V dd are the unt wre capactance, transton probablty of the clock net, the clock frequency, and the supply voltage, respectvely. For the clock net, α = snce there s one rsng and one fallng edge n every clock cycle. So the above equaton becomes ( e ) c e f Vdd power = Wth the maskng gates, ths power s dsspated only when the control sgnal s on. Thus the power dsspaton n edge e s ( e ) c e P( EN ) f Vdd power = Durng the layout synthess step, V dd and f are fxed parameters, hence we can use the swtched capactance as an exact measure of the power dsspaton. The swtched capactance w(e ) of an edge e s gven by w e ) = c e P( EN ). ( There may be a load capactance assocated wth each node of the clock tree. Includng the node capactance C at node v, the swtched capactance of e s gven by w e ) = ( c e + C ) P( EN ). ( The total swtched capactance n the clock tree s therefore W ( T ) = ( c e + C ) P( EN ). e. Swtched capactance n the c ontroller tree Smlarly, from Equaton (), we can see the swtched capactance of edge EN s w EN) = ( c EN + C ) P ( EN ) ( g tr where C g s the nput capactance of the AND gate. The total swtched capactance n the controller tree s W S = c EN + C ) P ( EN ) ( ) ( EN The obectve of our gated clock routng s to fnd trees T and S so as to mnmze W = W ( T ) + W ( S) subect to zero skew constrants. Notce that the sgnal probablty of EN determnes the swtched capactance n the clock tree whereas ts transton probablty determnes the swtched capactance n the controller tree. 3. Computaton of P(EN ) and P tr (EN ) To calculate W(T) and W(S), we need to compute the sgnal probabltes P(EN ) and the transton probabltes P tr (EN ). Let P(M ) be the probablty that M s actve (.e. M receves the clock sgnal). Suppose v has modules M, M,,M l at the leaves. If any of these modules are actve, then EN must be turned on. Thus P(EN ) s gven by P EN ) = P( M M M ) () ( l To fnd P tr (EN ), we need the module actvaton statstc over consecutve clock cycles. Let AT(M ) be a two-bt actvaton tag whch represents the module actvtes n two consecutve clock cycles. For example, AT(M ) = means that M s dle n the current clock cycle and becomes actve n the next clock cycle. AT(M ) can have four possble values and ther correspondng logc value transtons of EN are shown below.. AT(M ) = (EN stays at ). AT(M ) = (EN makes a to transton) 3. AT(M ) = (EN makes a to transton) 4. AT(M ) = (EN stays at ) g tr

3 Cases and 4 do not cause transton of EN, so we ust need to consder cases and 3 for the computaton of the transton probablty. If Regster Transfer Level (RTL) smulaton s used to fnd these probabltes, a huge number of clock-by-clock module usages have to be recorded. Certanly, the tme complexty wll be very large, especally for general-purpose mcroprocessors. So we propose a method for computng actvtes usng more effcent nstructon level smulaton of the processor and knowledge about the RTL descrpton of the processor. 3. RTL descrpton For smplcty, we assume that the mcroprocessor has four nstructons and sx modules throughout the rest of ths secton. The RTL descrpton of each nstructon tells us what modules are used to execute each nstructon. For example, we may have the followng RTL descrpton of the nstructons. Instructon Used Modules I M, M, M 3, M 5 I M, M 4 I 3 M, M 5, M 6 I 4 M 3, M 4 Table : RTL descrpton of nstructons 3. Instructon stream By smulatng the processor at the nstructon level wth a number of benchmark programs, we can trace the nstructons that are executed. For example, our nstructon stream for clock cycles may be gven as follows. I I I 4 I I 3 I I I I I I 3 I I I 3 I I I I I 4 I From ths, we can fnd any probabltes by scannng the nstructon stream. For example, M appears n I and I, and these two nstructons occur 5 tmes n the stream, so P(M ) = 5/ =.75. If a node v n the clock tree has two leaf nodes M 5 and M 6, any nstructons that use ether of these modules should contrbute to the sgnal probablty of EN. I and I 3 are such nstructons, so P(EN ) = P(M 5 M 6 ) = / =.55. The transton probablty of ths EN s also found by scannng the nstructon stream. We examne every two consecutve nstructons durng the scannng and count the number of transtons of EN ( transton when both M 5 and M 6 are dle n the current clock cycle and any of M 5 and M 6 are actve n the next clock cycle; transton s the reverse of ths). We can see that P tr (EN ) = /9=.56 (there are 9 transtons). However, the nstructon stream can be very long. To get accurate nstructon statstcs, we may need some mllons of nstructons. Because some nstructons are rarely executed, the nstructon stream should be very long to get reasonable probablty value for the rare nstructons. Therefore, the above brute-force method s very expensve. To overcome ths problem, we propose a method that computes all the necessary probabltes from the tables that can be generated by scannng the nstructon stream ust once. 3.3 Table-drven probablty com putaton Instructon Frequency Table (IFT) enlsts the probablty that each nstructon s executed on the average. By scannng the prevous nstructon stream, we have the IFT n Table. Instructon I I I 3 I 4 Probablty Table : Instructon Frequency Table To fnd P(M 5 M 6 ), we smply add the two probabltes of I and I 3 n Table, whch s.55. Any sgnal probablty P(EN ) can be found usng Table and Table wthout rescannng the nstructon stream. It was shown n [4] that the tme complexty of computng ths probablty s O(KL), where K s the total number of nstructons and L s the maxmum number of used modules for any nstructons (K = L = 4 n our example). Instructon Transton-Module Actvaton Table (IMATT) enlsts AT(M ) for every possble combnaton of two consecutve nstructons. In addton, IMATT keeps the probablty that the two nstructons occur n two consecutve clock cycles. By scannng the prevous nstructon stream, we have IMATT n Table 3. Prob. Instr. M M M 3 M 4 M 5 M 6 Trns..57 I I.58 I I.58 I I 3.57 I I 4.84 I I.57 I I.. I 4 I 4 Table 3: Instructon Transton-Module Actvaton Table For example, I I 3 occurs three tmes n the nstructon stream. So ts probablty s 3/9 =.58. Assume that v has leaf nodes M, M,,M l. In order for EN to make a transton, at least one of AT(M k ), k=,,l should be whle the remanng AT(M k )s should be ether or. Lkewse, n order for EN to make a transton, at least one of AT(M k ), k=,,l should be whle the remanng AT(M k )s should be ether or. All other cases force EN to reman at or. Alternatvely, we perform logcal OR over all the AT(M k )s and f ts result s or, we have transtons on EN. For example, f v has leaf nodes M, M 3, M 5 and M 6, I I causes EN to make a transton snce the OR of the four correspondng table entres s. For each row n Table 3, f the correspondng modules actvaton tags cause EN to

4 make a transton, the probablty on that row should be added to the transton probablty of EN. The tme complexty of computng the transton probablty of EN s O(K N), where K s the total number of nstructons and N s the total number of modules. 4. Clock Tree Constructon 4. Delay modelng To estmate the phase delay of the clock tree, we use the Elmore delay model as was used n [6] for zero-skew clock routng. Insertng gates reduces the subtree capactance n the Elmore delay computaton, thereby reducng the phase delay. 4. Mnmum swtched capactan ce heurstc Bottom-up mergng followed by top-down placement method s commonly used n clock routng. In [], the mergng sector s a lne segment wth slope ±, whch represents the possble locatons of the Stener node where ts two subtrees are merged. These mergng sectors are found n bottom-up fashon. The actual locatons of the Stener nodes are determned n top-down fashon (see an example n Fgure ). The nearest-neghbor heurstc of [3] greedly merges two nodes when the geometrc dstance between the correspondng mergng sectors s mnmum. Our method s also greedy, but the mergng sequence s determned by the swtched capactance. source Stener Snk Mergngsectors Fgure : An example of bottom-up mergng sequence Let ms(v ) be the mergng sector of v. Suppose we try to merge (ms(v ), ms(v )) and the root of the merged tree s v k. We can unquely determne e, e such that the zero skew constrant s satsfed. As mentoned before, we assume that the gate controller s located at the center of the chp. Let ths center be CP. To compute the swtched capactance n an edge of the controller tree, we need to estmate the dstance between the gate locaton (locaton of the Stener node) and the CP. Snce we do not know the exact locatons of the Stener nodes durng the bottom-up phase, we approxmate the edge length of the controller tree as the dstance between the CP and the mddle pont of the mergng sector. Let ths dstance be dst(cp, md(ms(v ))). Then the swtched capactance SC after the merge of (ms(v ), ms(v )) s SC( v, v ) = ( c e + ( c + ( c + C ) P( EN ) + ( c dst( CP, md( ms( v )) + C dst( CP, md( ms( v e g )) + C + C ) P( EN ) g ) P tr ) P tr ( EN ( EN When we merge subtrees bottom-up, we merge sectors that result n the smallest swtched capactance as gven n Equaton (3). Detaled algorthm for the clock tree constructon s smlar to [4]. We summarze the algorthm outlne below (SC s short for swtched capactance). PROCEDURE GatedClockRoutng Input: Instructon Stream, RTL descrpton of each nstructon, Snk locatons; Output: Clock Tree Layout wth gates begn scan the nstructon stream and create IFT and ITMAT; fnd P(EN ) and P tr (EN ) for every snk; compute SC between every par of snks; // bottom-up merge repeat pck the par ms(v x ), ms(v y ) whose SC s mnmum create new node v k ; compute P(EN k ) and P tr (EN k ); fnd ms(v k ); remove node v x, v y ; for each remanng node v n determne e k, e n satsfyng zero-skew; compute SC between v k, v n ; end for untl only the root s left // top-down placement place nternal nodes v k wthn each ms(v k ); end PROCEDURE Scannng the nstructon stream and the creatng the tables take O(B), where B s the length of the stream. The second and the thrd statements take O(N (KL + K N)) and O(N ) respectvely. Snce L < N, the combned complexty s O(K N ). The repeat loop terates N tmes and wthn each teraton, the domnatng complexty s the probablty computaton whch takes O(K N). So the overall complexty s O(B + K N ). 4.3 Reducton of Gates Insertng gates at every node of the clock tree may result n large area and ncrease complexty of the control crcut and ) ) (3)

5 the routng of the enable sgnals. Especally, snce the routng of enable sgnals s a star routng, ts area can be bgger than the clock tree routng f we do not reduce the number of gates. There are cases when nsertng gates hardly reduces swtched capactance. We can thnk of three cases when a node does not need a gate.. Actvty of the node s close to,. Swtched capactance of the node s very small, 3. Actvty of the parent node s almost the same as actvty of the node. Case () s obvous snce there s no tme frame durng whch the node can be shut off. In case (), the node's swtched capactance s so small that havng a gate can only reduce swtched capactance margnally. In case (3), there s very lttle ncrease n actvty when we go up from the node to ts parent. In ths case, t s not necessary for both the node and ts parent to have gates. Only the parent wll have a gate, and the resultng swtched capactance s at most slghtly hgher than the case that both nodes have gates. However, these gate removal schemes may remove so many gates n the tree that the phase delay of the clock sgnal may ncrease rapdly. So we ncluded a rule for enforcng a gate nserton regardless of those three schemes whenever the subtree capactance of the node reaches, say C g, where C g s the nput capactance of a gate. 5. Expermental Results We mplemented our algorthm n C++ on a Sun Sparc workstatons. For snk locatons (module locatons) and the snk load capactance, we used the benchmarks r-r5 from [6]. The nstructon stream and the used modules for each nstructon are generated accordng to a probablstc model of the CPU when t executes typcal programs. The benchmark characterstcs are shown n Table 4. The length of the nstructon stream was thousands for all the benchmarks. The average number of used modules per nstructon s about 4% for all the benchmarks (ths can be seen n the column labeled Ave(M(I ))). That s, about 4% of the modules are actve at any gven tme on the average. Bench No. of snks No. of nstr Ave(M (I )) r r r r r Table 4: Benchmark characterstcs for gated clock routng 5. Buffered clock tree vs. gated clock tree Buffered clock tree s a commonly used method n current clock routng. The buffered clock tree s constructed usng the nearest neghbor heurstc and the sze of a buffer s assumed to be half the sze of AND-gates. The comparson among buffered clock tree, gated clock tree and gated clock tree wth gate reducton heurstc s shown n Fgure Swtched Capactance r r r3 r4 r5 Area r r r3 r4 r5 Fgure 3: Comparson among dfferent clock routng methods. Swtched capactance n pf, area n 6 λ As can be seen from the fgure, f the gate reducton heurstc s not appled, the gated clock routng s worse than the conventonal buffered clock routng. The maor overhead n swtched capactance and the area comes from the star routng. After the gate reducton, t consumes about 3% less power than the buffered clock routng. There s stll however an area overhead. 5. Impact of average module act vty Buffered Gated Gate Red. Buffered Gated Gate Red. If the average actvty s too hgh, then there s lttle room for power savngs. The average module actvty vs. swtched capactance s shown n Fgure 4. As the average module actvty ncreases, the power consumpton dfference between the two routng methods dmnshes. Thus the gated clock routng s more effectve when the module actvty s low. Note that the power consumpton of the gated clock tree wll be at least 4% of the ungated clock tree as a result.

6 Gate Red. Buffered Our expermental results showed that there s an optmum number of gates for lowest swtched capactance. Our results help a desgner choose trade-off among the power, area and the complexty of the routng. In ths paper, we assumed a centralzed gate controller. However we are also nvestgatng a dstrbuted controller for reduced star routng area. Ths s llustrated n Fgure 6. Fgure 4: Average module actvty (x-axs) vs. swtched capactance (y-axs) for benchmark r 5.3 Optmum number of gates If there are a lot of gates, then the swtched capactance n the clock tree s reduced, but the swtched capactance and the area of the controller tree s ncreased. On the contrary, f there are too few gates, the swtched capactance n the clock tree wll be ncreased. Intutvely, there wll be an optmum number of gates that mnmzes the total swtched capactance. Ths s shown n Fgure Swtched Capactance gate reducton (%) Fgure 5: Gate reducton vs. swtched capactance and area for benchmark r We controlled the number of gates by gvng dfferent parameters n the gate reducton heurstc. When there are many gates, the controller tree domnates the swtched capactance and the area. As the number of gates s reduced, the swtched capactance n the controller tree s reduced but that of the clock tree s ncreased. In the fgure, the optmum gate reducton for lowest power s at 55%. 6. Concluson 5 5 Controller tree Clock tree Area gate reducton (%) We presented a gated clock routng whch has lower swtched capactance over buffered clock trees. We presented a clock topology generaton heurstc based on the module actvtes and the snk locatons. We proposed a method to fnd the sgnal probablty and the transton probablty of the gate control sgnals from the tables generated from the nstructon stream. (a) Fgure 6: (a) one centralzed controller vs. (b) four dstrbuted controllers Assume that the chp s square and ts sde s of length D. Then the longest edge length of the star tree s D/. Assumng the average edge length s half of ths (D/4), the total routng area s GD/4 where G s the number of gates. If we dvde the chp nto k equal szed parttons (where k s power of two), then each partton has G/k gates and the average edge length s D / 4 k. Therefore the total routng area s G D GD k = k 4 k 4 k As the number of partton ncreases, the star routng area s reduced by a factor of k. Feasblty of the dstrbuted controllers and ther mpact on the desgn complexty of the controller logc n currently under nvestgaton. References [] Mazhar Aldna, José Montero, Srnvas Devadas, Abht Ghosh, Maros Papaefthymou, Precomputaton-Based Sequental Logc Optmzaton for Low Power, IEEE Transactons on VLSI Systems, vol., no. 4, pp , December, 994. [] Kenneth D. Boese and Adrew B. Kahng, Zero-Skew Clock Routng Trees Wth Mnmum Wrelength, Proc. IEEE Internatonal Conference on ASIC, pp , 99. [3] M. Edahro, Mnmum Path-Length Equ-Dstance Routng, Proc. IEEE Asa-Pacfc Conf. on Crcuts and Systems, pp. 4-46, 99. [4] Jaewon Oh and Massoud Pedram, Power Reducton n Mcroprocessor Chps by Gated Clock Routng, to appear n Asa and South Pacfc Desgn Automaton Conference, 998. [5] Gustavo E. Téllez, Amr Farrah, Mad Sarrafzadeh, Actvty Drven Clock Desgn for Low Power Crcuts, Proc. Internatonal Conference on Computer-Aded Desgn, pp. 6-65, 995. [6] R-S Tsay, Exact zero skew, Internatonal Conference on Computer- Aded Desgn, pp , 99. (b)