RT Level Power Analysis y. Jianwen Zhu, Poonam Agrawal, Daniel D. Gajski. components [La94]. its simplicity.

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1 RT Level Power Analyss y Janwen Zhu, Poonam Agrawal, Danel D. Gajsk Department of Informaton and omputer Scence Unversty of alforna, Irvne, A Abstract Elevatng power estmaton to archtectural and behavoral level s essental for desgn exploraton beyond logc level. In contrast wth purely statstcal approach, an analytcal model s presented to estmate the power consumpton n datapath and controller for a gven RT level desgn. Expermental result shows that order of magntude speed-up over low level tools as well as satsfactory accuracy can be acheved. Ths work can also serve as the bass for behavoral level estmaton tool. 1 Introducton Wth the ncreasng demand of low power applcatons, there s a growng nterest n power estmaton technques. It s essental for the power optmzaton tools n that t provdes the evaluaton of the cost functon, t helps to dentfy the \hot-spots" { the canddates for further optmzaton. Power estmaton tools can operate on derent levels of abstracton. A lot of nterestng work has been done on crcut and gate level [Na94]. Whle these tools can often acheve very hgh accuracy, they are prohbtvely expensve n archtecture exploraton, whch s beleved to be able to brng most of the power reducton. It s thus desrable to have estmator operatng on RT level n order to provde fast evaluaton of the power metrc wthout sacrcng too much accuracy. Some related work at ths level nclude [La94] [Me94]. In contrast wth those purely statstcal approach, we present n ths paper a power analyss technque whch s analytcal n nature. The rest of the paper s organzed n a bottom-up fashon. In Secton 2, the power model of datapath components as well as nterconnectons s dscussed. Then we present the power analyss technques at the RT level n Secton 3. We conclude the paper wth some expermental results. 2 omponent Level Power Analyss In ths secton, we try to dentfy the sources of power consumpton for the components n the datapath lbrary as well as the nterconnectons such as buses and clock trees. Havng dented the sources of power dsspaton for the gates, we need to nvestgate the power consumpton model at the component level. In other words, we need to know the capactance swtched durng each access of the functonal unts, regsters, and bus drvers. Ideally, the energy consumed for each access of a component should be a functon of ts (1) btwdth, (2) ts prevous data, whch determne the prevous states of all the nternal crcut nodes, (3) the current data, whch determne the current states of all the crcut nodes and n turn ther swtchng actvtes. Ths s not practcal snce the data s not avalable untl run tme. However, statstcs measures such as mean, varance, and correlaton on the nput data are relatvely easy to obtan through functonal smulaton. It s reasonable to expect that the energy of the component s a functon of the statstcs of the data and the btwdth. Based on ths dea, omponent characterzaton technques such as Dual Bt Model (DBT) are proposed to model the power consumpton of datapath components [La94]. An alternatve s to assume unform whte nose nputs for each component. Based on ths assumpton, the power consumpton of a component depends solely on ts sze. Statstcal methods can be appled to obtan an average value for each component n the lbrary. We adopt ths approach because of ts smplcty. In the dscussons that follow, we assume each component c n the datapath lbrary s assocated wth a capactance, the value of whch s dened as the average capactance swtched for each access of the component. Power Model of Interconnectons Strctly speakng, the power model for the bus and clock tree belongs to the subject of next secton because they all depends on the RT level netlst. However, we advance t here for ease of dscusson. Power Model of Statc MOS Gates Three man sources of power dsspaton n statc MOS crcut are dynamc swtchng, leakage current and short crcut current respectvely. The domnant factor s the rst one due to the chargng or dschargng of crcut capactances. Power Model of Datapath omponents (+) + ( ) * * (drv) o (reg) + w Input Bus Output Bus y Ths work s partally supported by Toshba Inc. Fgure 1: apactances of Multplexed Bus

2 There are two factors that contrbute to the capactance of the bus: wre capactance, as ndcated by w n Fgure 1. The wre capactance s determned by the length of the wre and n turn the result of routng. Estmaton of wre length can be one of the followng: 1. performng detaled placement and routng; 2. performng rough oorplanng, and then use the square root of the resultant chp area as an approxmaton of the wre length; 3. summng up the area of all the components as an approxmaton of the chp area (assume the oorplaner s perfect), and then use the square root of the chp area. Whle 1 s too expensve to be practcal and 2 needs an addtonal oorplaner, 3 s adopted for ts smplcty. component load: the component load refers to the capactances contrbuted by the unts attached to the bus. There are two types of buses: 1. Multplexed Bus: As shown n Fgure 1, bus drvers are used for multplexed bus. For every data transfer bound to the bus, the capactances ntroduced are: (1) the output capactance of the bus drver ( o(drv)), (2) the nput capactance of the functonal unts for nput buses (lke (+); (3)), or the nput capactance of the regster for output buses ( (Reg)). 2. Drect onnecton: (reg) (reg) o ( + ) (+) o Input Bus Output Bus (reg) Fgure 2: apactances of Drect onnecton Bus As shown n Fgure 2, for drect connecton bus, there s no need for bus drvers. For every data transfer bound to the bus, the capactance ntroduced are: (1) the output capactance of the source functonal unt or regster (lke o(+) or o(reg)), (2) the nput capactance of the snk functonal unt or regster ( (+) and (Reg)). Smlarly, the capactance of the clock tree s the wre capactance plus the capactance of the clock nput clk(reg) of each regster. Same technque can be appled: (lock) =(w+ clk (Reg)) 1jRegj where Reg s the set of regsters n the desgn. 3 RT Level Power Analyss 3.1 Overvew Problem Statement Ths secton addresses the problem of estmatng power at the RT level, whch mples that the followng s known: 1. RT Level Descrpton A regster transfer level desgn can be convenently speced by a state acton table (SAT), each row of whch ndcates that at a partcular state, under a partcular condton, the system wll evolve to another gven state, and the datpath wll perform some gven computaton. A formal denton of the state acton table wll be gven n Secton Branchng Probablty: Gven a state acton table, the executon sequence of the system s stll not known due to the unavalablty of the condtons. We assume some prolng technques are appled pror to the power analyss so that for each par of rows (; j) n the state acton table, a branchng probablty Prob(; j) s obtaned. A more detaled treatment wll be presented n Secton omponent apactance: Based on dscussons n Secton 2, for every component n the datapath lbrary, we assume that the average capactance swtched for each access s known. In other words, the average capactance of each bus drver can be wrtten as (Drv), each regster can be wrtten as (Reg), and each functonal unt FU can be wrtten as (FU ). We also assume the nput and output capactances of each component are known. For nterconnectons such as bus and clock tree, although accurate nformaton s not known untl the layout stage, we assume some area estmaton technques dscussed n Secton 2 are appled such that for each bus Bus,we know the average capactance swtched for each access, denoted as (Bus ). Smlarly, the capactance of the clock tree can be denoted as (lock). Wth the above nformaton gven, we need to estmate the power consumpton of the hardware, whch s dened as Energy Power = ycles 2 lock P erod where ycles s the total number of clock cycles. Archtectural Model In general, dgtal hardware can be modeled as an FSMD (Fnte State Machne wth a Datapath), where the datapath s responsble for the computaton, and the controller determnes when and what computaton wll be performed [Ga92]. Datapath A typcal datapath s shown n Fgure 3. The datapath conssts of functonal unts, regsters, and buses (nterconnectons). The bus may or may not be attached wth a bus drver dependng upon whether t has derent sources. We omt the case of multplexers snce they can be treated as bus drvers. (1)

3 Functonal Unt Bus * + Bus Drver Fgure 3: Datapath Model Because the applcatons concerned n ths work are often power crtcal, we assume another desgn style called dynamc power management, whch s frequently adopted by desgners (Fgure 4): we assume each functonal unt has an enable nput n order to shut down the unt durng ts nactvty. The enable crcutry can be mplemented smply as a swtch whch separates the bus and the functonal unt. The enable controls the on/o of the swtch. Note that n order for ths technque to take eect, desgn care has to be exercsed to ensure that the enable sgnal s asserted before the change of regster output. Enable Enable Functonal Unt Fgure 4: Functonal Unt wth Enable Input ontroller ontroller mplements a nte state machne. In general, t contans a state regster, whch stores the current state, as well as some control logc to compute the next state and output sgnals. ontrol logc can be mplemented ether as (a)rom, or (b)pla, or (c)2-level random logc, or (d)mult-level random logc. Whle mult-level logc mplementaton s very dcult to predct, the analyss of the rest s smlar and relatvely smple. We take (c) as a representatve of (a), (b), (c) and an approxmaton of (d) n ths paper. A typcal 2-level logc controller mplementaton s shown n Fgure 5. As shown n Fgure 5, A typcal controller s composed of four parts, namely, the state regster, the decoder, next state logc and output logc. The decoder s mplemented as a set of AND-gates. It takes as nputs each bt of the state regster and the status sgnals as well as ther complements. The next state logc and output logc s mplemented as a set of OR-gates. It take as nput the output of the state decoder. There are three types of control lnes n the output logc: (1) control lnes for loadng regsters, (2) control lnes for enablng (shuttng down) the functonal unts, (3) control lnes for the bus drvers. Based on the structure of the hardware, computaton of the energy consumpton can be decomposed nto Energy = E(Datapath)+E(ontroller) +E(lock) where and E(Datapath) =E(FU)+E(Reg)+E(Bus) E(ontroller)=E(SR)+E(NS)+E(Decoder) + E(OutputLogc) 3.2 Formal Denton of State Acton Table In ths secton we ntroduce some notatons as well as a formal denton of the state acton table. An actvty vector V ~ =(v 1;v 2; :::) s dened as a boolean vector wth v 2f0;1g. At a partcular state, the state of the hardware can be characterzed by a set of actvty vectors, namely, the current state vector S, ~ the status vector, ~ the next state vector NS, ~ the functon unt vector FU, ~ the the regster vector Reg, ~ the the bus vector Bus, ~ the the bus drver vector Drv. ~ Whle S; ~ ; ~ NS ~ ndcates the value of the state regster, status sgnals and next state sgnals, the value of FU; ~ Reg; ~ Bus; ~ Drv ~ ndcates the actveness of correspondng datapath components. The cardnalty of the vector V ~ s dened as the total number of 1's of the vector: j ~ V j = For V ~ =(v 1;v 2; :::; v n) and W ~ =(w 1;w 2; :::; w n), ther exclusve ors dened as ~V 8 W ~ =(v 1 8w 1 ;v 2 8w 2 ; :::) ther concatenaton s dened as ~V # W ~ =(v 1 ;v 2 ; :::; vn;w 1 ;w 2 ; :::; wn) The state tuple ~t can then be dened as the concatenaton of the above actvty vectors. n =1 ~t = ~ S# ~ # ~ NS# ~ FU# ~ Reg# ~ Bus# ~ Drv The behavor of a RT level desgn can be speced by the state acton table SAT, dened as a set of dstnct state tuples: SAT = f~t g A state trace ST of SAT s dened as a sequence of state tuples n SAT: ST =[~t 1 ;~t 2 ; :::; ~tn] such that the next state vector of ~t equals to the current state vector of ~t +1. Note that the state acton table denes the behavor of the hardware, whereas the state trace denes an actual executon scenaro of the hardware. In the next two sectons, we rst dscuss the computaton of power consumpton for an executon sequence n Secton 3.3, based on whch we derve estmaton technques for power consumpton drectly from the state acton table n Secton 3.4. v

4 3.3 Power Estmaton from State Trace Ths secton presents the analyss of power f a state trace ST =[~t 1;~t 2; :::;~t n] of the state acton table SAT s gven ycles The number of cycles of the state trace ST s smply the number of state tuples n ST: It follows that ycles = jstj = n (2) E(lock)=2 2 (lock) 2 V 2 DD 2 ycles =2 2 (lock) 2 VDD 2 2jSTj (3) where the factor 2 accounts for the swtches of both the fallng and rsng edges of the clock Datapath The actvty of the datapath at state ~t can be characterzed by the correspondng actvty vectors: FU, ~ Reg ~, Bus ~, and Drv ~.We denote ther concatenaton as DP ~ : DP ~ = FU ~ # Reg ~ # Bus ~ # Drv ~ The capactances of all the functonal unts n the datapath forms a capactance vector ~ FU =((FU 1);(FU 2); :::). Smlarly, we can dene the capactance vectors for regsters, buses, and bus drvers as ~ Reg; ~ Bus and ~ Drv respectvely. We denote ther concatenaton as ~ DP : ~ DP = ~ FU # ~ Reg # ~ Bus # ~ Drv So the energy consumed at state ~t s E(~t )=( ~ DP 1 ~ DP ) 2 V 2 DD where j:j stands for the dot product of two vectors. It follows that the total energy consumed on the executon sequence can be computed as E(Datapath) = ontroller General Model ~t 2ST ( DP ~ 1 ~ DP ) 2 VDD 2 (4) Fgure 5 shows the controller mplementaton. The controller falls naturally nto four parts, namely, the state regster, the decoder, the next state logc, and the output logc. The decoder s essentally a set of AND-gates, nputs of whch are connected to the output of the state regster and the status sgnals. Note that each nput s ndcated as a dot n Fgure 5 and ntroduces a capactance load ( And) for the state regster output. The next state logc and the output logc are essentally a set of OR-gates, nputs of whch are outputs of the decoder. Agan, each nput s ndcated as a dot n Fgure 5 and wll ntroduce a capactance load ( Or) for the AND-gates of the decoder. The dots n next state logc and output logc forms two matrces: next state matrx and output logc matrx. The rows of the matrces correspond to the decoder outputs, whch n turn correspond to a state tuple n the state acton table. The ~t S ~ ~ NS ~ D ~ O ~ ~t ~t ~t ~t ~t ~t ~t ~t Fgure 6: The Actvty Vectors columns of the matrces correspond to the next state sgnals and output sgnals respectvely. The role of the dots n power analyss of the controller s two-fold: (1) Snce each dot ntroduces a capactance of sze Or, the number of dots along each row gves the total load of correspondng state decoder AND-gate. (2) The dots along each column ndcates a true value of the correspondng sgnal. Note that dstrbuton of the dots at each row correspond exactly to the value of the state tuple n the state acton table. The actvty of the controller at state ~t can be characterzed by a set of actvty vectors, namely the current state vector S ~, the next state vector NS ~ ; the decoder vector D ~ ; and the output vector O ~. Each actvty vector correspond to the output of state regster, status sgnals, next state logc, decoder and output logc respectvely. Fgure 6 shows the values of these vectors at each state for the example shown n Fgure 5. It s obvous that ~O = ~ FU# ~ Reg# ~ Drv Each bt of the actvty vector V ~ (could be one of ~S; NS; ~ D; ~ O) ~ s assocated wth a capactance. The capactances for all the bts also form a capactance vector, denoted as ~ L =( L0; L1; :::). The energy consumed at state can then be measured as ( V ~ 8 V +1) ~ 1 ~ L 2 V 2 DD The total energy consumed for the entre state trace on ths vector can be computed as ~t 2ST ( ~ V 8 ~ V +1 ) 1 ~ L 2 V 2 DD Based on ths model, we wll dentfy the capactance vector as well as actvty vector for each part of the controller. State and Next State Logc Snce for ~t ;~t +1 2 ST, we always have NS ~ = S ~ +1. The swtchng actvtes of the state vector and next state vector are the same, so we treat them together. The capactance of each bt of the state regster conssts of ts (1) nternal capactances and (2) the output loads due to ts fanout to the state decoder. The capactance of each bt of the next state logc s the nput capactance of the state regster. The capactances mentoned above are the same for each bt, so we denote ther sum as Reg, and the correspondng capactance vector becomes Reg 2 I, ~ where I ~ =(1;1; :::; 1) s the unt vector. the total energy consumpton of the state regster and next state logc can then be computed as E(SR)+E(NS)= Reg 2 V 2 DD 2 8~t 2ST (( ~ S 8 ~ NS ) 1 ~ I)

5 Decoder S 1 S 1 S 0 S D Next State Logc Or Output Logc dot And S State NS Or LoadRegs EnableFUs EnableDrvers O Decoder = Reg 2 V 2 DD 2 8~t 2ST Fgure 5: ontroller j ~ S 8 ~ NS j (5) The swtchng actvty of the decoder s elegantly smple to analyze. At every state ~t 2 ST, only the output of correspondng AND-gate s 1. In other words, at every state, exactly two AND-gates wll swtch: The gate corresponds to prevous state wll swtch from 1 to 0; the gate corresponds to current state wll swtch from 0 to 1, and the rest of the gates wll reman unchanged. The capactance of each AND-gate n the state decoder s determned by ts fanout, that s, how many dots along the row n Fgure 5. If we assume each nput of the OR-gates ntroduces the same capactances as Or, the th bt of the capactance vector ~ L can be computed as #dots(row )2 Or, where #dots(row ) can be computed as j NS ~ # O ~ j. Due to the \one-hot" property of the actvty vector D, the energy consumed on the decoder can then be computed by countng the number of dots along the rows. E(Decoder) =22 Or 2 V 2 DD 2 Output Logc 8~t 2ST j NS ~ # O ~ j (6) The actvty vector of the output logc s O ~ = FU ~ # Reg ~ # Drv ~.Ifwedenote the capactance vector as ~ O, then the energy consumed on the output logc s: Energy(OutputLogc) =V 2 DD 2 ~t 2ST 3.4 RT Level Power Estmaton ( ~ O 8 ~ O +1 ) 1 ~ O (7) Branchng Probablty and Executon Frequency In the prevous secton, we develop a set of formula for power estmaton of a state trace. However, the state trace nformaton s not avalable n general. We resort to prolng technques to obtan branchng probablty functon Prob(; j) dened for every par of tuples (~t ;~t j) n the state acton table SAT. The executon frequency of a state tuple n SAT s dened as the expected number of tmes the state tuple wll be executed. The executon frequency can be obtaned ether from the prolng tool or drectly from the branchng probablty functon. Gven the branchng probablty functon, the determnaton of executon frequency of each state tuple can be formulated as solvng a set of lnear equatons wth the form Freq(~t j )= 8 Freq(~t )2Prob(; j) for 8~t j 2 SAT. Soluton can then be obtaned through standard procedures such as Gaussan elmnaton or LU factorzaton. Formula The formula developed n the prevous secton can then be rewrtten by nspectng the state tuples n SAT one by one. In other words, the power metrcs can be measured as the sum of the correspondng metrcs of all the state tuples weghted by ther executon frequences. ycles= Freq(~t ) (8) E(lock)=2 2 (lock) 2 VDD 2 2 ycles (9) E(Datapath)=V 2 DD 2 E(SR)+E(NS)= Reg 2 V 2 DD 2 Freq(~t )2 ( DP ~ 1 ~ DP ) (10) ~t j 2SAT Freq(~t )2 Prob(; j) 2j ~ S 8 ~ S j j (11)

6 E(Decoder)=2 2 Or 2 V 2 DD 2 E(OutputLogc)=V 2 DD 2 Freq(~t )2j ~ NS # ~ O j (12) Freq(~t )2 ~t j 2SAT Prob(; j) 2 (( ~ O 8 ~ O j ) 1 ~ O ) (13) 4 Expermental Results Behavoral VHDL Descrpton VHDL Descrpton of omponents tables show the estmated swtched capactance for derent classes of components (such as the functonal unts (FU), regsters (Reg), buses (Bus), bus drvers (Drv), clock (lk), state regster (SR), next state logc (NS), decoder (Dec), output logc (Output) ), the total estmated swtched capactance, the measured swtched capactance, and the error computed as jmeasured0estmatedj measured. The rows of the tables correspond to derent benchmarks. 5 onclusons The descrbed power estmaton technque whch s statstcal n nature at the component level, and analytcal at the RT level, oers fast feedback for hgh level exploraton tools. Experments on standard benchmarks show that the average error of the datapath s 5% and the controller s 7%. Our future work wll extend ths technque to the behavoral level. Manual Desgn RT Netlst Archtectural Power Analyzer netlst power profle ompass Syntheszer RT omp. Lbrary hp ompler omponet Power Profler FU Reg Bus Drv lk Total Measured Err HAL % DT % SRA % ELL % Table 1: Swtched apactance of the Datapath SR,NS Dec Output lk Total Measured Err HAL % DT % SRA % ELL % netlst Table 2: Swtched apactance of the ontroller total power Manual omparson Extractor Logc Smulator total power netlst annotated wth capactances Fgure 7: Block Dagram of the Experment In order to evaluate the estmaton tool, we appled t to a set of well known benchmarks [HW92]. Fgure 7 shows the block dagram of the experment. The component lbrary was bult by feedng functonal VHDL descrpton of each component to OMPASS ASI Syntheszer. The syntheszed components were then fed nto the component power proler [Ag95] to obtan an average power for each component. The average component power was stored n the lbrary. The RT level desgn of each benchmark was manually syntheszed from behavoral VHDL descrpton. Assumng archtectural model n Secton 3.1, the power estmaton of each benchmark was obtaned by applyng equatons 8-13 n Secton 3.4. We are able to obtan the average power of each benchmark n a couple of seconds on a Sparc 5 staton. The RT level VHDL descrpton of each benchmark nstantatng the components n the same lbrary was also fed nto the OMPASS chp compler to obtan the layout. Netlsts annotated wth node capactances were then extracted from the layout. Logc smulaton assumng random nput was nvoked to obtan the total swtched capactances. We compare the estmated results of datapath and controller wth the measured results obtaned from the layout n Table 1 and Table 2 respectvely. The columns of the 6 References [Ag95] P. Agrawal, D. Gajsk, F. Kurdah, \omponent Power Proler (PP)", TR-IS-95-x, U, Irvne [Ga92] D. Gajsk, N. Dutt, A. Wu, S. Ln, Hgh Level Synthess: Introducton to hp and System Desgn, Kluwer, 1992 [Ga94] D. Gajsk, F. Vahd, S. Narayan, J. Gong, Speccaton and Desgn of Embedded Systems, Prentce Hall, 1994 [Go93] J. Gong, D. Gajsk, S. Narayan, \Software Estmaton from Executable Speccatons", TR-IS- 93-5, U, Irvne [HW92] Benchmarks for the Sxth Internatonal Workshop on Hgh-Level Synthess, [La94] P. Landman, J. Rabaey, \Black-Box apactance Models for Archtectural Power Analyss", Internatonal Workshop on Low Power Desgn, Napa Valley, A, Aprl 1994 [Me94] R. Mehra, J. Rabaey, \Behavoral Level Power Estmaton and Exploraton", Internatonal Workshop on Low Power Desgn, Napa Valley, A, Aprl 1994 [Na94] F. Najm, \A Survey of Power Estmaton Technques n VLSI rcuts", IEEE Transacton on VLSI Systems, pp , Dec., 1994, [Na95] F. Najm, \Feedback, orrelaton, and Delay oncerns n the Power Estmaton of VLSI rcuts", Proceedngs of the Desgn Automaton onference, pp , 1995 [We93] N. H.E. Weste, K. Eshraghan, Prncples of MOS VLSI Desgn: A System Perspectve, Second Edton, Addson-Wesley, 1993