Effective Power Optimization combining Placement, Sizing, and Multi-Vt techniques

Transcription

1 Effectve Power Optmzaton combnng Placement, Szng, and Mult-Vt technques Tao Luo, Davd Newmark*, and Davd Z Pan Department of Electrcal and Computer Engneerng, Unversty of Texas at Austn *Advanced Mcro Devces, INC. 1

2 Overvew Introducton Power dsspaton ncreases dramatcally» As the technology scales down. To maxmze the power reducton» We combne placement, gate szng, and mult-vt technques» How to ntegrate technques wth dsont obectves? The proposed methodology Integrate placement, gate szng and Vt-swappng Lnear Programmng based placement for power Geometrc Programmng based gate szng for power» Gate szng on crtcal paths» Gate szng on non-crtcal paths Expermental results Conclusons 2

3 Power Consumpton Trend Dynamc power stll domnates The percentage of the leakage power ncreases as technology scales down Sw tchng 32% Leakge 36.00% Internal 32% AMD 65 nm Source: Synopsys, Inc. 3

4 Power Optmzaton Technques Power optmzaton technques P swtch P leak = α f C L V DD 2 k w α : swtchng factor f : frequency C L : capactve load k : parameter for leakage W : sze of gate Placement Dual-Vdd Mult-Vt α f C L V DD 2 k w Clock gatng Gate szng 4

5 Maxmze the Power Reducton Physcal synthess technques that affect the power Placement» Reduce the length of nets wth hgh swtchng rate Gate szng» Choose the mnmum gate szes satsfyng the tmng constrants Vt swappng:» LowVt (LVT) s used to close tmng on crtcal paths» HghVt (HVT) s used to reduce leakage on noncrtcal paths» RegularVt (RVT) for other cells. 5

6 Maxmze the Power Reducton How to ntegrate above technques to maxmze the power reducton? Tmng and power are often conflct obectves Those technques can be used for ether tmng and power Above technques affect each other» Usng smaller gate szes mproves the power but ncreases the delay.» HVT reduces the power but hurts the tmng.» We can use large gate szes and less LVTs, or smaller gate szes and more LVTs, etc. 6

7 Improve the Slack Dstrbuton Vt swappng s the most effectve technque for leakage reducton Usng hgh threshold voltage has exponental savng on leakage» Leakage current s exponental to Vt, and lnear to gate sze AMD 65-nm cell LVT RVT HVT Delay Leakage We may use gate szng to help Vt-swappng 7

8 Improve the Slack Dstrbuton The effectveness of Vt-swappng reles on the slack profle. Integrate those technques through the slack profle management Placement and gate szng are formulated to mprove the slack profle» For more effectve Vt swappng fnally» use more HVTs and less LVTs overall Slack dstrbuton Orgnal Optmzed 250 num gates slack 8

9 9 Lnear Program formulaton Varables: cell coordnates Delay models W H y y x x Cpn L c Cap b t l r L k pn y b pn y t pn x r pn x l = = = 1,2,.., ),, ( ), ( ), ( ), ( I I Cap u Slew u sp Sp Cap a Slew a dp Dp = =

10 LP based Power Aware Placement Select a set of crtcal paths Lnear program to mnmze the sum of weghted nets. Two maor components on net weghts» The tmng weght s based on the delay senstvty of the net.» The power weght s based on nets swtchng factor mn wt wt wt t p = βwt p wt L Selected = a2 = 0.5α F V a1 1 2 u2 crtcal (1 β ) wt t nets 10

11 Geometrc Programmng (GP) Prelmnary Statc tmng analyss AAT = max{aat 1, AAT 2 }D RAT = mn { RAT 3 -D 3, RAT 4 -D 4 } D = d h /W W : the sze of gate RAT 3 AAT AAT 2 AAT 2 RAT RAT

12 GP based Gate Szng for Near Crtcal Cells Effort based delay models For crtcal and near crtcal cells Maxmze the sum of slack on crtcal prmary outputs Increase the sze of crtcal cells and push the slack of near crtcal cells to be more postve, but not larger than a threshold. 12

13 GP Gate Szng for Non-Crtcal Cells Szng down cells wth large slacks drectly s. t. mn ( ΔPg AT max{( T cycle / ΔW ) T threshold ), AT NC org }, PO Addtonal constrants Short-crcut power constrant,» Short crcut power could be large f not properly controlled Pow er S7 I 5 short S5 S3 0 Output cap Input slew S1 1 2 Maxmum slew constrant Effectve fan-out constrant (control the nose) Otput cap Delay 1 S1 S S S S5 Input slew

14 The Overall Flow Intal desgn database No Crtal path placement opt. Legalze No mprovement? Slack mproved? Yes No Dscard Yes Keep Crtcal path gate szng opt. Yes Slack mproved? No non-crtcal gate szng opt. Tmng Analyss after each step Pre-routng est. Parastc est. Prmetme Tmng Vth swappng opt. Updatng tmng nto desgn database Ext 14

15 Expermental Results 15

16 Leakage Power Breaks Down Leakage power consumpton before and after optmzaton Leakage s reduced effectvely 100% 100% 90% 80% 80% 70% 60% 60% 50% 40% 40% 30% 20% 20% 10% 0% 0% ckt1 ckt2 ckt3 ckt4 ckt5 ckt6 ckt7 ckt8 ckt1 ckt2 ckt3 ckt4 ckt5 ckt6 ckt7 ckt8 Orgnal Dynamc Leakage Post optmzaton 16

17 Vt Percentages and Runtme Use a few low Vt cells only 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% ckt1 ckt2 ckt3 ckt4 ckt5 ckt6 ckt7 ckt8 LVT RVT HVT 17

18 Conclusons We propose the methodology to ntegrate several physcal synthess technques To maxmze the leakage and total power reducton through the slack profle management. Our LP based placement and GP based gate szng algorthms maxmze the effectveness of the mult-vt swappng technque for power reducton. Varous practcal desgn constrants are ncluded n our formulaton Short crcut power s not gnorable Our proposed method s very effectve Acheved 63.8% leakage power reducton and 32.8% overall power reducton on 65nm mcroprocessor crcuts. 18