Statistical Leakage and Timing Optimization for Submicron Process Variation

Transcription

1 Statstcal Leakage and Tmng Optmzaton for Submcron Process araton Yuanln Lu and shwan. grawal uburn Unversty epartment of Electrcal and omputer Engneerng uburn, L 36849, US luyuanl@auburn.edu, vagrawal@eng.auburn.edu bstract Leakage power s becomng a domnant contrbutor to e total power consumpton and dual- assgnment s an cent technque to decrease leakage power, for whch ectve desgn meods have been proposed. However, due to e exponental relaton of subreshold current w process parameters, such as, e ectve gate leng, oxde ckness and dopng concentraton, process varatons can severely affect bo power and tmng yelds of e desgns obtaned by ose meods. n s paper, we propose a mxed nteger lnear programmng meod for dual- desgn at mnmzes e leakage power and crcut delay n a statstcal sense such at e mpact of process varaton on e respectve yelds s mnmzed. The expermental results show at 3% more leakage power reducton can be acheved by usng statstcal approach when compared w e determnstc approach.. ntroducton W e contnung trend n e MOS technology scalng, leakage power s becomng a domnant contrbutor to e total power consumpton. To reduce leakage power, many technques have been proposed, ncludng transstor szng, mult-, dual-, optmal standby nput vector selecton, dual-, transstor stackng, and body bas. ual- assgnment [-6, 7-9,, ] s an cent technque for leakage reducton. Tradtonal determnstc approaches for dual-reshold assgnment [-6,, ] to mnmze e leakage power utlze e tmng slack of noncrtcal pas to assgn hgh to some or all gates on ose pas to decrease e leakage. These approaches can be dvded nto two groups: heurstc algorms [-4] and lnear programmng [5, 6,, ]. Unlke a heurstc algorm at can only guarantee a locally optmal soluton, lnear programmng formulaton ensures a global optmzaton. However, e ncreased varaton of process parameters of nanoscale devces can cause a sgnfcant ncrease n e leakage current because of an exponental relaton between e leakage current and some key process parameters. Gate leakage s most senstve to e varaton n oxde ckness (T ox ). The subreshold current s extremely senstve to e varaton n oxde ckness (T ox ), ectve gate leng (L ) and dopng concentraton (N dop ). ompared w e gate leakage, e subreshold leakage s more senstve to parameter varatons []. Twenty percent varatons n ectve channel leng and oxde ckness can cause up to 3 and 5 tmes dfferences, respectvely, n e amount of subreshold leakage current. Gate leakage can have 8 tmes dfference due to a % varaton n oxde ckness. araton of process parameters not only affects e leakage current but also changes e gate delay, degradng eer one or bo, power and tmng yelds of an optmzed desgn. To mnmze e ect of process varaton, some technques [7-9] statstcally optmze e leakage power and crcut performance by dual- assgnment. Leakage current and delay are treated as random varables. dynamc programmng approach for leakage optmzaton by dual- assgnment has been proposed [7] usng two prunng crtera at stochastcally dentfy pareto-optmal solutons and prune e sub-optmal ones. noer approach [9] solves e statstcal leakage mnmzaton problem usng a eoretcally rgorous formulaton for dual- assgnment and gate szng. Our work s motvated by e above research. mxed nteger lnear programmng (MLP) model s proposed to mnmze leakage power w specfed tmng yeld under process varaton. Ths MLP meod s specfcally devsed w a set of constrants whose sze s lnear n e number of gates. lough eoretcal worst-case complexty of MLP s exponental, our expermental results show at actual complexty depends on e nature of e problem. To deal w e complextes of delay models and leakage calculaton, two look up tables for e nomnal delay and leakage current are pre-constructed for each cell. Ths greatly smplfes e optmzaton procedure. Expermental results show at 3% more reducton of leakage power can be acheved by usng e statstcal approach when e result s compared to a determnstc approach. Ths paper s organzed as follows. Secton presents a determnstc lnear programmng formulaton. Secton 3 onference Proceedngs: LS esgn - 6 Embedded Systems, January 7. opyrght 7 by The nsttute of Electrcal and Electroncs Engneers, nc. ll rghts Reserved.

2 dscusses e statstcal leakage and gate delay modelng, and proposes a statstcal lnear programmng meod for leakage mnmzaton under process varaton. n Secton 4, expermental results are presented and dscussed. concluson s gven n Secton 5.. etermnstc ual- LP n e determnstc approach, e delay and subreshold current of every gate are assumed to be fxed and wout any ect of e process parameter varaton. ascally, s type of meods can be dvded nto two groups: heurstc algorms [-4] and lnear programmng [5-6,, ]. Heurstc algorms gve a locally optmal soluton and lnear programmng formulaton ensures a globally optmum soluton. n LP at optmzes e leakage power and assgns dual- to gates n one step [, ] has an advantage over an teratve procedure [5], whch must assume power-delay senstvtes to be constants n a small range. Fgure gves e basc dea of e LP meod [, ] to mnmze total subreshold leakage whle keepng e crcut performance by dual- assgnment. subnom, Mnmze gate number Fgure. asc dea of LP for leakage mnmzaton Subject to T POk T k PO max Fgure. asc dea of usng LP to optmze leakage. Mnmze { subnom, L, + ( ) subnom, H, } Fgure. etaled determnstc LP formulaton for leakage mnmzaton. detaled verson for e LP formulaton s presented n Fgure. s an nteger at can only be eer or. value means at gate s assgned low, and means at gate s assgned hgh. T s e latest arrval tme at e output of gate. Each gate n e desgn lbrary w low and hgh reshold versons s characterzed for ts leakage n varous nput states and gate delay, whch also depends on e fanout number, usng Spce smulaton. 3. Statstcal ual- ssgnment Process varatons nclude nter-de and ntra-de varatons, or global and local varatons. For nter-de (-O) Subject to = nom, L, + ( ) nom, H, (-) T Tj + j fann of gate (-) = or (-3) T POk T max k PO (-4) varatons, e determnstc and statstcal approaches are exactly e same. Snce our objectve s to have a statstcal LP formulaton at enhances e determnstc approach to leakage optmzaton under process varatons, we gnore e nter-de varaton. n e remander of s paper, process varaton wll only mean ntra-de varaton. Leakage current s composed of reverse based PN juncton leakage, gate leakage and subreshold leakage. n a sub-mcron process, PN juncton leakage s much smaller an e oer two components. Gate leakage s most senstve to e varaton n T ox and changes n e gate leakage due to oer process parameter varatons can be gnored []. Furer, assumng T ox to be a well-controlled process parameter [4, 5], we gnore e gate leakage varaton n our desgn, focusng only on changes n e subreshold leakage due to process varaton. ue to e exponental relaton of subreshold current w process parameters, such as, e ectve gate leng, oxde ckness and dopng concentraton, process varaton can severely affect bo power and tmng yelds of a desgn obtaned by a determnstc meod. ecause fxed subreshold leakage and gate delay do not represent e real crcut condton, statstcal modelng should be used. Ths s dscussed next. 3. Statstcal Subreshold Leakage Modelng Subreshold current has an exponental relaton w e reshold voltage, whch n turn s a functon of oxde ckness, ectve channel leng, dopng concentraton, etc. T ox s a farly well-controlled process parameter and does not sgnfcantly nfluence subreshold leakage varaton [4, 5]. Therefore, we only consder varatons n L and N dop. The statstcal subreshold model can be wrtten as [5]: L, nom exp + c LL + c3, Ndop sub = sub () c Where, L s e change n e ectve channel leng due to e process varaton and,ndop s e change n e reshold voltage due to e random dstrbuton of dopng concentraton, N dop. o are random varables w a normal dstrbuton, N(,). Fttng parameters c, c and c 3 are determned from Spce smulaton. From equaton (), t s obvous at sub has a lognormal dstrbuton. The total leakage current n a crcut, whch s e sum of subreshold currents of ndvdual gates, has an approxmately lognormal dstrbuton. Rao et al. [5] use e central lmt eorem to estmate s lognormal dstrbuton by ts mean value w e assumpton at ere s a large number of gates n e crcut, whch ndeed s e case for most present day chps. Hence, e total leakage can be expressed as: onference Proceedngs: LS esgn - 6 Embedded Systems, January 7. opyrght 7 by The nsttute of Electrcal and Electroncs Engneers, nc. ll rghts Reserved.

3 sub, total= sub, E sub, = SL S subnom, () Where, S L = λ + λ L exp λ + 4 L L λ λ (3) λ 3 =, Ndop S exp (4) λ S L and S are scale factors ntroduced due to local varatons n L and,ndop. λ, λ and λ 3 are fttng parameters. For a gven process, L and,ndop are predetermned. Therefore, n our statstcal lnear programmng formulaton, e objectve functon s a sum of all nomnal subreshold leakage currents, multpled by scale factors, S L and S. 3. Statstc elay Modelng The determnstc gate delay s gven by [3]: dd (5) ( ) α dd where α equals.3 for e short channel model. Smlar to e subreshold current model, e devaton due to e process parameter varaton s also a consderaton n our statstcal delay model. The change of due to e varaton of process parameters can be expressed as [7]: = β (6) where s a process parameter, s e nomnal value of, and β s a constant for e specfc technology. To get an approxmated lnear relaton between and e varatons of e process parameters, equaton (5) s expanded nto a Taylor seres (7) n whch only e frst order term s retaned because hgher orders terms are relatvely small and can be gnored. (... d =,, ) + ( ) (7),,... d Let {,, 3 } = {L, T ox, N dop }. ombnng equatons (6) and (7), we get: L T N ox dop = nom, c c c 3 (8) L Tox Ndop where, c, c, and c 3 are senstvtes of gate delay w respect to e varaton of each process parameter and can be acqured from Spce smulaton. L, T ox and N dop are normal N(,) random varables. Therefore, n statstcal analyss, becomes a random varable, whch also has a normal dstrbuton. Let L T N ox dop = c + c + c3, (9) L Tox N dop r Equaton (8) becomes: ( r ) = + nom, () ecause r s a normal N(,) random varable,, e mean value of, s equvalent to nom, e nomnal delay of gate. 3.3 Statstcal ual- ssgnment LP n statstcal approach to mnmze leakage power by dual- assgnment (Fgure 3), e delay and subreshold current are bo random varables, and η s e expected tmng yeld. The power yeld s not consdered because n Secton 4 (Results) we wll fnd at e statstcal approach can get about 3% addtonal leakage power reducton for most crcuts compared to e determnstc approach. Mnmze Fgure 3. asc LP for statstcal dual- assgnment. n Fgure 3, T PO s e pa delay from prmary nput to e prmary output and s assumed to have a normal (Gaussan) dstrbuton N( TPO, TPO). nequalty () allows leakage to be optmzed w tmng yeld η and t can be expressed nto a lnear format by e percent pont functon Φ - [6]: T PO + sub, total () P T PO T max () Subject to ( ) η ( η) Tmax PO Φ (3) n statstcal lnear programmng (Fgure 4) all varables, except, are random varables w normal dstrbuton. omparng e determnstc LP (Fgure ) and statstcal LP (Fgure 4), we observe e followng dfferences: The determnstc gate delay n (-) s extended to (S-) and (S-) to get e mean and standard devaton of e statstcal delay. (-) s extended to to (S-3) rough (S-6) to get e mean and standard devaton of e statstcal arrval tme T at e output of gate. onference Proceedngs: LS esgn - 6 Embedded Systems, January 7. opyrght 7 by The nsttute of Electrcal and Electroncs Engneers, nc. ll rghts Reserved.

4 (-4) s updated to (S-8) to ensure certan tmng yeld under process varaton. Mnmze S L = S S L S Fgure 4. etaled formulaton of statstcal dual- assgnment LP. 3.4 Lnear pproxmatons n lnear programmng, all e expressons and constrants should be lnear functons. However, n statstcal analyss, some nonlnear operatons are present. We, erefore, use lnear approxmatons., = + Subject to f and are N(, ) random varables, en er sum also has a normal dstrbuton. dd s a lnear functon, but n statstcal analyss, to obtan e standard devaton, we must deal w = +, whch s a nonlnear operaton. onsderng, ( + ) { + ( ) H } subnom, L, subnom,, subnom, gate number + ( + ) one can fnd a lnear approxmaton [9, ]: gate number = + = k( + ) w k [,] ( ) nom, H nom, L, +, (S-O) = (S-) = (S-) r j fan n of gate (S-3) + T Tj Tj, = k( Tj + ) (S-4) temp + + 3, T (S-5) Tj T ( temp T T ) /3 Tj = (S-6) = or (S-7) k PO T POk + Φ ( η) Tmax PO (S-8) k M, = M(, ) f and are N(, ) random varables, does not necessarly have a normal dstrbuton [7, 8]. However, a normal approxmaton w followng mean and standard devaton has been used [9, ]: = max(, ) (4) { max( + 3, + 3 ) }/ 3 = (5) The error n s approxmaton has been shown to be small [9, ]. M, = M(+, +) Smlarly, for functon =Max(+,+), we use (6) and (7) to estmate e mean value and standard devaton of random varable. = max(, ) + (6) { max( + + 3, ) }/ 3 = (7) The above lnear approxmatons are used n our statstcal analyss to model e leakage optmzaton problem under process varaton by a lnear programmng formulaton. 4. Results We use e PTM 7nm MOS technology []. Low for NMOS and PMOS are. and -., respectvely. Hgh for NMOS and PMOS are.3 and -.34, respectvely. We regenerated e netlsts of SS 85 benchmark crcuts usng a cell lbrary n whch e maxmum gate fann s fve. Two look-up tables for nomnal gate delays and nomnal leakage currents, respectvely, for each type of cell were constructed usng Spce smulaton. program parsed e netlst and generated e constrant set for e PLE LP solver n e MPL software package []. PLE en gave e optmal assgnment as well as e mnmzed leakage current for e crcut. 4. omparson of Leakage Power Reducton by etermnstc and Statstcal Meods To compare e power optmzaton results of e statstcal LP w ose from e determnstc approach, we assume at all e gates have e same c, c and c 3 (senstvtes of gate delay to e varaton of dfferent process parameters) n equaton (8). Therefore, each gate has e same r. (= /u ). We assume t to be %. Ths assumpton s only for e smplcty and does not change e cacy of e statstcal approach. n Table, columns 4, 6 and 9 gve e optmzed leakage power by determnstc LP, by statstcal LP w 99% tmng yeld and by statstcal LP w 95% tmng yeld. onference Proceedngs: LS esgn - 6 Embedded Systems, January 7. opyrght 7 by The nsttute of Electrcal and Electroncs Engneers, nc. ll rghts Reserved.

5 Table. omparson of leakage power savng due to statstcal modelng w two dfferent tmng yelds (η). rcut etermnstc Optmzaton (η =%) Statstcal Optmzaton (η =99%) Statstcal Optmzaton (η =95%) Name # gates Unoptmzed Leakage Power (W) Optmzed Leakage Power (W) Run Tme (s) Optmzed Leakage Power (W) Extra Power Savng Run Tme (s) Optmzed Leakage Power (W) Extra Power Savng Run Tme (s) % % % % % % % % % % % % % % % % % %.58 verage of SS 85 benchmarks.4 9.% % 4.64 RM7 5.5k % % From Table, we see at compared to e determnstc meod, whch uses e fxed values, when we use statstcal models for gate delay and subreshold leakage current, SS85 benchmarks can acheve on average 9% greater leakage power savng w 99% tmng yeld and 4% greater power savng w 95% tmng yeld. The reason s at statstcal model has a more flexble optmzaton space, whle e determnstc approach assumes e worst case. For c499 and c355, whch have many crtcal pas due to er extremely symmetrcal crcut structures, e optmzaton space s lmted and erefore e addtonal power savng contrbuted by optmzaton s much smaller, especally w e hgher tmng yeld (99%). Normalzed Leakage Power etermnstc LP Statstcal LP ( 99% Tmng Yeld) Statstcal LP ( 95% Tmng Yeld) Normalzed Tmng Fgure 5. Power-delay curves of determnstc and statstcal approaches for 43. t s also obvous at w a decreased tmng yeld, hgher power savng can be acheved due to e relaxed tmng constrants, resultng n larger optmzaton space. Fgure 5 shows e power-delay curves for 43 for determnstc and statstcal approaches. The startng ponts of e ree curves, (,), (,.65) and (,.59), ndcate at f we can reduce e leakage power to some unt by determnstc approach,.65 unt and.59 unt leakage power can be acheved by usng statstc approach w 99% and 95% tmng yelds, respectvely. Lower e tmng yeld, hgher s power savng. W a furer relaxed T max, all ree curves wll gve more reducton n leakage power because more gates wll be assgned hgh. 4. Run Tme of MLP lgorm The run tme of LP s always a bg concern snce ts complexty s exponental n e number of varables and constrants of e problem n e worst case. However, our expermental results show at e real computng tme may depend on e crcut structure, logc dep, etc., and may not be exponental. Runnng on a.4ghz M Opteron 5 processor w 3G memory, many PU run tmes for solvng e LP problem were less an one second (columns 5, 8 and n Table ). Ths s an advantage over oer technques [9] because we acheve 3% more leakage reducton w 99% tmng yeld but n much less PU tme. onference Proceedngs: LS esgn - 6 Embedded Systems, January 7. opyrght 7 by The nsttute of Electrcal and Electroncs Engneers, nc. ll rghts Reserved.

6 esdes SS 85 benchmark crcuts, we also optmzed e leakage for an RM7 P core, whch has 5.5k combnatonal cells and.4k sequental cells mplemented n TSM 9nm MOS process. The expermental results n e last row of Table show 4% more leakage reducton acheved w 37 seconds run tme and partly demonstrate e feasblty of applyng our MLP approach to real crcuts. lough today's SO may have over one mllon gates, t always has a herarchcal structure. LP constrants can be generated for submodules at a lower level and e run tmes wll be determned by e number of gates n e ndvdual submodules. Such a technque may not guarantee a global optmzaton, but stll would get a reasonable result wn acceptable run tme. 5. oncluson mxed nteger lnear programmng formulaton to statstcally mnmze e leakage power n a dual- process under process varatons s proposed n s paper. The expermental results show at 3% more leakage power reducton can be acheved by usng s statstcal approach compared w e determnstc approach. n e statstcal approach, e mpact of process varaton on leakage power and crcut performance s smultaneously mnmzed when a small yeld loss s permtted. cknowledgment uors are grateful for assstance from nalog evces. 6. References [] M. Ketkar and S. S. Sapatnekar, Standby Power Optmzaton va Transstor Szng and ual Threshold oltage ssgnment, Proc.,, pp [] L. We, Z. hen, M. Johnson and K. Roy, esgn and Optmzaton of Low oltage Hgh Performance ual Threshold MOS rcuts, Proc., 998, pp [3] L. We, Z. hen, K. Roy, Y. Ye and. e, Mxed- (MT) MOS rcut esgn Meodology for Low Power pplcatons, Proc., 999, pp [4] Q. Wang, and S.. K. rudhula, "Statc Power Optmzaton of eep Submcron MOS rcuts for ual T Technology," Proc,, 998, pp [5]. Nguyen,. avare, M. Orshansky,. hnney,. Thompson, and K. Keutzer, Mnmzaton of ynamc and Statc Power Through Jont ssgnment of Threshold oltages and Szng Optmzaton, Proc. SLPE, 3, pp [6] F. Gao and J. P. Hayes, Gate szng and t ssgnment for ctve-mode Leakage Power Reducton, Proc., 4, pp [7]. avood and. Srvastava, Probablstc ual- Optmzaton Under arablty, Proc. SLPE, 5, pp [8]. Srvastava,. Sylvester,. laauw, Statstcal Optmzaton of Leakage Power onsderng Process aratons Usng ual- and Szng, Proc., 4, pp [9] M. Man,. evgan and M. Orshansky, n Effcent lgorm for Statstcal Mnmzaton of Total Power Under Tmng Yeld onstrants, Proc., 5, pp [] S. Mukhopadhyay and K. Roy, Modelng and Estmaton of Total Leakage urrent n Nano-Scaled MOS evces onsderng e Effect of Parameter araton, Proc. SLPE, 3, pp [] Y. Lu and.. grawal, Leakage and ynamc Gltch Power Mnmzaton Usng nteger Lnear Programmng for ssgnment and Pa alancng, PTMOS, 5, pp [] Y. Lu and.. grawal, MOS Leakage and Gltch Power Mnmzaton for Power-Performance Tradeoff, Journal of Low Power Electroncs, vol., no. 3, ecember 6. [3] T. Sakura and. R. Newton, lpha-power Law MOSFET Model and ts pplcatons to MOS nverter elay and Oer Formulas, EEE Journal of Sold-State rcuts, vol. 5, no., pp , February 99. [4] R. Rao,. Srvastava,. laauw and. Sylvester, Statstcal nalyss of Subreshold Leakage urrent for LS rcuts, EEE Transactons on LS Systems, vol., no., Feb. 4, pp [5] R. Rao,. evgan,. laauw and. Sylvester, Parametrc Yeld Estmaton onsderng Leakage arablty, Proc., 4, pp [6] M. Man and M. Orshansky, New Statstcal Optmzaton lgorm for Gate Szng, Proc., 4, pp [7] E. T.. F. Jacobs and M. R.. M. erkelaar, Gate Szng Usng a Statstcal elay Model, Proc. TE,, pp [8]. E. lark, The Greatest of a Fnte Set of Random arables, J. Operatons Research Soc. merca, vol. 9, pp. 45-6, 96. [9] F. Hu, Process-araton-Resstant ynamc Power Optmzaton for LS rcuts, Ph ssertaton, ept. of EE, uburn Unversty, uburn, labama, May 6. [] F. Hu and.. grawal, nput-specfc ynamc Power Optmzaton for LS rcuts, Proc. SLPE, 6, pp [] R. Fourer,. M. Gay, and. W. Kernghan, MPL: Modelng Language for Maematcal Programmng. Sou San Francsco, alforna: The Scentfc Press, 993. [] PTM: erkeley Predctve Technology Model. See onference Proceedngs: LS esgn - 6 Embedded Systems, January 7. opyrght 7 by The nsttute of Electrcal and Electroncs Engneers, nc. ll rghts Reserved.