Run-time Active Leakage Reduction By Power Gating And Reverse Body Biasing: An Energy View

Transcription

1 Run-tme Actve Leakage Reducton By Power Gatng And Reverse Body Basng: An Energy Vew Hao Xu, Ranga Vemur and Wen-Ben Jone Department of Electrcal and Computer Engneerng, Unversty of Cncnnat Cncnnat, Oho Emal: {xuho, ranga, Abstract Run-tme Actve Leakage Reducton (RALR) s a recent technque and ams at aggressvely reducng leakage power consumpton. Ths paper studes the feasblty of RALR from the energy aspect, for both power gatng (PG) and reverse body bas (RBB) mplementatons. We develop two energy savng models for PG and RBB, respectvely. These models can accurately estmate the crcut energy savng at any tme, even when the crcut s n state transton. In PG modelng, we dscover a physcal phenomenon called nstant savng, whch can affect the model accuracy by 3%-5%. Based on the RBB model, we derve the optmum desgn pont of RBB for RALR. Fnally n terms of energy savng, we defne four fgures-of-mert, to compare the effcacy of usng PG and RBB to mplement RALR. I. INTRODUCTION MOSFET scalng nto deep sub--nm has resulted n sgnfcant ncrease n leakage power consumpton. Partcularly, n 45nm technology generaton and beyond, leakage power consumpton wll catch up wth, and may even domnate, dynamc power consumpton []. Ths makes leakage power reducton an ndspensable component n nano-era low power desgn. Subthreshold leakage, gate leakage and band-to-band tunnelng leakage (BTBT) are the three man components contrbutng to the total leakage power. Many leakage reducton technques have been ntroduced and studed so far. They can be characterzed nto two classes: run-tme technques and desgn-tme technques. The run-tme technques, such as reverse body basng, nput vector control and power gatng [2], tune the crcut nto a lower-leakage state durng run-tme, based on the crcut workload varaton. Currently, most of the run-tme technques change the crcut state only when they are n standby mode. However as the technology scales down, more aggressve leakage reducton technques are requred. As a promsng technque, run-tme actve leakage power reducton (RALR) has drawn more attenton recently [3-7]. As shown n Fgure, the RALR swtches the crcut nto a low-leakage state once t detects suffcent dleness n crcut workload, even when the crcut s n the actve mode. In ths way, t s able to explot more crcut slackness, and thus reduce more leakage power. Furthermore, because the leakage n the actve mode s sgnfcantly larger due to the hgher de temperature n actve mode [3], the study of RALR s even more mportant. Energy overhead of state transtons has always been a major concern of power management systems. Snce RALR swtches the crcut state more frequently, t ncurs more INPUT LOGIC BLOCK WORKLOAD Standby Actve LEAK. CONTROL CONTROL Tradtonal Run-tme Leakage Reducton WORKLOAD MONITOR CONTROL Actve Mode Leakage Reducton Fg.. Actve Mode Leakage Reducton energy overhead. Hence, to guarantee RALR s effectveness, desgners need to make sure the leakage energy savng by applyng the RALR s larger than the overhead. Ths has been dentfed as the key desgn problem of RALR n [4], [5]. To ths end, an accurate leakage energy savng model (E s (t)) asa functon of tme s requred. Tradtonally, the smplest way to estmate E s (t) s to assume that the crcut leakage s reduced by a constant rato R, at any tme after the crcut enters ts low-leakage state. Wth ths assumpton, t yelds: E s (t) =I leak ( R)t () where I leak s the crcut leakage current n the normal state. Equaton s used n many researches. However, t s evdent that leakage reducton s not an mmedate effect. Crcut state transton usually requres capactance chargng or dschargng, whch takes tme. For example, Fgure 2.a shows the dagram of applyng ground power gatng (PG) to an nverter. After the control sgnal swtches off the power gate, the nternal node capactance s charged up by the leakage current. In return, the subthreshold leakage and gate leakage reduce, because of smaller V ds. Fgure 2.b shows the dagram of PMOS reverse I sub Vrutal Ground Control Voltage P Substrate Voltage Vrutal Ground Control I I Sub Sub t t a. Ground Power Gatng b. PMOS Reverse Body Bas Fg. 2. Leakage Reducton Process of Power Gatng and Reverse Body Bas body basng (RBB). After the control sgnal connects the body voltage to the bas voltage, the P substrate capactance s gradually charged up by the bas voltage. The subthreshold leakage then reduces because of large V bs. (BTBT leakage also ncreases [6].) Thus n both cases, nstead of beng a constant, the leakage reducton rato R ncreases gradually after the crcut transton. Consequently, usng Equaton ntroduces error durng the crcut state transton and s an optmstc energy savng model. I sub Bas

2 For leakage reducton technques used n standby mode, ths error s neglgble snce the crcut downtme s long. However for RALR, the crcut downtme s usually short and the state transton happens frequently. In ths case, ths error s not neglgble. Accurate estmatons of energy savng, even when the crcut s n state transton, are essental to make desgn trade-offs for RALR. Some recent researches have consdered ths error. Yu et al. [3] multply the leakage energy savng of PG wth an emprcal value (.73) to justfy ths error. In [7] and [5], Hu et al. and Usam et al. derve energy savng models of PG factorng n the varaton of R. Smlarly n [4], Tsa et al. derve an energy savng model for RBB, consderng the substrate chargng process. However, the models n [3], [7], [5], [4] do not consder the mpact of crcut topology and nput vectors. Snce leakage has a strong dependency on the nput vectors [], ther models are rather hgh level and cannot be used when accurate estmatons are necessary. In [8], we have developed a method to estmate the dynamc vrtual ground voltage of PG. In ths paper, based on the results of [8], we derve two accurate energy savng models for PG and RBB, respectvely. Gven a specfc crcut topology and nput vector, these two models can gve accurate estmaton on energy savng, even when the crcut s n state transton. In order to compare the effcacy of PG and RBB, we defne four fgures-of-mert n terms of energy savng. These four propertes can be used to study other technques as well. Ths paper s organzed as follows. Secton II and III derves the energy savng model for PG and RBB, respectvely. Secton IV defnes four fgures-of mert and use them to compare PG and RBB. Secton V shows the expermental results to verfy our models and gan observatons. Fnally, Secton VI concludes the paper. II. ENERGY SAVING MODEL OF PG In ths secton, we derve an accurate energy savng model of PG based on the results of [8]. We focus on the ground gatng only. Supply gatng can be studed n a smlar way. In the study of PG, we only consder the sub-threshold leakage and refer to t as leakage [8]. As llustrated n Fgure 2, when ground gatng s appled, the energy overhead (E F ) for swtchng the footer s: E F = C F 2 (2) where C F s the gate capactor of the footer. Assumng that after the footer s off, the leakage current s (I(t)), and the orgnal leakage current wthout PG s Î, we then have the energy savng model at any tme t: E PG (t) = C F 2 + V DD (Î I(t))t (3) To quantfy the leakage current varaton (I(t)), we frst study three major physcal phenomena that occur after the crcut ground s gated. A. Phenomenon : Chargng of Internal Nodes After the crcut ground s gated, the leakage current starts to charge up the nternal nodes. By assumng that the footer leakage s I F (t), and the total nternal node capactor s C nt, ths chargng process can be characterzed by: V nt (t) = t (I(t) I F (t))dt (4) C nt where V nt (t) s the nternal node voltage. Ideally, V nt (t) should be equal to the vrtual ground voltage. In fact, t can be dfferent at nternal nodes, due to the non-deal conductvty of transstors. However, we approxmate V nt (t) nto to the vrtual ground voltage V VG (t), and transform C nt nto equvalent capactance that attached to the vrtual ground. The composton of C nt wll be dscussed n Secton II.C. B. Phenomenon 2: Subthreshold Leakage Reducton As the nternal node voltage ncreases, the voltage dfferental applyng to each transstor n the crcut reduces. As a result, the second physcal phenomenon s the leakage reducton of each transstor. [] gves the sub-threshold leakage current equaton for a sngle off-state transstor: I = A e /mvt (VG VS V th γ V S+ηV DS) ( e VDS/vT ) wth A = µ C W ox (v T ) 2 c.8 c V th/ηv T (5) L eff where V th s the zero bas threshold voltage, v T s the thermal voltage, γ s the lnearzed body effect coeffcent, and η s the DIBL coeffcent. Equaton 5 can be used to calculate the leakage reducton of each transstor. At the gate level for any complex gate, [8] has proven that the total leakage (I gate ) of the gate can be approxmated nto a sngle exponental functon of ts vrtual ground voltage (V VG ). I gate Îe KgateVV G (6) where K gate s the leakage reducton exponent of the gate, and Î s zero-v VG leakage current. C. Phenomenon 3: Crcut Self-dschargng Ths phenomenon s not explaned n [8]. However, t s crtcal for energy savng estmaton, snce t can affect the accuracy by 3%-5%. The capactance n the crcut can be categorzed nto four types: gate capactance (C g ), NMOS dffuson capactance (C dn ), PMOS dffuson capactance (C dp ) and parastc capactance (C p ). For C dn and C p, the ncrease of nternal nodes voltage s a chargng process. On the contrary, for gate capactance C g and PMOS dffuson capactance C dp, ths ncrease results n a dschargng process. For example, Fgure 3 shows all the capactances of a ground gated nverter wth nput. C dn, C p and footer dffuson capactance C df are essentally connected between the vrtual ground and the real ground. We call them groundcapactance. C dp, C gn and C gp are connected between the vrtual ground and the. We call them Selfcapactance. When the vrtual ground voltage ncreases, the voltage potentals of the ground-capactance ncrease, whle the voltage potentals of self-capactance decrease. Thus, after the ground s gated, the ground-capactance s charged, and at the same tme the self-capactance dscharges.

3 C gp C gn V VG C dp C dn C dn+c df C p V VG C gn+c gp+c dp C dn +C df +C p I dscharge I dscharge I vdd I charge Fg. 3. Capactance of A Ground Gated Inverter The dscharge current (I dscharge ) of the self-capactance flows through the off-state PMOS, together wth the leakage current (I ) from V DD. Snce the maxmal current that can flows through PMOS s lmted to of PMOS, we have: = I + I dscharge (7) Smlarly for the chargng current (I charge ) of the groundcapactance, we have: = I charge + I dscharge (8) From Equaton 7 we can observe that the dscharge current occupes a porton of and essentally reduces the leakage current from V DD. Thus, rght after the crcut ground s gated, the crcut leakage current I s mmedately reduced by: R = I I dscharge = (9) I charge + I dscharge We call ths mmedate reducton as nstant savngs of PG. The rest part of the leakage current reduces gradually wth the ncrease of vrtual ground voltage. We call t gradual savngs of PG. Thus, unlke the tradtonal understandng of PG, a sgnfcant amount of leakage energy can be saved rght after PG s appled, as shown n Fgure 4. I Instant Savng Gradual Savng I V Ground Gated t Fg. 4. Instant Savng and Gradual Savng of PG Furthermore, for the chargng process of the groundcapactance (C g )wehave: { dv I charge = C VG g dt () C g = C dn + C df + C p For the chargng process of the self-capactance (C s ): { dv I dscharge = C VG self dt () C s = C dp + C gn + C gp Equatons, and 9 together yelds: I dscharge C s R = = (2) I charge + I dscharge C s + C g Conclusvely, as demonstrated n Fgure 3, a ground gated crcut can be consdered as a self-capactor and a groundcapactor. The dschargng current of the self-capactor occupes a sgnfcant porton of the leakage current capacty of the crcut, and thus causes an nstant reducton on the leakage current from V DD by R (Equaton 2). We call ths phenomenon as Crcut Self-dschargng. Expermental results shows that ths physcal phenomenon can affect the energy savng estmaton by 3% to 5%, dependng on the values of C s and C g. DD D. Energy Savng Model of PG Based on the prevous analyss, we model a ground-gated crcut as shown n Fgure 5. The leakage current of each gate () and the footer s modeled as a sngle V VG -controlled current source I. All the self-capactances (C s ) of each gate are lumped together as C s (C s = C s ). And all the groundcapactances (C g ) are lumped together as C g (C g = C g ). C s Fg. 5. I footer I C g V VG Model of A Ground Gated Crcut The gate coeffcents C s, C g, K and Î (Equaton 6) should be characterzed at the gate level, for each gate type and each possble nput vector. Fgure 6 llustrates a coeffcent table of AND3. Once the coeffcent tables are created, gven a crcut topology wth a partcular nput vector, we can buld the above crcut model, usng the flow shown n Fgure 6. AND3 C g C s K I * * * * * * * * * * * * * * * * * * * * Crcut Topology Crcut State Logc Smulaton Technology Crcut Model of PG Energy Savng Model C ell Lbrary Gate Coef. Table Fg. 6. Gate Coeffcent Table And The Modelng Flow Next, wth the crcut model, we derve the leakage varaton model. In Fgure 5, apply KCL current law at V DD : I + I dscharge = = I = Î e K V VG I dscharge = (3) dv C VG s dt where I s the actual leakage current drawn from V DD. At the vrtual ground we have: I footer + I charge + I dscharge = I footer = ÎF e K F V VG I charge = (4) dv C VG g dt Equatons 3 and 4 can be smplfed nto: t V VG(t) = Cs + (I C g off(t) I footer (t))dt I off (t) = I = Î e K V VG (t) (5) I footer (t) =ÎF ek F V VG (t) Cg Cs I (t) = Cg + (t)+ C s Cg + I footer (t) C s (6) Solvng Equatons 5 yelds V VG (t), (t) and I footer (t). Then gven (t) and I footer (t), we can obtan the leakage current varaton I (t) usng Equaton 6. Fnally, gven I (t), we can obtan the energy savng model E PG (t) by: E PG (t) = C F V 2 DD + t V DD (Î I V DD (t))dt (7) Equatons 5 have no closed-form soluton. The detal of how to solve t s explaned n [8].

4 III. ENERGY SAVING MODEL OF RBB In ths secton, we derve an accurate energy savng model for RBB. In the followng, we use PMOS RBB as an example. NMOS RBB can be modeled n a smlar way. Body bas can be mplemented by charge bump crcutry [9], whch usually has sgnfcant chargng tme. In order to satsfy the crtcal tmng requrement of RALR, we use the V th hoppng scheme ntroduced n [2], where hgh-v th control transstors are nserted to swtch the substrate voltage between the normal value (V DD ) and the based value (V P ), as shown n Fgure 7. The szng of the control transstors are mportant. The sze V P V DD CONTROL P P2 CONTROL Pull-down Network Crcut Fg. 7. PMOS RBB Implementaton for RALR of the one (P ) controllng the bas voltage determnes the chargng speed of the substrate, and thus the leakage reducton speed. The sze of the one (P 2 ) controllng the normal voltage determnes the dscharge speed of the substrate, and thus the wake up tme. Ther szng wll be dscussed n Secton III.D. Here we derve a general energy savng model for all szes. Once the control sgnal of RBB s asserted, the energy overhead for swtchng the control transstor s: E C = C C VP 2 (8) where C C s the gate capactance of the control transstors (C C of P and C C2 of P 2 ). Note that the voltage of control sgnals should be V P, nstead of normal V DD. Next, we study three major physcal phenomena that occur after RBB s appled. A. Phenomenon : Substrate Chargng As soon as the control sgnal swtches the substrate to the bas voltage source, the bas voltage source starts to charge up the substrate, va the control transstor P. Assumng that the resstance of P s R, ths process can be characterzed by: V b (t) =(V P V DD )( e t R C b ) (9) where V b (t) s the ncrement of the P substrate voltage, and C b s the total capactance of the P substrates. C b conssts of two types of capactance: the capactance (C bv ) between P substrate and V DD and the capactance (C bg ) between P substrate and the ground. The chargng current to C bv and C bg has dfferent mpact. For example, Fgure 8 shows applyng RBB to an nverter wth nput. It can be modeled as a three-termnal devce, as shown on the rght sde. The chargng current (I bg )ofc bg drectly goes to the ground, I leak C bv C bg Bas Fg. 8. C bv C bg Substrate Chargng of RBB Bas whle the chargng current (I bv )ofc bv goes through the offstate PMOS and then reaches the ground. Smlar to the selfdschargng current n PG, ths I bv occupes a porton of the maxmum current ( ) that can leak through the crcut, and thus reduces the leakage current (I ) from V DD. However, I bv consumes energy of the bas voltage source. So unlke PG, no extra energy s saved n ths case n RBB. B. Phenomenon 2 and 3: Leakage Varaton Wth the ncrease of substrate voltage, the second phenomena n RBB s the reducton of the subthreshold leakage. It s formulated n [6] as: I sub = Îsube Bs V b (2) where Îsub s the subthreshold leakage under zero bas, and B s s a technology dependent parameter. V b s the ncrement of the substrate voltage V b. Meanwhle, the BTBT leakage ncreases [6]: I btbt Îbtbte Bt V b (2) where Îbtbt s the BTBT leakage under zero bas, and B t s a technology dependent parameter. Next, we study the leakage varaton of a gate when applyng RBB. Fgure 9 shows a large fan-n gate wth output for llustraton purpose. Its pull-down network s on, so the off-state PMOS n the pull-up network are the sources of leakage current. Assume that the pull-up network has four parallel branches, and n each branch there are four PMOS n seres. Wth a partcular nput vector, t has the on and off pattern as shown n the fgure. RBB changes the V b of all b V DD b 2 b 3 b 4 Pull-down Network V P PMOS RBB Leakage Current of A Complex Gate Fg. 9. the off-state PMOS to the same value. Thus usng Equaton 2 for each transstor n b,wehave: I = I e Bs V b = I b e Bs V b = I b I 2 = I 2e Bs V b = I b e Bs V b = I b I 3 = I 3e Bs V b = I b e Bs V b = I b (22) I 4 = I 4e Bs V b = I b e Bs V b = I b where I b and I b s the subthreshold leakage of b before and after RBB, respectvely. We can observe that the subthreshold leakage current of each branch s an exponental functon of V b. Now for the complex gate, we have: I gate = I b e Bs V b + I b2 e Bs V b + I b3 e Bs V b + I b4 e Bs V b =(I b + I b2 + I b3 + I b4 )e Bs V b =(Îgate)eBs V b (23) So the subthreshold leakage of the gate s also an exponental functon of V b. Furthermore, snce all the gates n the crcut

5 have the same exponent B s, the total subthreshold leakage of the whole crcut can be modeled as: I S = Î S e Bs V b (24) where ÎS s the zero-bas subthreshold leakage of each gate. Smlarly, the BTBT leakage of the whole crcut s: I T = Î T e Bt V b (25) where ÎT s the zero-bas BTBT leakage of each gate. C. Energy Savng Model of RBB Based on the prevous analyss, we model a body-based crcut as shown n Fgure. The leakage current of all gates n the crcut s lumped nto three V b -controlled current sources: subthreshold leakage I S, substrate to ground BTBT leakage I TG, and substrate to V DD BTBT leakage I TV. The substrate capactance of all gates s lumped nto two capactors: C bv (C bv = C bv ) and C bg (C bg = C bg ). Note that PMOS RBB only reduces the leakage of the gates whose pull-up network s off. For those gates wth pull-down network n off-state, NMOS RBB should be appled. However, snce the leakage of pull-down network does not change wth PMOS RBB, t s not ncluded n the crcut model. I S C bv C bg I TV V b R V P Hence, the leakage { current drawn from V DD s: I = IS ITV I bv I S = Î S e Bs V b (3) Makng all the currents as functons of tme, we have the energy consumpton of V DD at any tme t: t E (t) = V DD I (t)dt (32) Usng Equatons 8, 9, together wth 29 and 32, we have the overall energy savng model (E BB (t)) of RBB: E BB (t) =V DD (ÎS+ÎT )t C C VP 2 E bas (t) E (t) (33) where ÎS and ÎT are the total subthreshold and BTBT leakage current of the crcut wthout RBB, respectvely. D. Optmum Desgn Ponts for RALR In [6], the optmum value of bas voltage V P s determned by maxmzng the total leakage reducton rato. However, ths optmum value (OPT n Fgure ) s obtaned by assumng that the crcut stays n RBB mode for a long tme and the energy overhead (E b ) for chargng the substrate s not consdered. For RALR, snce the state transton occurs frequently, E b s not neglgble. As shown n Fgure, E b has a quadratc dependency on V P, whle the leakage energy reducton ncreases slowly wth V P when the substrate voltage s hgh enough. Thus, by countng n the energy overhead, there exsts another optmum V P (OPT2 n Fgure ) for RALR, at whch the net energy savng s maxmzed. Energy Substrate Chargng Overhead E b OPT2 OPT Total Leakage Energy Savng I TG Fg.. Model of PMOS RBB Crcut For a gven crcut n a partcular nput vector, the above crcut model s derved va a flow smlar to Fgure 6. A gate level coeffcent table for RBB needs to be bult as well, contanng I S, I TG, I TV, C bv and C bg of each gate. Next, wth the crcut model, we derve the energy savng model of RBB. The BTBT leakage currents n Fgure are: I TV = Î TV e Bt V b I TG = (26) Î TG e Bt V b where V b can be solved usng Equaton 9. The chargng currents of substrate capactance C bv and C bg are: { I bv = (V P V b )C bv R (C bv +C bg ) (27) I bg = (V P V b )C bg R (C bv +C bg ) Hence, the total current from the bas voltage V P to V DD s: I bas = I TV + I TG + I bv + I bg (28) Makng all currents as functons of tme, we have the energy consumpton of the bas voltage source at any tme t: t E bas (t) = V P I bas (t)dt (29) Now, applyng KCL current law at V DD n Fgure, we have: I + I TV + I bv = I S (3) V P OPT : Optmum V P wthout consderng E b OPT 2 : Optmum V P consderng E b Fg.. Optmum Bas Voltage of RBB To fully charged up the substrate, the energy overhead s: E b =(C bg + C bv ) VP 2 + C bg V DD V P (34) The leakage energy savng (E savng (t)) s: E savng(t) =(ÎS IS) t +(ÎT IT ) t =( e Bs V P )ÎSt +( e Bt V P )ÎT t (35) Assume that we want to archve the maxmal net energy savng at tme T, then the net energy savng (E net (t)) att s: E net (T )=E savng (T ) E b E C (36) From Equatons 34, 35 and 8, we can see that the above equaton s a functon of V P. The maxmal value of E net (T ) can be obtaned by solvng: E net (T ) = (37) V P The control transstor P also has an optmum szng. If P s desgned to be too small, then substrate chargng wll be slow and thus the leakage reducton wll be less effectve. If P s too large, then the swtchng overhead of P wll exceed the leakage savng. The optmum szng (Z )ofp can be determned as followng. R and C C n Equaton 33 and 9 can be consdered as functons of Z. Thus, Equaton 33 turns nto a functon of Z. If we want to archve the maxmal

6 energy savng at tme T, the optmum Z can be determned by solvng: E BB (T ) Z = (38) In the above analyss, T controls the crcut dleness that we want to optmze for. To optmze RBB for standby leakage reducton, T can be set to a large value. Otherwse for RALR, T can be set to a small value. Fgure 2 shows the V P values optmzed for dfferent T on benchmark crcut C355 n 65nm technology. When T s set to be suffcently large, the energy Optmum Vp (V) Optmum Vp for RALR Optmum Vp n [6] ms 6 Idle Tme T (ns) Fg. 2. Optmum Bas Voltage VS. Idle Tme T on C355 65nm overhead for state transton s neglgble. Hence the optmum V P s close to the optmum bas voltage n [6]. In Fgure 2, ths value s 3V. (The normal bas voltage s.9v.) Ths bas voltage yelds the optmum energy savng only when T s larger than 3ms. So t s not applcable for RALR. For RALR applcatons, for example when T s ns, The optmum V P s only.5v. IV. ENERGY SAVING COMPARISON OF PG AND RBB Snce RALR performs state transton more frequently, the technque that mplements t should have small energy overhead and quck leakage reducton ablty. To precsely compare the effcacy of PG and RBB, we defne four fguresof-mert of RALR. In order to compare PG and RBB, for each crcut, the T value of RBB n Equatons 37 and 38 s set to be the energy breakeven tme of PG. Energy breakeven tme s defned as the tme pont, at whch the leakage energy savng compensates the energy overhead consumed by state transton [5]. At the energy breakeven tme of PG, the net energy savng due to applyng PG s zero, whle we wll show n Secton V that the net energy savng due to applyng RBB can reach 8%. Thus, f RBB s optmzed for RALR, t s able to archve better energy savng than PG. The reasons why RBB has ths advantage are shown n the followng. ) Energy overhead The energy overhead of PG s caused by swtchng the footer: C F 2. For RBB, ths overhead has two components. One s for swtchng the control transstors: C C VP 2. The other s for chargng the substrate capactance: E b n Equaton 34. The values of C F, C C and C b and ther correspondng energy consumpton of benchmark crcut C355 s shown n Table I. We can observe that a) C C s usually very small because substrate chargng does not requre hgh current. b) Although C b s much larger than C F, E b s smaller than E F because C b s only charged up for.2v n ths case. c) In general, RBB has less overhead than PG f t s optmzed for RALR. TABLE I. ENERGY OVERHEAD OF PG AND RBB ON C355 BM. RBB V DD =.9v PG V P C C C b (ff) E c E b E total (E-5J) C F (ff) E F (E-5J) 32nm.8v nm.2v nm.v ) Current Injecton Speed Both PG and RBB essentally nject current to one of the transstor termnals and change the termnal voltage. Leakage current s then reduced as a result of termnal voltage changes. So the current njecton speed mpacts the energy savng speed. For PG, the subthreshold leakage current s njected nto the crcut and rases the nternal nodes voltages. Its njecton speed s controlled by the value of leakage current (I sub ). For RBB, the bas voltage source njects the current nto substrate. Its njecton speed s controlled by the value of on-current (I on ) of the control transstor (P ), whch s usually larger than I sub. However wth PG, as we descrbe n Secton II.C, the mportant phenomenon, crcut self-dschargng, causes nstant leakage reducton, and thus boosts ts energy savng. Accordng to our experments, ths nstant reducton can be 3% to 5%. Ths phenomenon partally compensates the slow current njecton speed of PG. 3) Leakage Reducton Rate Wth the change of transstor termnal voltages n the low-leakage state, the leakage current reduces. Accordng to Equaton 6, the PG leakage reducton rate reles on the exponent K. Accordng to Equaton 2, the RBB leakage reducton rate reles on B s. Hence K and B s represent the effcency of turnng current njecton to leakage reducton. Table II compares the K and B s for a sngle PMOS or NMOS. It can be observed that PG has a better leakage reducton rate than RBB does. TABLE II. LEAKAGE REDUCTION EXPONENT OF PG AND RBB 32nm(V th =.v) 45nm(V th =.6v) 65nm(V th =.8v) NMOS PMOS NMOS PMOS NMOS PMOS PG (K) RBB (B s) ) Stablzed Leakage Reducton Rato If the crcut stays n the low-leakage state for a long perod of tme, the fnal stablzed leakage value becomes crtcal for energy savng. For PG, ths stablzed value depends on the V th of the footer. For RBB, ths value depends on the value of the bas voltage V P. In our experments, snce V P s optmzed for RALR, the stablzed leakage reducton rato of RBB s only 3, whle PG s over 3. Increasng V P can further mprove the reducton rato. However, [] has ndcated that the effectveness of RBB s dmnshng wth technology scalng. In concluson, Table III compares the four fgures-of-mert of PG and RBB. It can be concluded from the table that RBB s sutable for short dleness explotaton due to lower overhead and faster current njecton speed, whle PG s more sutable

7 for long dleness explotaton due to ts hgh leakage reducton rate and stablzed leakage reducton rato. TABLE III. FOUR FIGURES-OF-MERIT OF PG AND RBB Short Term Long Term Energy Current Leakage Stablzed Leakage Overhead Injecton Speed Reducton Rate Reducton Rato PG Hgh Medum Hgh Hgh RBB Medum Hgh Medum Low V. EXPERIMENTAL RESULTS FOR PG AND RBB We conducted experments to compare our model estmates wth HSPICE smulaton results. The ISCAS85 benchmark crcuts n 32nm, 45nm and 65nm technologes [] are used n the experments. The gate level mplementaton and parastc nformaton of the benchmarks s from [2]. Each crcut s gven a partcular nput for all the experments. The smulaton temperature s set at C to emulate the runtme temperature. The gate leakage s set to be zero. Footers are nserted nto the benchmark crcuts to mplement ground gatng. The footer sze s desgned to be equal to the total NMOS wdth of the crcut. Snce the footer s large, t requres an non-neglgble drvng crcut. To emulate the energy overhead of the drvng crcut, we double the swtchng energy of the footer to be conservatve. The PMOS RBB s mplemented as llustrated n Fgure 7. The bas voltage and sze of the control transstors are set to enable the maxmum energy savng at the energy breakeven tme of PG. P and P 2 are of the same sze for smplcty. Smlar to PG, we double the swtchng energy of them. A. Model Verfcaton of PG For each benchmark crcut n three technologes, we smulated ts leakage energy consumpton at V DD after PG s appled. Then the smulaton data s sampled at 8 tme ponts and compared wth model estmates, as shown n Fgure 3. The worst case and average error of these 8 ponts are shown n Table IV. Our PG model has on the average 2.%, maxmally 6.7% error on the tme-varyng leakage energy consumpton estmaton. Ths accuracy guarantees the accuracy of energy savng estmaton. In order to verfy the self-dschargng phenomenon descrbed n Secton II.C, we also present the average error of energy savng estmaton wthout consderng self-dschargng ( No SD. n Table IV). The error can be as sgnfcant as 3% to 5%. Leakage Energy (E 5J) Fg Model Smulaton Tme After PG (ns) Leakage Energy Consumpton Estmates of PG on 32nm C7552 TABLE IV. ERROR % OF LEAKAGE ENERGY CONSUMPTION ESTIMATES OF PG BM. Gate 32nm 45nm 65nm Cnts. Max. Avg. NO SD. Max. Avg. NO SD. Max. Avg. NO SD. C C C C C C C C C C Overall 5.7% 2.% 4.4%.7% 6.7% 2.4% B. Model Verfcaton of RBB For RBB model verfcaton, we smulated the energy consumpton at V DD, as well as at the bas voltage V P. Then we sum them up to obtan the total energy consumpton. Table V shows our RBB model has on the average.3%, maxmally 5.5% error on the total energy consumpton estmaton. Fgure 4 llustrates the model versus smulaton for C7552. TABLE V. ERROR % OF TOTAL ENERGY CONSUMPTION ESTIMATES OF RBB Ckt. 32nm 45nm 65nm Ckt. 32nm 45nm 65nm % M. A. M. A. M. A. % M. A. M. A. M. A. C C C C C C C C C C Overall Total Energy (E 5J) Fg Model Smulaton Tme After RBB (ns) Total Energy Consumpton Estmates of RBB on 32nm C7552 C. Optmum Desgn Pont of RBB We conducted experments to verfy the optmum desgn ponts of RBB. Fgure 5 shows the total energy savng of 65nm C355 at 3.ns (energy breakeven tme of PG) wth dfferent bas voltage V P. As predcted by the model, settng V P as.v (V DD =.9v) yelds the maxmum energy savng. Total Energy Sang (E 5J) at 3.ns 5 5 Optmum Vp Model Smulaton Bas Voltage Vp (v) Fg. 5. RBB Optmum Bas Voltage on 65nm C355 at Idle Tme 3.ns Fgure 6 shows the total energy savng model as a functon of tme wth dfferent V P value. As can be observed, f V P value s smaller than.v (.v, the green lne), the overhead

8 s smaller but the leakage reducton s not effectve enough. If V P value s larger than.v (.2v-.4v), the leakage reducton s mproved. However the overhead wll be too hgh such that at 3.ns, ther net energy savng s less than usng.v. Total Energy Savng (E 5J) Fg v.v.2v 2.3v.4v Tme After RBB (ns) Total Energy Savng Model wth Dfferent V P on 65nm C355 D. Energy Savng Comparson of PG and RBB We conducted experments to compare the energy savng of PG and RBB for the same crcut wth the same nput vector. RBB s desgned to have maxmum energy savng at the energy breakeven tme pont of PG. Fgure 7 shows the comparson of 65nm C355. As shown, RBB has better energy savng ablty than PG before 9.ns, due to ts small energy overhead and fast charge njecton speed. However after 9.ns, the energy savng of PG catches up wth RBB, because PG has hgher stablzed leakage reducton rato. At the energy breakeven tme of PG (3.ns), the net energy savng of RBB s J, whch s 8% of the total leakage energy consumpton (4.2 3 J) untl 3.ns wthout RBB. Thus n ths case, the energy savng of RBB s 8%, whle the energy savng of PG s zero. Ths observaton demonstrates that by choosng the optmum desgn pont, RBB s more sutable than PG for short-term dleness explotaton. Total Energy Savng (E 5J) Fg PG Smulaton RBB Smulaton Tme After RALR (ns) Energy Savng Comparson of PG and RBB on 65nm C355 The energy breakeven tme of RBB n ths case s 5.8ns. Here we compare the energy breakeven tme of PG and RBB to llustrate the effcacy of them to mplement RALR. Table VI shows the comparson for each benchmark crcut. We can observe that RBB wth optmum desgn pont has 8% (32nm), 34% (45nm) and 52% (65nm) of mprovement on energy breakeven tme over PG. TABLE VI. ENERGY BREAKEVEN TIME (NS) OF PG AND RBB Ckt. 32nm 45nm 65nm Ckt. 32nm 45nm 65nm ns PG RBB PG RBB PG RBB PG RBB PG RBB PG RBB C C C C C C C C C C PG-RBB 8% 34% 52% When technology moves ahead, the advantage of RBB n RALR dmnshes (52% to 8%). Ths s because the subthreshold leakage ncreases sgnfcantly wth new technologes. It helps to mprove the current njecton rate of PG, and thus enables fast leakage reducton of PG. VI. CONCLUSION Ths study targets run-tme actve leakage reducton (RALR) n sub-65nm technologes. To ths end, we study both PG and RBB mplementatons from the energy perspectve. Ths paper has the followng three contrbutons: ) We develop an accurate energy savng model for any crcut at any tme after PG s appled, even when the crcut s n state transton. Durng the modelng, we dscover a physcal phenomenon called Crcut Self-dschargng, whch affects the model accuracy by 3%- 5% and can sgnfcantly change the tradtonal understandng of energy savng by applyng PG. 2) We develop another energy savng model for RBB. Based on the model, we derve the optmum desgn pont for RBB n RALR applcatons. 3) We defne 4 fgures-of-mert to quanttatvely analyze the effcacy of usng PG and RBB to mplement RALR. Theoretcal analyss based on the 4 fgures-of-mert and expermental results ndcate that PG has domnatng advantages over RBB n long dleness explotaton. Whereas f RBB s optmzed for RALR, t has the advantage of small energy overhead and faster charge njecton speed, whch makes RBB sutable for short dleness explotaton. However, ths advantage shrnks when the technology moves ahead. REFERENCES [] K. Roy, S. Mukhopadhyay, and H. Mahmood-Memand, Leakage current mechansms and leakage reducton technques n deepsubmcrometer cmos crcuts, Proc. IEEE, vol. 9, pp , Feb. 23. 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